amd/amdgpu/amdgpu_ras_eeprom.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _AMDGPU_RAS_EEPROM_H
0025 #define _AMDGPU_RAS_EEPROM_H
0026
0027 #include <linux/i2c.h>
0028
0029 struct amdgpu_device;
0030
0031 enum amdgpu_ras_eeprom_err_type {
0032     AMDGPU_RAS_EEPROM_ERR_NA,
0033     AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
0034     AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE,
0035     AMDGPU_RAS_EEPROM_ERR_COUNT,
0036 };
0037
0038 struct amdgpu_ras_eeprom_table_header {
0039     uint32_t header;
0040     uint32_t version;
0041     uint32_t first_rec_offset;
0042     uint32_t tbl_size;
0043     uint32_t checksum;
0044 } __packed;
0045
0046 struct amdgpu_ras_eeprom_control {
0047     struct amdgpu_ras_eeprom_table_header tbl_hdr;
0048
0049     /* Base I2C EEPPROM 19-bit memory address,
0050      * where the table is located. For more information,
0051      * see top of amdgpu_eeprom.c.
0052      */
0053     u32 i2c_address;
0054
0055     /* The byte offset off of @i2c_address
0056      * where the table header is found,
0057      * and where the records start--always
0058      * right after the header.
0059      */
0060     u32 ras_header_offset;
0061     u32 ras_record_offset;
0062
0063     /* Number of records in the table.
0064      */
0065     u32 ras_num_recs;
0066
0067     /* First record index to read, 0-based.
0068      * Range is [0, num_recs-1]. This is
0069      * an absolute index, starting right after
0070      * the table header.
0071      */
0072     u32 ras_fri;
0073
0074     /* Maximum possible number of records
0075      * we could store, i.e. the maximum capacity
0076      * of the table.
0077      */
0078     u32 ras_max_record_count;
0079
0080     /* Protect table access via this mutex.
0081      */
0082     struct mutex ras_tbl_mutex;
0083
0084     /* Record channel info which occurred bad pages
0085      */
0086     u32 bad_channel_bitmap;
0087 };
0088
0089 /*
0090  * Represents single table record. Packed to be easily serialized into byte
0091  * stream.
0092  */
0093 struct eeprom_table_record {
0094
0095     union {
0096         uint64_t address;
0097         uint64_t offset;
0098     };
0099
0100     uint64_t retired_page;
0101     uint64_t ts;
0102
0103     enum amdgpu_ras_eeprom_err_type err_type;
0104
0105     union {
0106         unsigned char bank;
0107         unsigned char cu;
0108     };
0109
0110     unsigned char mem_channel;
0111     unsigned char mcumc_id;
0112 } __packed;
0113
0114 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
0115                bool *exceed_err_limit);
0116
0117 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
0118
0119 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
0120
0121 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
0122                struct eeprom_table_record *records, const u32 num);
0123
0124 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
0125                  struct eeprom_table_record *records, const u32 num);
0126
0127 uint32_t amdgpu_ras_eeprom_max_record_count(void);
0128
0129 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);
0130
0131 extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
0132 extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;
0133
0134 #endif // _AMDGPU_RAS_EEPROM_H