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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Author: Huang Rui
0023  *
0024  */
0025 #ifndef __AMDGPU_PSP_H__
0026 #define __AMDGPU_PSP_H__
0027 
0028 #include "amdgpu.h"
0029 #include "psp_gfx_if.h"
0030 #include "ta_xgmi_if.h"
0031 #include "ta_ras_if.h"
0032 #include "ta_rap_if.h"
0033 #include "ta_secureDisplay_if.h"
0034 
0035 #define PSP_FENCE_BUFFER_SIZE   0x1000
0036 #define PSP_CMD_BUFFER_SIZE 0x1000
0037 #define PSP_1_MEG       0x100000
0038 #define PSP_TMR_SIZE(adev)  ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
0039 #define PSP_TMR_ALIGNMENT   0x100000
0040 #define PSP_FW_NAME_LEN     0x24
0041 
0042 enum psp_shared_mem_size {
0043     PSP_ASD_SHARED_MEM_SIZE             = 0x0,
0044     PSP_XGMI_SHARED_MEM_SIZE            = 0x4000,
0045     PSP_RAS_SHARED_MEM_SIZE             = 0x4000,
0046     PSP_HDCP_SHARED_MEM_SIZE            = 0x4000,
0047     PSP_DTM_SHARED_MEM_SIZE             = 0x4000,
0048     PSP_RAP_SHARED_MEM_SIZE             = 0x4000,
0049     PSP_SECUREDISPLAY_SHARED_MEM_SIZE   = 0x4000,
0050 };
0051 
0052 enum ta_type_id {
0053     TA_TYPE_XGMI = 1,
0054     TA_TYPE_RAS,
0055     TA_TYPE_HDCP,
0056     TA_TYPE_DTM,
0057     TA_TYPE_RAP,
0058     TA_TYPE_SECUREDISPLAY,
0059 
0060     TA_TYPE_MAX_INDEX,
0061 };
0062 
0063 struct psp_context;
0064 struct psp_xgmi_node_info;
0065 struct psp_xgmi_topology_info;
0066 struct psp_bin_desc;
0067 
0068 enum psp_bootloader_cmd {
0069     PSP_BL__LOAD_SYSDRV     = 0x10000,
0070     PSP_BL__LOAD_SOSDRV     = 0x20000,
0071     PSP_BL__LOAD_KEY_DATABASE   = 0x80000,
0072     PSP_BL__LOAD_SOCDRV             = 0xB0000,
0073     PSP_BL__LOAD_DBGDRV             = 0xC0000,
0074     PSP_BL__LOAD_INTFDRV        = 0xD0000,
0075     PSP_BL__DRAM_LONG_TRAIN     = 0x100000,
0076     PSP_BL__DRAM_SHORT_TRAIN    = 0x200000,
0077     PSP_BL__LOAD_TOS_SPL_TABLE  = 0x10000000,
0078 };
0079 
0080 enum psp_ring_type
0081 {
0082     PSP_RING_TYPE__INVALID = 0,
0083     /*
0084      * These values map to the way the PSP kernel identifies the
0085      * rings.
0086      */
0087     PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
0088     PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
0089 };
0090 
0091 struct psp_ring
0092 {
0093     enum psp_ring_type      ring_type;
0094     struct psp_gfx_rb_frame     *ring_mem;
0095     uint64_t            ring_mem_mc_addr;
0096     void                *ring_mem_handle;
0097     uint32_t            ring_size;
0098     uint32_t            ring_wptr;
0099 };
0100 
0101 /* More registers may will be supported */
0102 enum psp_reg_prog_id {
0103     PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
0104     PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
0105     PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
0106     PSP_REG_LAST
0107 };
0108 
0109 struct psp_funcs
0110 {
0111     int (*init_microcode)(struct psp_context *psp);
0112     int (*bootloader_load_kdb)(struct psp_context *psp);
0113     int (*bootloader_load_spl)(struct psp_context *psp);
0114     int (*bootloader_load_sysdrv)(struct psp_context *psp);
0115     int (*bootloader_load_soc_drv)(struct psp_context *psp);
0116     int (*bootloader_load_intf_drv)(struct psp_context *psp);
0117     int (*bootloader_load_dbg_drv)(struct psp_context *psp);
0118     int (*bootloader_load_sos)(struct psp_context *psp);
0119     int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
0120     int (*ring_create)(struct psp_context *psp,
0121                enum psp_ring_type ring_type);
0122     int (*ring_stop)(struct psp_context *psp,
0123                 enum psp_ring_type ring_type);
0124     int (*ring_destroy)(struct psp_context *psp,
0125                 enum psp_ring_type ring_type);
0126     bool (*smu_reload_quirk)(struct psp_context *psp);
0127     int (*mode1_reset)(struct psp_context *psp);
0128     int (*mem_training)(struct psp_context *psp, uint32_t ops);
0129     uint32_t (*ring_get_wptr)(struct psp_context *psp);
0130     void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
0131     int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
0132     int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
0133     int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
0134     int (*vbflash_stat)(struct psp_context *psp);
0135 };
0136 
0137 #define AMDGPU_XGMI_MAX_CONNECTED_NODES     64
0138 struct psp_xgmi_node_info {
0139     uint64_t                node_id;
0140     uint8_t                 num_hops;
0141     uint8_t                 is_sharing_enabled;
0142     enum ta_xgmi_assigned_sdma_engine   sdma_engine;
0143     uint8_t                 num_links;
0144 };
0145 
0146 struct psp_xgmi_topology_info {
0147     uint32_t            num_nodes;
0148     struct psp_xgmi_node_info   nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
0149 };
0150 
0151 struct psp_bin_desc {
0152     uint32_t fw_version;
0153     uint32_t feature_version;
0154     uint32_t size_bytes;
0155     uint8_t *start_addr;
0156 };
0157 
0158 struct ta_mem_context {
0159     struct amdgpu_bo        *shared_bo;
0160     uint64_t        shared_mc_addr;
0161     void            *shared_buf;
0162     enum psp_shared_mem_size    shared_mem_size;
0163 };
0164 
0165 struct ta_context {
0166     bool            initialized;
0167     uint32_t        session_id;
0168     uint32_t        resp_status;
0169     struct ta_mem_context   mem_context;
0170     struct psp_bin_desc     bin_desc;
0171     enum psp_gfx_cmd_id     ta_load_type;
0172     enum ta_type_id     ta_type;
0173 };
0174 
0175 struct ta_cp_context {
0176     struct ta_context       context;
0177     struct mutex            mutex;
0178 };
0179 
0180 struct psp_xgmi_context {
0181     struct ta_context       context;
0182     struct psp_xgmi_topology_info   top_info;
0183     bool                supports_extended_data;
0184 };
0185 
0186 struct psp_ras_context {
0187     struct ta_context       context;
0188     struct amdgpu_ras       *ras;
0189 };
0190 
0191 #define MEM_TRAIN_SYSTEM_SIGNATURE      0x54534942
0192 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES   0x1000
0193 #define GDDR6_MEM_TRAINING_OFFSET       0x8000
0194 /*Define the VRAM size that will be encroached by BIST training.*/
0195 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE  0x2000000
0196 
0197 enum psp_memory_training_init_flag {
0198     PSP_MEM_TRAIN_NOT_SUPPORT   = 0x0,
0199     PSP_MEM_TRAIN_SUPPORT       = 0x1,
0200     PSP_MEM_TRAIN_INIT_FAILED   = 0x2,
0201     PSP_MEM_TRAIN_RESERVE_SUCCESS   = 0x4,
0202     PSP_MEM_TRAIN_INIT_SUCCESS  = 0x8,
0203 };
0204 
0205 enum psp_memory_training_ops {
0206     PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
0207     PSP_MEM_TRAIN_SAVE      = 0x2,
0208     PSP_MEM_TRAIN_RESTORE       = 0x4,
0209     PSP_MEM_TRAIN_SEND_SHORT_MSG    = 0x8,
0210     PSP_MEM_TRAIN_COLD_BOOT     = PSP_MEM_TRAIN_SEND_LONG_MSG,
0211     PSP_MEM_TRAIN_RESUME        = PSP_MEM_TRAIN_SEND_SHORT_MSG,
0212 };
0213 
0214 struct psp_memory_training_context {
0215     /*training data size*/
0216     u64 train_data_size;
0217     /*
0218      * sys_cache
0219      * cpu virtual address
0220      * system memory buffer that used to store the training data.
0221      */
0222     void *sys_cache;
0223 
0224     /*vram offset of the p2c training data*/
0225     u64 p2c_train_data_offset;
0226 
0227     /*vram offset of the c2p training data*/
0228     u64 c2p_train_data_offset;
0229     struct amdgpu_bo *c2p_bo;
0230 
0231     enum psp_memory_training_init_flag init;
0232     u32 training_cnt;
0233     bool enable_mem_training;
0234 };
0235 
0236 /** PSP runtime DB **/
0237 #define PSP_RUNTIME_DB_SIZE_IN_BYTES        0x10000
0238 #define PSP_RUNTIME_DB_OFFSET           0x100000
0239 #define PSP_RUNTIME_DB_COOKIE_ID        0x0ed5
0240 #define PSP_RUNTIME_DB_VER_1            0x0100
0241 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
0242 
0243 enum psp_runtime_entry_type {
0244     PSP_RUNTIME_ENTRY_TYPE_INVALID      = 0x0,
0245     PSP_RUNTIME_ENTRY_TYPE_TEST     = 0x1,
0246     PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON  = 0x2,  /* Common mGPU runtime data */
0247     PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL    = 0x3,  /* WAFL runtime data */
0248     PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI    = 0x4,  /* XGMI runtime data */
0249     PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG  = 0x5,  /* Boot Config runtime data */
0250     PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
0251 };
0252 
0253 /* PSP runtime DB header */
0254 struct psp_runtime_data_header {
0255     /* determine the existence of runtime db */
0256     uint16_t cookie;
0257     /* version of runtime db */
0258     uint16_t version;
0259 };
0260 
0261 /* PSP runtime DB entry */
0262 struct psp_runtime_entry {
0263     /* type of runtime db entry */
0264     uint32_t entry_type;
0265     /* offset of entry in bytes */
0266     uint16_t offset;
0267     /* size of entry in bytes */
0268     uint16_t size;
0269 };
0270 
0271 /* PSP runtime DB directory */
0272 struct psp_runtime_data_directory {
0273     /* number of valid entries */
0274     uint16_t            entry_count;
0275     /* db entries*/
0276     struct psp_runtime_entry    entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
0277 };
0278 
0279 /* PSP runtime DB boot config feature bitmask */
0280 enum psp_runtime_boot_cfg_feature {
0281     BOOT_CFG_FEATURE_GECC                       = 0x1,
0282     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING    = 0x2,
0283 };
0284 
0285 /* PSP run time DB SCPM authentication defines */
0286 enum psp_runtime_scpm_authentication {
0287     SCPM_DISABLE                     = 0x0,
0288     SCPM_ENABLE                      = 0x1,
0289     SCPM_ENABLE_WITH_SCPM_ERR        = 0x2,
0290 };
0291 
0292 /* PSP runtime DB boot config entry */
0293 struct psp_runtime_boot_cfg_entry {
0294     uint32_t boot_cfg_bitmask;
0295     uint32_t reserved;
0296 };
0297 
0298 /* PSP runtime DB SCPM entry */
0299 struct psp_runtime_scpm_entry {
0300     enum psp_runtime_scpm_authentication scpm_status;
0301 };
0302 
0303 struct psp_context
0304 {
0305     struct amdgpu_device            *adev;
0306     struct psp_ring                 km_ring;
0307     struct psp_gfx_cmd_resp     *cmd;
0308 
0309     const struct psp_funcs      *funcs;
0310 
0311     /* firmware buffer */
0312     struct amdgpu_bo        *fw_pri_bo;
0313     uint64_t            fw_pri_mc_addr;
0314     void                *fw_pri_buf;
0315 
0316     /* sos firmware */
0317     const struct firmware       *sos_fw;
0318     struct psp_bin_desc     sys;
0319     struct psp_bin_desc     sos;
0320     struct psp_bin_desc     toc;
0321     struct psp_bin_desc     kdb;
0322     struct psp_bin_desc     spl;
0323     struct psp_bin_desc     rl;
0324     struct psp_bin_desc     soc_drv;
0325     struct psp_bin_desc     intf_drv;
0326     struct psp_bin_desc     dbg_drv;
0327 
0328     /* tmr buffer */
0329     struct amdgpu_bo        *tmr_bo;
0330     uint64_t            tmr_mc_addr;
0331 
0332     /* asd firmware */
0333     const struct firmware   *asd_fw;
0334 
0335     /* toc firmware */
0336     const struct firmware       *toc_fw;
0337 
0338     /* cap firmware */
0339     const struct firmware       *cap_fw;
0340 
0341     /* fence buffer */
0342     struct amdgpu_bo        *fence_buf_bo;
0343     uint64_t            fence_buf_mc_addr;
0344     void                *fence_buf;
0345 
0346     /* cmd buffer */
0347     struct amdgpu_bo        *cmd_buf_bo;
0348     uint64_t            cmd_buf_mc_addr;
0349     struct psp_gfx_cmd_resp     *cmd_buf_mem;
0350 
0351     /* fence value associated with cmd buffer */
0352     atomic_t            fence_value;
0353     /* flag to mark whether gfx fw autoload is supported or not */
0354     bool                autoload_supported;
0355     /* flag to mark whether df cstate management centralized to PMFW */
0356     bool                pmfw_centralized_cstate_management;
0357 
0358     /* xgmi ta firmware and buffer */
0359     const struct firmware       *ta_fw;
0360     uint32_t            ta_fw_version;
0361 
0362     uint32_t            cap_fw_version;
0363     uint32_t            cap_feature_version;
0364     uint32_t            cap_ucode_size;
0365 
0366     struct ta_context       asd_context;
0367     struct psp_xgmi_context     xgmi_context;
0368     struct psp_ras_context      ras_context;
0369     struct ta_cp_context        hdcp_context;
0370     struct ta_cp_context        dtm_context;
0371     struct ta_cp_context        rap_context;
0372     struct ta_cp_context        securedisplay_context;
0373     struct mutex            mutex;
0374     struct psp_memory_training_context mem_train_ctx;
0375 
0376     uint32_t            boot_cfg_bitmask;
0377 
0378     char *vbflash_tmp_buf;
0379     size_t vbflash_image_size;
0380     bool vbflash_done;
0381 };
0382 
0383 struct amdgpu_psp_funcs {
0384     bool (*check_fw_loading_status)(struct amdgpu_device *adev,
0385                     enum AMDGPU_UCODE_ID);
0386 };
0387 
0388 
0389 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
0390 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
0391 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
0392 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
0393 #define psp_init_microcode(psp) \
0394         ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
0395 #define psp_bootloader_load_kdb(psp) \
0396         ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
0397 #define psp_bootloader_load_spl(psp) \
0398         ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
0399 #define psp_bootloader_load_sysdrv(psp) \
0400         ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
0401 #define psp_bootloader_load_soc_drv(psp) \
0402         ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
0403 #define psp_bootloader_load_intf_drv(psp) \
0404         ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
0405 #define psp_bootloader_load_dbg_drv(psp) \
0406         ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
0407 #define psp_bootloader_load_sos(psp) \
0408         ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
0409 #define psp_smu_reload_quirk(psp) \
0410         ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
0411 #define psp_mode1_reset(psp) \
0412         ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
0413 #define psp_mem_training(psp, ops) \
0414     ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
0415 
0416 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
0417 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
0418 
0419 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
0420     ((psp)->funcs->load_usbc_pd_fw ? \
0421     (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
0422 
0423 #define psp_read_usbc_pd_fw(psp, fw_ver) \
0424     ((psp)->funcs->read_usbc_pd_fw ? \
0425     (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
0426 
0427 #define psp_update_spirom(psp, fw_pri_mc_addr) \
0428     ((psp)->funcs->update_spirom ? \
0429     (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
0430 
0431 #define psp_vbflash_status(psp) \
0432     ((psp)->funcs->vbflash_stat ? \
0433     (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
0434 
0435 extern const struct amd_ip_funcs psp_ip_funcs;
0436 
0437 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
0438 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
0439 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
0440 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
0441 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
0442 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
0443 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
0444 
0445 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
0446             uint32_t field_val, uint32_t mask, bool check_changed);
0447 
0448 int psp_gpu_reset(struct amdgpu_device *adev);
0449 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
0450             uint64_t cmd_gpu_addr, int cmd_size);
0451 
0452 int psp_ta_init_shared_buf(struct psp_context *psp,
0453                   struct ta_mem_context *mem_ctx);
0454 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
0455 int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
0456 int psp_ta_load(struct psp_context *psp, struct ta_context *context);
0457 int psp_ta_invoke(struct psp_context *psp,
0458             uint32_t ta_cmd_id,
0459             struct ta_context *context);
0460 int psp_ta_invoke_indirect(struct psp_context *psp,
0461           uint32_t ta_cmd_id,
0462           struct ta_context *context);
0463 
0464 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
0465 int psp_xgmi_terminate(struct psp_context *psp);
0466 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
0467 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
0468 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
0469 int psp_xgmi_get_topology_info(struct psp_context *psp,
0470                    int number_devices,
0471                    struct psp_xgmi_topology_info *topology,
0472                    bool get_extended_data);
0473 int psp_xgmi_set_topology_info(struct psp_context *psp,
0474                    int number_devices,
0475                    struct psp_xgmi_topology_info *topology);
0476 
0477 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
0478 int psp_ras_enable_features(struct psp_context *psp,
0479         union ta_ras_cmd_input *info, bool enable);
0480 int psp_ras_trigger_error(struct psp_context *psp,
0481               struct ta_ras_trigger_error_input *info);
0482 int psp_ras_terminate(struct psp_context *psp);
0483 
0484 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
0485 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
0486 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
0487 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
0488 
0489 int psp_rlc_autoload_start(struct psp_context *psp);
0490 
0491 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
0492         uint32_t value);
0493 int psp_ring_cmd_submit(struct psp_context *psp,
0494             uint64_t cmd_buf_mc_addr,
0495             uint64_t fence_mc_addr,
0496             int index);
0497 int psp_init_asd_microcode(struct psp_context *psp,
0498                const char *chip_name);
0499 int psp_init_toc_microcode(struct psp_context *psp,
0500                const char *chip_name);
0501 int psp_init_sos_microcode(struct psp_context *psp,
0502                const char *chip_name);
0503 int psp_init_ta_microcode(struct psp_context *psp,
0504               const char *chip_name);
0505 int psp_init_cap_microcode(struct psp_context *psp,
0506               const char *chip_name);
0507 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
0508                     uint64_t *output_ptr);
0509 
0510 int psp_load_fw_list(struct psp_context *psp,
0511              struct amdgpu_firmware_info **ucode_list, int ucode_count);
0512 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
0513 
0514 int is_psp_fw_valid(struct psp_bin_desc bin);
0515 
0516 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev);
0517 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev);
0518 #endif
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