amd/amdgpu/amdgpu_pmu.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _AMDGPU_PMU_H_
0025 #define _AMDGPU_PMU_H_
0026
0027 /* PMU types. */
0028 enum amdgpu_pmu_perf_type {
0029     AMDGPU_PMU_PERF_TYPE_NONE = 0,
0030     AMDGPU_PMU_PERF_TYPE_DF,
0031     AMDGPU_PMU_PERF_TYPE_ALL
0032 };
0033
0034 /*
0035  * PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type"
0036  * configurations.  Event config types are parsed from the 64-bit raw
0037  * config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and
0038  * are registered into the HW perf events config_base.
0039  *
0040  * PMU types with only a single event configuration type
0041  * (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated
0042  * when the performance counter is added.
0043  */
0044 enum amdgpu_pmu_event_config_type {
0045     AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0,
0046     AMDGPU_PMU_EVENT_CONFIG_TYPE_DF,
0047     AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
0048     AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX
0049 };
0050
0051 #define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT  56
0052 #define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK   0xff
0053
0054 int amdgpu_pmu_init(struct amdgpu_device *adev);
0055 void amdgpu_pmu_fini(struct amdgpu_device *adev);
0056
0057 #endif /* _AMDGPU_PMU_H_ */