amd/amdgpu/amdgpu_nbio.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_NBIO_H__
0024 #define __AMDGPU_NBIO_H__
0025
0026 /*
0027  * amdgpu nbio functions
0028  */
0029 struct nbio_hdp_flush_reg {
0030     u32 ref_and_mask_cp0;
0031     u32 ref_and_mask_cp1;
0032     u32 ref_and_mask_cp2;
0033     u32 ref_and_mask_cp3;
0034     u32 ref_and_mask_cp4;
0035     u32 ref_and_mask_cp5;
0036     u32 ref_and_mask_cp6;
0037     u32 ref_and_mask_cp7;
0038     u32 ref_and_mask_cp8;
0039     u32 ref_and_mask_cp9;
0040     u32 ref_and_mask_sdma0;
0041     u32 ref_and_mask_sdma1;
0042     u32 ref_and_mask_sdma2;
0043     u32 ref_and_mask_sdma3;
0044     u32 ref_and_mask_sdma4;
0045     u32 ref_and_mask_sdma5;
0046     u32 ref_and_mask_sdma6;
0047     u32 ref_and_mask_sdma7;
0048 };
0049
0050 struct amdgpu_nbio_ras {
0051     struct amdgpu_ras_block_object ras_block;
0052     void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
0053     void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
0054     int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
0055     int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
0056 };
0057
0058 struct amdgpu_nbio_funcs {
0059     const struct nbio_hdp_flush_reg *hdp_flush_reg;
0060     u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
0061     u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
0062     u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
0063     u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
0064     u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
0065     u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
0066     u32 (*get_rev_id)(struct amdgpu_device *adev);
0067     void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
0068     u32 (*get_memsize)(struct amdgpu_device *adev);
0069     void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
0070             bool use_doorbell, int doorbell_index, int doorbell_size);
0071     void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
0072                    int doorbell_index, int instance);
0073     void (*gc_doorbell_init)(struct amdgpu_device *adev);
0074     void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
0075                      bool enable);
0076     void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
0077                           bool enable);
0078     void (*ih_doorbell_range)(struct amdgpu_device *adev,
0079                   bool use_doorbell, int doorbell_index);
0080     void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
0081                       bool enable);
0082     void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
0083                          bool enable);
0084     void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
0085                         bool enable);
0086     void (*get_clockgating_state)(struct amdgpu_device *adev,
0087                       u64 *flags);
0088     void (*ih_control)(struct amdgpu_device *adev);
0089     void (*init_registers)(struct amdgpu_device *adev);
0090     void (*remap_hdp_registers)(struct amdgpu_device *adev);
0091     void (*enable_aspm)(struct amdgpu_device *adev,
0092                 bool enable);
0093     void (*program_aspm)(struct amdgpu_device *adev);
0094     void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
0095     void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
0096     void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
0097     u32 (*get_rom_offset)(struct amdgpu_device *adev);
0098 };
0099
0100 struct amdgpu_nbio {
0101     const struct nbio_hdp_flush_reg *hdp_flush_reg;
0102     struct amdgpu_irq_src ras_controller_irq;
0103     struct amdgpu_irq_src ras_err_event_athub_irq;
0104     struct ras_common_if *ras_if;
0105     const struct amdgpu_nbio_funcs *funcs;
0106     struct amdgpu_nbio_ras  *ras;
0107 };
0108
0109 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
0110 #endif