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0001 /*
0002  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
0003  *                VA Linux Systems Inc., Fremont, California.
0004  * Copyright 2008 Red Hat Inc.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Original Authors:
0025  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
0026  *
0027  * Kernel port Author: Dave Airlie
0028  */
0029 
0030 #ifndef AMDGPU_MODE_H
0031 #define AMDGPU_MODE_H
0032 
0033 #include <drm/display/drm_dp_helper.h>
0034 #include <drm/drm_crtc.h>
0035 #include <drm/drm_edid.h>
0036 #include <drm/drm_encoder.h>
0037 #include <drm/drm_fixed.h>
0038 #include <drm/drm_crtc_helper.h>
0039 #include <drm/drm_fb_helper.h>
0040 #include <drm/drm_framebuffer.h>
0041 #include <drm/drm_plane_helper.h>
0042 #include <drm/drm_probe_helper.h>
0043 #include <linux/i2c.h>
0044 #include <linux/i2c-algo-bit.h>
0045 #include <linux/hrtimer.h>
0046 #include "amdgpu_irq.h"
0047 
0048 #include <drm/display/drm_dp_mst_helper.h>
0049 #include "modules/inc/mod_freesync.h"
0050 #include "amdgpu_dm_irq_params.h"
0051 
0052 struct amdgpu_bo;
0053 struct amdgpu_device;
0054 struct amdgpu_encoder;
0055 struct amdgpu_router;
0056 struct amdgpu_hpd;
0057 
0058 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
0059 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
0060 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
0061 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
0062 
0063 #define to_dm_plane_state(x)    container_of(x, struct dm_plane_state, base)
0064 
0065 #define AMDGPU_MAX_HPD_PINS 6
0066 #define AMDGPU_MAX_CRTCS 6
0067 #define AMDGPU_MAX_PLANES 6
0068 #define AMDGPU_MAX_AFMT_BLOCKS 9
0069 
0070 enum amdgpu_rmx_type {
0071     RMX_OFF,
0072     RMX_FULL,
0073     RMX_CENTER,
0074     RMX_ASPECT
0075 };
0076 
0077 enum amdgpu_underscan_type {
0078     UNDERSCAN_OFF,
0079     UNDERSCAN_ON,
0080     UNDERSCAN_AUTO,
0081 };
0082 
0083 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
0084 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
0085 
0086 enum amdgpu_hpd_id {
0087     AMDGPU_HPD_1 = 0,
0088     AMDGPU_HPD_2,
0089     AMDGPU_HPD_3,
0090     AMDGPU_HPD_4,
0091     AMDGPU_HPD_5,
0092     AMDGPU_HPD_6,
0093     AMDGPU_HPD_NONE = 0xff,
0094 };
0095 
0096 enum amdgpu_crtc_irq {
0097     AMDGPU_CRTC_IRQ_VBLANK1 = 0,
0098     AMDGPU_CRTC_IRQ_VBLANK2,
0099     AMDGPU_CRTC_IRQ_VBLANK3,
0100     AMDGPU_CRTC_IRQ_VBLANK4,
0101     AMDGPU_CRTC_IRQ_VBLANK5,
0102     AMDGPU_CRTC_IRQ_VBLANK6,
0103     AMDGPU_CRTC_IRQ_VLINE1,
0104     AMDGPU_CRTC_IRQ_VLINE2,
0105     AMDGPU_CRTC_IRQ_VLINE3,
0106     AMDGPU_CRTC_IRQ_VLINE4,
0107     AMDGPU_CRTC_IRQ_VLINE5,
0108     AMDGPU_CRTC_IRQ_VLINE6,
0109     AMDGPU_CRTC_IRQ_NONE = 0xff
0110 };
0111 
0112 enum amdgpu_pageflip_irq {
0113     AMDGPU_PAGEFLIP_IRQ_D1 = 0,
0114     AMDGPU_PAGEFLIP_IRQ_D2,
0115     AMDGPU_PAGEFLIP_IRQ_D3,
0116     AMDGPU_PAGEFLIP_IRQ_D4,
0117     AMDGPU_PAGEFLIP_IRQ_D5,
0118     AMDGPU_PAGEFLIP_IRQ_D6,
0119     AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
0120 };
0121 
0122 enum amdgpu_flip_status {
0123     AMDGPU_FLIP_NONE,
0124     AMDGPU_FLIP_PENDING,
0125     AMDGPU_FLIP_SUBMITTED
0126 };
0127 
0128 #define AMDGPU_MAX_I2C_BUS 16
0129 
0130 /* amdgpu gpio-based i2c
0131  * 1. "mask" reg and bits
0132  *    grabs the gpio pins for software use
0133  *    0=not held  1=held
0134  * 2. "a" reg and bits
0135  *    output pin value
0136  *    0=low 1=high
0137  * 3. "en" reg and bits
0138  *    sets the pin direction
0139  *    0=input 1=output
0140  * 4. "y" reg and bits
0141  *    input pin value
0142  *    0=low 1=high
0143  */
0144 struct amdgpu_i2c_bus_rec {
0145     bool valid;
0146     /* id used by atom */
0147     uint8_t i2c_id;
0148     /* id used by atom */
0149     enum amdgpu_hpd_id hpd;
0150     /* can be used with hw i2c engine */
0151     bool hw_capable;
0152     /* uses multi-media i2c engine */
0153     bool mm_i2c;
0154     /* regs and bits */
0155     uint32_t mask_clk_reg;
0156     uint32_t mask_data_reg;
0157     uint32_t a_clk_reg;
0158     uint32_t a_data_reg;
0159     uint32_t en_clk_reg;
0160     uint32_t en_data_reg;
0161     uint32_t y_clk_reg;
0162     uint32_t y_data_reg;
0163     uint32_t mask_clk_mask;
0164     uint32_t mask_data_mask;
0165     uint32_t a_clk_mask;
0166     uint32_t a_data_mask;
0167     uint32_t en_clk_mask;
0168     uint32_t en_data_mask;
0169     uint32_t y_clk_mask;
0170     uint32_t y_data_mask;
0171 };
0172 
0173 #define AMDGPU_MAX_BIOS_CONNECTOR 16
0174 
0175 /* pll flags */
0176 #define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
0177 #define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
0178 #define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
0179 #define AMDGPU_PLL_LEGACY               (1 << 3)
0180 #define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
0181 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
0182 #define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
0183 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
0184 #define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
0185 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
0186 #define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
0187 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
0188 #define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
0189 #define AMDGPU_PLL_IS_LCD               (1 << 13)
0190 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
0191 
0192 struct amdgpu_pll {
0193     /* reference frequency */
0194     uint32_t reference_freq;
0195 
0196     /* fixed dividers */
0197     uint32_t reference_div;
0198     uint32_t post_div;
0199 
0200     /* pll in/out limits */
0201     uint32_t pll_in_min;
0202     uint32_t pll_in_max;
0203     uint32_t pll_out_min;
0204     uint32_t pll_out_max;
0205     uint32_t lcd_pll_out_min;
0206     uint32_t lcd_pll_out_max;
0207     uint32_t best_vco;
0208 
0209     /* divider limits */
0210     uint32_t min_ref_div;
0211     uint32_t max_ref_div;
0212     uint32_t min_post_div;
0213     uint32_t max_post_div;
0214     uint32_t min_feedback_div;
0215     uint32_t max_feedback_div;
0216     uint32_t min_frac_feedback_div;
0217     uint32_t max_frac_feedback_div;
0218 
0219     /* flags for the current clock */
0220     uint32_t flags;
0221 
0222     /* pll id */
0223     uint32_t id;
0224 };
0225 
0226 struct amdgpu_i2c_chan {
0227     struct i2c_adapter adapter;
0228     struct drm_device *dev;
0229     struct i2c_algo_bit_data bit;
0230     struct amdgpu_i2c_bus_rec rec;
0231     struct drm_dp_aux aux;
0232     bool has_aux;
0233     struct mutex mutex;
0234 };
0235 
0236 struct amdgpu_afmt {
0237     bool enabled;
0238     int offset;
0239     bool last_buffer_filled_status;
0240     int id;
0241     struct amdgpu_audio_pin *pin;
0242 };
0243 
0244 /*
0245  * Audio
0246  */
0247 struct amdgpu_audio_pin {
0248     int         channels;
0249     int         rate;
0250     int         bits_per_sample;
0251     u8          status_bits;
0252     u8          category_code;
0253     u32         offset;
0254     bool            connected;
0255     u32         id;
0256 };
0257 
0258 struct amdgpu_audio {
0259     bool enabled;
0260     struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
0261     int num_pins;
0262 };
0263 
0264 struct amdgpu_display_funcs {
0265     /* display watermarks */
0266     void (*bandwidth_update)(struct amdgpu_device *adev);
0267     /* get frame count */
0268     u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
0269     /* set backlight level */
0270     void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
0271                     u8 level);
0272     /* get backlight level */
0273     u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
0274     /* hotplug detect */
0275     bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
0276     void (*hpd_set_polarity)(struct amdgpu_device *adev,
0277                  enum amdgpu_hpd_id hpd);
0278     u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
0279     /* pageflipping */
0280     void (*page_flip)(struct amdgpu_device *adev,
0281               int crtc_id, u64 crtc_base, bool async);
0282     int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
0283                     u32 *vbl, u32 *position);
0284     /* display topology setup */
0285     void (*add_encoder)(struct amdgpu_device *adev,
0286                 uint32_t encoder_enum,
0287                 uint32_t supported_device,
0288                 u16 caps);
0289     void (*add_connector)(struct amdgpu_device *adev,
0290                   uint32_t connector_id,
0291                   uint32_t supported_device,
0292                   int connector_type,
0293                   struct amdgpu_i2c_bus_rec *i2c_bus,
0294                   uint16_t connector_object_id,
0295                   struct amdgpu_hpd *hpd,
0296                   struct amdgpu_router *router);
0297 
0298 
0299 };
0300 
0301 struct amdgpu_framebuffer {
0302     struct drm_framebuffer base;
0303 
0304     uint64_t tiling_flags;
0305     bool tmz_surface;
0306 
0307     /* caching for later use */
0308     uint64_t address;
0309 };
0310 
0311 struct amdgpu_mode_info {
0312     struct atom_context *atom_context;
0313     struct card_info *atom_card_info;
0314     bool mode_config_initialized;
0315     struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
0316     struct drm_plane *planes[AMDGPU_MAX_PLANES];
0317     struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
0318     /* DVI-I properties */
0319     struct drm_property *coherent_mode_property;
0320     /* DAC enable load detect */
0321     struct drm_property *load_detect_property;
0322     /* underscan */
0323     struct drm_property *underscan_property;
0324     struct drm_property *underscan_hborder_property;
0325     struct drm_property *underscan_vborder_property;
0326     /* audio */
0327     struct drm_property *audio_property;
0328     /* FMT dithering */
0329     struct drm_property *dither_property;
0330     /* Adaptive Backlight Modulation (power feature) */
0331     struct drm_property *abm_level_property;
0332     /* hardcoded DFP edid from BIOS */
0333     struct edid *bios_hardcoded_edid;
0334     int bios_hardcoded_edid_size;
0335 
0336     /* firmware flags */
0337     u32 firmware_flags;
0338     /* pointer to backlight encoder */
0339     struct amdgpu_encoder *bl_encoder;
0340     u8 bl_level; /* saved backlight level */
0341     struct amdgpu_audio audio; /* audio stuff */
0342     int         num_crtc; /* number of crtcs */
0343     int         num_hpd; /* number of hpd pins */
0344     int         num_dig; /* number of dig blocks */
0345     bool            gpu_vm_support; /* supports display from GTT */
0346     int         disp_priority;
0347     const struct amdgpu_display_funcs *funcs;
0348     const enum drm_plane_type *plane_type;
0349 };
0350 
0351 #define AMDGPU_MAX_BL_LEVEL 0xFF
0352 
0353 struct amdgpu_backlight_privdata {
0354     struct amdgpu_encoder *encoder;
0355     uint8_t negative;
0356 };
0357 
0358 struct amdgpu_atom_ss {
0359     uint16_t percentage;
0360     uint16_t percentage_divider;
0361     uint8_t type;
0362     uint16_t step;
0363     uint8_t delay;
0364     uint8_t range;
0365     uint8_t refdiv;
0366     /* asic_ss */
0367     uint16_t rate;
0368     uint16_t amount;
0369 };
0370 
0371 struct amdgpu_crtc {
0372     struct drm_crtc base;
0373     int crtc_id;
0374     bool enabled;
0375     bool can_tile;
0376     uint32_t crtc_offset;
0377     struct drm_gem_object *cursor_bo;
0378     uint64_t cursor_addr;
0379     int cursor_x;
0380     int cursor_y;
0381     int cursor_hot_x;
0382     int cursor_hot_y;
0383     int cursor_width;
0384     int cursor_height;
0385     int max_cursor_width;
0386     int max_cursor_height;
0387     enum amdgpu_rmx_type rmx_type;
0388     u8 h_border;
0389     u8 v_border;
0390     fixed20_12 vsc;
0391     fixed20_12 hsc;
0392     struct drm_display_mode native_mode;
0393     u32 pll_id;
0394     /* page flipping */
0395     struct amdgpu_flip_work *pflip_works;
0396     enum amdgpu_flip_status pflip_status;
0397     int deferred_flip_completion;
0398     /* parameters access from DM IRQ handler */
0399     struct dm_irq_params dm_irq_params;
0400     /* pll sharing */
0401     struct amdgpu_atom_ss ss;
0402     bool ss_enabled;
0403     u32 adjusted_clock;
0404     int bpc;
0405     u32 pll_reference_div;
0406     u32 pll_post_div;
0407     u32 pll_flags;
0408     struct drm_encoder *encoder;
0409     struct drm_connector *connector;
0410     /* for dpm */
0411     u32 line_time;
0412     u32 wm_low;
0413     u32 wm_high;
0414     u32 lb_vblank_lead_lines;
0415     struct drm_display_mode hw_mode;
0416     /* for virtual dce */
0417     struct hrtimer vblank_timer;
0418     enum amdgpu_interrupt_state vsync_timer_enabled;
0419 
0420     int otg_inst;
0421     struct drm_pending_vblank_event *event;
0422 };
0423 
0424 struct amdgpu_encoder_atom_dig {
0425     bool linkb;
0426     /* atom dig */
0427     bool coherent_mode;
0428     int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
0429     /* atom lvds/edp */
0430     uint32_t lcd_misc;
0431     uint16_t panel_pwr_delay;
0432     uint32_t lcd_ss_id;
0433     /* panel mode */
0434     struct drm_display_mode native_mode;
0435     struct backlight_device *bl_dev;
0436     int dpms_mode;
0437     uint8_t backlight_level;
0438     int panel_mode;
0439     struct amdgpu_afmt *afmt;
0440 };
0441 
0442 struct amdgpu_encoder {
0443     struct drm_encoder base;
0444     uint32_t encoder_enum;
0445     uint32_t encoder_id;
0446     uint32_t devices;
0447     uint32_t active_device;
0448     uint32_t flags;
0449     uint32_t pixel_clock;
0450     enum amdgpu_rmx_type rmx_type;
0451     enum amdgpu_underscan_type underscan_type;
0452     uint32_t underscan_hborder;
0453     uint32_t underscan_vborder;
0454     struct drm_display_mode native_mode;
0455     void *enc_priv;
0456     int audio_polling_active;
0457     bool is_ext_encoder;
0458     u16 caps;
0459 };
0460 
0461 struct amdgpu_connector_atom_dig {
0462     /* displayport */
0463     u8 dpcd[DP_RECEIVER_CAP_SIZE];
0464     u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
0465     u8 dp_sink_type;
0466     int dp_clock;
0467     int dp_lane_count;
0468     bool edp_on;
0469 };
0470 
0471 struct amdgpu_gpio_rec {
0472     bool valid;
0473     u8 id;
0474     u32 reg;
0475     u32 mask;
0476     u32 shift;
0477 };
0478 
0479 struct amdgpu_hpd {
0480     enum amdgpu_hpd_id hpd;
0481     u8 plugged_state;
0482     struct amdgpu_gpio_rec gpio;
0483 };
0484 
0485 struct amdgpu_router {
0486     u32 router_id;
0487     struct amdgpu_i2c_bus_rec i2c_info;
0488     u8 i2c_addr;
0489     /* i2c mux */
0490     bool ddc_valid;
0491     u8 ddc_mux_type;
0492     u8 ddc_mux_control_pin;
0493     u8 ddc_mux_state;
0494     /* clock/data mux */
0495     bool cd_valid;
0496     u8 cd_mux_type;
0497     u8 cd_mux_control_pin;
0498     u8 cd_mux_state;
0499 };
0500 
0501 enum amdgpu_connector_audio {
0502     AMDGPU_AUDIO_DISABLE = 0,
0503     AMDGPU_AUDIO_ENABLE = 1,
0504     AMDGPU_AUDIO_AUTO = 2
0505 };
0506 
0507 enum amdgpu_connector_dither {
0508     AMDGPU_FMT_DITHER_DISABLE = 0,
0509     AMDGPU_FMT_DITHER_ENABLE = 1,
0510 };
0511 
0512 struct amdgpu_dm_dp_aux {
0513     struct drm_dp_aux aux;
0514     struct ddc_service *ddc_service;
0515 };
0516 
0517 struct amdgpu_i2c_adapter {
0518     struct i2c_adapter base;
0519 
0520     struct ddc_service *ddc_service;
0521 };
0522 
0523 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
0524 
0525 struct amdgpu_connector {
0526     struct drm_connector base;
0527     uint32_t connector_id;
0528     uint32_t devices;
0529     struct amdgpu_i2c_chan *ddc_bus;
0530     /* some systems have an hdmi and vga port with a shared ddc line */
0531     bool shared_ddc;
0532     bool use_digital;
0533     /* we need to mind the EDID between detect
0534        and get modes due to analog/digital/tvencoder */
0535     struct edid *edid;
0536     void *con_priv;
0537     bool dac_load_detect;
0538     bool detected_by_load; /* if the connection status was determined by load */
0539     uint16_t connector_object_id;
0540     struct amdgpu_hpd hpd;
0541     struct amdgpu_router router;
0542     struct amdgpu_i2c_chan *router_bus;
0543     enum amdgpu_connector_audio audio;
0544     enum amdgpu_connector_dither dither;
0545     unsigned pixelclock_for_modeset;
0546 };
0547 
0548 /* TODO: start to use this struct and remove same field from base one */
0549 struct amdgpu_mst_connector {
0550     struct amdgpu_connector base;
0551 
0552     struct drm_dp_mst_topology_mgr mst_mgr;
0553     struct amdgpu_dm_dp_aux dm_dp_aux;
0554     struct drm_dp_mst_port *port;
0555     struct amdgpu_connector *mst_port;
0556     bool is_mst_connector;
0557     struct amdgpu_encoder *mst_encoder;
0558 };
0559 
0560 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
0561                 ((em) == ATOM_ENCODER_MODE_DP_MST))
0562 
0563 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
0564 #define DRM_SCANOUTPOS_VALID        (1 << 0)
0565 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
0566 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
0567 #define USE_REAL_VBLANKSTART        (1 << 30)
0568 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
0569 
0570 void amdgpu_link_encoder_connector(struct drm_device *dev);
0571 
0572 struct drm_connector *
0573 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
0574 struct drm_connector *
0575 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
0576 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
0577                     u32 pixel_clock);
0578 
0579 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
0580 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
0581 
0582 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
0583                   bool use_aux);
0584 
0585 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
0586 
0587 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
0588             unsigned int pipe, unsigned int flags, int *vpos,
0589             int *hpos, ktime_t *stime, ktime_t *etime,
0590             const struct drm_display_mode *mode);
0591 
0592 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
0593 
0594 void amdgpu_enc_destroy(struct drm_encoder *encoder);
0595 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
0596 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
0597                 const struct drm_display_mode *mode,
0598                 struct drm_display_mode *adjusted_mode);
0599 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
0600                  struct drm_display_mode *adjusted_mode);
0601 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
0602 
0603 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
0604             bool in_vblank_irq, int *vpos,
0605             int *hpos, ktime_t *stime, ktime_t *etime,
0606             const struct drm_display_mode *mode);
0607 
0608 /* amdgpu_display.c */
0609 void amdgpu_display_print_display_setup(struct drm_device *dev);
0610 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
0611 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
0612                    struct drm_modeset_acquire_ctx *ctx);
0613 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
0614                 struct drm_framebuffer *fb,
0615                 struct drm_pending_vblank_event *event,
0616                 uint32_t page_flip_flags, uint32_t target,
0617                 struct drm_modeset_acquire_ctx *ctx);
0618 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
0619 
0620 #endif
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