amd/amdgpu/amdgpu_mes_ctx.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_MES_CTX_H__
0025 #define __AMDGPU_MES_CTX_H__
0026
0027 #include "v10_structs.h"
0028
0029 enum {
0030     AMDGPU_MES_CTX_RPTR_OFFS = 0,
0031     AMDGPU_MES_CTX_WPTR_OFFS,
0032     AMDGPU_MES_CTX_FENCE_OFFS,
0033     AMDGPU_MES_CTX_COND_EXE_OFFS,
0034     AMDGPU_MES_CTX_TRAIL_FENCE_OFFS,
0035     AMDGPU_MES_CTX_MAX_OFFS,
0036 };
0037
0038 enum {
0039     AMDGPU_MES_CTX_RING_OFFS = AMDGPU_MES_CTX_MAX_OFFS,
0040     AMDGPU_MES_CTX_IB_OFFS,
0041     AMDGPU_MES_CTX_PADDING_OFFS,
0042 };
0043
0044 #define AMDGPU_MES_CTX_MAX_GFX_RINGS            1
0045 #define AMDGPU_MES_CTX_MAX_COMPUTE_RINGS        4
0046 #define AMDGPU_MES_CTX_MAX_SDMA_RINGS           2
0047 #define AMDGPU_MES_CTX_MAX_RINGS                    \
0048     (AMDGPU_MES_CTX_MAX_GFX_RINGS +                 \
0049      AMDGPU_MES_CTX_MAX_COMPUTE_RINGS +             \
0050      AMDGPU_MES_CTX_MAX_SDMA_RINGS)
0051
0052 #define AMDGPU_CSA_SDMA_SIZE    64
0053 #define GFX10_MEC_HPD_SIZE  2048
0054
0055 struct amdgpu_wb_slot {
0056     uint32_t data[8];
0057 };
0058
0059 struct amdgpu_mes_ctx_meta_data {
0060     struct {
0061         uint8_t ring[PAGE_SIZE * 4];
0062
0063         /* gfx csa */
0064         struct v10_gfx_meta_data gfx_meta_data;
0065
0066         uint8_t gds_backup[64 * 1024];
0067
0068         struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
0069
0070         /* only for ib test */
0071         uint32_t ib[256] __aligned(256);
0072
0073         uint32_t padding[64];
0074
0075     } __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS];
0076
0077     struct {
0078         uint8_t ring[PAGE_SIZE * 4];
0079
0080         uint8_t mec_hpd[GFX10_MEC_HPD_SIZE];
0081
0082         struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
0083
0084         /* only for ib test */
0085         uint32_t ib[256] __aligned(256);
0086
0087         uint32_t padding[64];
0088
0089     } __aligned(PAGE_SIZE) compute[AMDGPU_MES_CTX_MAX_COMPUTE_RINGS];
0090
0091     struct {
0092         uint8_t ring[PAGE_SIZE * 4];
0093
0094         /* sdma csa for mcbp */
0095         uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE];
0096
0097         struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
0098
0099         /* only for ib test */
0100         uint32_t ib[256] __aligned(256);
0101
0102         uint32_t padding[64];
0103
0104     } __aligned(PAGE_SIZE) sdma[AMDGPU_MES_CTX_MAX_SDMA_RINGS];
0105 };
0106
0107 struct amdgpu_mes_ctx_data {
0108     struct amdgpu_bo    *meta_data_obj;
0109     uint64_t                meta_data_gpu_addr;
0110     uint64_t                meta_data_mc_addr;
0111     struct amdgpu_bo_va *meta_data_va;
0112     void                    *meta_data_ptr;
0113     uint32_t                gang_ids[AMDGPU_HW_IP_DMA+1];
0114 };
0115
0116 #define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
0117 #define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
0118
0119 #define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
0120 #define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
0121
0122 #endif