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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 
0029 #include "amdgpu.h"
0030 #include <drm/amdgpu_drm.h>
0031 #include <drm/drm_drv.h>
0032 #include "amdgpu_uvd.h"
0033 #include "amdgpu_vce.h"
0034 #include "atom.h"
0035 
0036 #include <linux/vga_switcheroo.h>
0037 #include <linux/slab.h>
0038 #include <linux/uaccess.h>
0039 #include <linux/pci.h>
0040 #include <linux/pm_runtime.h>
0041 #include "amdgpu_amdkfd.h"
0042 #include "amdgpu_gem.h"
0043 #include "amdgpu_display.h"
0044 #include "amdgpu_ras.h"
0045 
0046 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
0047 {
0048     struct amdgpu_gpu_instance *gpu_instance;
0049     int i;
0050 
0051     mutex_lock(&mgpu_info.mutex);
0052 
0053     for (i = 0; i < mgpu_info.num_gpu; i++) {
0054         gpu_instance = &(mgpu_info.gpu_ins[i]);
0055         if (gpu_instance->adev == adev) {
0056             mgpu_info.gpu_ins[i] =
0057                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
0058             mgpu_info.num_gpu--;
0059             if (adev->flags & AMD_IS_APU)
0060                 mgpu_info.num_apu--;
0061             else
0062                 mgpu_info.num_dgpu--;
0063             break;
0064         }
0065     }
0066 
0067     mutex_unlock(&mgpu_info.mutex);
0068 }
0069 
0070 /**
0071  * amdgpu_driver_unload_kms - Main unload function for KMS.
0072  *
0073  * @dev: drm dev pointer
0074  *
0075  * This is the main unload function for KMS (all asics).
0076  * Returns 0 on success.
0077  */
0078 void amdgpu_driver_unload_kms(struct drm_device *dev)
0079 {
0080     struct amdgpu_device *adev = drm_to_adev(dev);
0081 
0082     if (adev == NULL)
0083         return;
0084 
0085     amdgpu_unregister_gpu_instance(adev);
0086 
0087     if (adev->rmmio == NULL)
0088         return;
0089 
0090     if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
0091         DRM_WARN("smart shift update failed\n");
0092 
0093     amdgpu_acpi_fini(adev);
0094     amdgpu_device_fini_hw(adev);
0095 }
0096 
0097 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
0098 {
0099     struct amdgpu_gpu_instance *gpu_instance;
0100 
0101     mutex_lock(&mgpu_info.mutex);
0102 
0103     if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
0104         DRM_ERROR("Cannot register more gpu instance\n");
0105         mutex_unlock(&mgpu_info.mutex);
0106         return;
0107     }
0108 
0109     gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
0110     gpu_instance->adev = adev;
0111     gpu_instance->mgpu_fan_enabled = 0;
0112 
0113     mgpu_info.num_gpu++;
0114     if (adev->flags & AMD_IS_APU)
0115         mgpu_info.num_apu++;
0116     else
0117         mgpu_info.num_dgpu++;
0118 
0119     mutex_unlock(&mgpu_info.mutex);
0120 }
0121 
0122 /**
0123  * amdgpu_driver_load_kms - Main load function for KMS.
0124  *
0125  * @adev: pointer to struct amdgpu_device
0126  * @flags: device flags
0127  *
0128  * This is the main load function for KMS (all asics).
0129  * Returns 0 on success, error on failure.
0130  */
0131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
0132 {
0133     struct drm_device *dev;
0134     int r, acpi_status;
0135 
0136     dev = adev_to_drm(adev);
0137 
0138     /* amdgpu_device_init should report only fatal error
0139      * like memory allocation failure or iomapping failure,
0140      * or memory manager initialization failure, it must
0141      * properly initialize the GPU MC controller and permit
0142      * VRAM allocation
0143      */
0144     r = amdgpu_device_init(adev, flags);
0145     if (r) {
0146         dev_err(dev->dev, "Fatal error during GPU init\n");
0147         goto out;
0148     }
0149 
0150     adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
0151     if (amdgpu_device_supports_px(dev) &&
0152         (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
0153         adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
0154         dev_info(adev->dev, "Using ATPX for runtime pm\n");
0155     } else if (amdgpu_device_supports_boco(dev) &&
0156            (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
0157         adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
0158         dev_info(adev->dev, "Using BOCO for runtime pm\n");
0159     } else if (amdgpu_device_supports_baco(dev) &&
0160            (amdgpu_runtime_pm != 0)) {
0161         switch (adev->asic_type) {
0162         case CHIP_VEGA20:
0163         case CHIP_ARCTURUS:
0164             /* enable BACO as runpm mode if runpm=1 */
0165             if (amdgpu_runtime_pm > 0)
0166                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
0167             break;
0168         case CHIP_VEGA10:
0169             /* enable BACO as runpm mode if noretry=0 */
0170             if (!adev->gmc.noretry)
0171                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
0172             break;
0173         default:
0174             /* enable BACO as runpm mode on CI+ */
0175             adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
0176             break;
0177         }
0178 
0179         if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
0180             dev_info(adev->dev, "Using BACO for runtime pm\n");
0181     }
0182 
0183     /* Call ACPI methods: require modeset init
0184      * but failure is not fatal
0185      */
0186 
0187     acpi_status = amdgpu_acpi_init(adev);
0188     if (acpi_status)
0189         dev_dbg(dev->dev, "Error during ACPI methods call\n");
0190 
0191     if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
0192         DRM_WARN("smart shift update failed\n");
0193 
0194 out:
0195     if (r)
0196         amdgpu_driver_unload_kms(dev);
0197 
0198     return r;
0199 }
0200 
0201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
0202                 struct drm_amdgpu_query_fw *query_fw,
0203                 struct amdgpu_device *adev)
0204 {
0205     switch (query_fw->fw_type) {
0206     case AMDGPU_INFO_FW_VCE:
0207         fw_info->ver = adev->vce.fw_version;
0208         fw_info->feature = adev->vce.fb_version;
0209         break;
0210     case AMDGPU_INFO_FW_UVD:
0211         fw_info->ver = adev->uvd.fw_version;
0212         fw_info->feature = 0;
0213         break;
0214     case AMDGPU_INFO_FW_VCN:
0215         fw_info->ver = adev->vcn.fw_version;
0216         fw_info->feature = 0;
0217         break;
0218     case AMDGPU_INFO_FW_GMC:
0219         fw_info->ver = adev->gmc.fw_version;
0220         fw_info->feature = 0;
0221         break;
0222     case AMDGPU_INFO_FW_GFX_ME:
0223         fw_info->ver = adev->gfx.me_fw_version;
0224         fw_info->feature = adev->gfx.me_feature_version;
0225         break;
0226     case AMDGPU_INFO_FW_GFX_PFP:
0227         fw_info->ver = adev->gfx.pfp_fw_version;
0228         fw_info->feature = adev->gfx.pfp_feature_version;
0229         break;
0230     case AMDGPU_INFO_FW_GFX_CE:
0231         fw_info->ver = adev->gfx.ce_fw_version;
0232         fw_info->feature = adev->gfx.ce_feature_version;
0233         break;
0234     case AMDGPU_INFO_FW_GFX_RLC:
0235         fw_info->ver = adev->gfx.rlc_fw_version;
0236         fw_info->feature = adev->gfx.rlc_feature_version;
0237         break;
0238     case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
0239         fw_info->ver = adev->gfx.rlc_srlc_fw_version;
0240         fw_info->feature = adev->gfx.rlc_srlc_feature_version;
0241         break;
0242     case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
0243         fw_info->ver = adev->gfx.rlc_srlg_fw_version;
0244         fw_info->feature = adev->gfx.rlc_srlg_feature_version;
0245         break;
0246     case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
0247         fw_info->ver = adev->gfx.rlc_srls_fw_version;
0248         fw_info->feature = adev->gfx.rlc_srls_feature_version;
0249         break;
0250     case AMDGPU_INFO_FW_GFX_MEC:
0251         if (query_fw->index == 0) {
0252             fw_info->ver = adev->gfx.mec_fw_version;
0253             fw_info->feature = adev->gfx.mec_feature_version;
0254         } else if (query_fw->index == 1) {
0255             fw_info->ver = adev->gfx.mec2_fw_version;
0256             fw_info->feature = adev->gfx.mec2_feature_version;
0257         } else
0258             return -EINVAL;
0259         break;
0260     case AMDGPU_INFO_FW_SMC:
0261         fw_info->ver = adev->pm.fw_version;
0262         fw_info->feature = 0;
0263         break;
0264     case AMDGPU_INFO_FW_TA:
0265         switch (query_fw->index) {
0266         case TA_FW_TYPE_PSP_XGMI:
0267             fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
0268             fw_info->feature = adev->psp.xgmi_context.context
0269                            .bin_desc.feature_version;
0270             break;
0271         case TA_FW_TYPE_PSP_RAS:
0272             fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
0273             fw_info->feature = adev->psp.ras_context.context
0274                            .bin_desc.feature_version;
0275             break;
0276         case TA_FW_TYPE_PSP_HDCP:
0277             fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
0278             fw_info->feature = adev->psp.hdcp_context.context
0279                            .bin_desc.feature_version;
0280             break;
0281         case TA_FW_TYPE_PSP_DTM:
0282             fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
0283             fw_info->feature = adev->psp.dtm_context.context
0284                            .bin_desc.feature_version;
0285             break;
0286         case TA_FW_TYPE_PSP_RAP:
0287             fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
0288             fw_info->feature = adev->psp.rap_context.context
0289                            .bin_desc.feature_version;
0290             break;
0291         case TA_FW_TYPE_PSP_SECUREDISPLAY:
0292             fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
0293             fw_info->feature =
0294                 adev->psp.securedisplay_context.context.bin_desc
0295                     .feature_version;
0296             break;
0297         default:
0298             return -EINVAL;
0299         }
0300         break;
0301     case AMDGPU_INFO_FW_SDMA:
0302         if (query_fw->index >= adev->sdma.num_instances)
0303             return -EINVAL;
0304         fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
0305         fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
0306         break;
0307     case AMDGPU_INFO_FW_SOS:
0308         fw_info->ver = adev->psp.sos.fw_version;
0309         fw_info->feature = adev->psp.sos.feature_version;
0310         break;
0311     case AMDGPU_INFO_FW_ASD:
0312         fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
0313         fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
0314         break;
0315     case AMDGPU_INFO_FW_DMCU:
0316         fw_info->ver = adev->dm.dmcu_fw_version;
0317         fw_info->feature = 0;
0318         break;
0319     case AMDGPU_INFO_FW_DMCUB:
0320         fw_info->ver = adev->dm.dmcub_fw_version;
0321         fw_info->feature = 0;
0322         break;
0323     case AMDGPU_INFO_FW_TOC:
0324         fw_info->ver = adev->psp.toc.fw_version;
0325         fw_info->feature = adev->psp.toc.feature_version;
0326         break;
0327     case AMDGPU_INFO_FW_CAP:
0328         fw_info->ver = adev->psp.cap_fw_version;
0329         fw_info->feature = adev->psp.cap_feature_version;
0330         break;
0331     default:
0332         return -EINVAL;
0333     }
0334     return 0;
0335 }
0336 
0337 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
0338                  struct drm_amdgpu_info *info,
0339                  struct drm_amdgpu_info_hw_ip *result)
0340 {
0341     uint32_t ib_start_alignment = 0;
0342     uint32_t ib_size_alignment = 0;
0343     enum amd_ip_block_type type;
0344     unsigned int num_rings = 0;
0345     unsigned int i, j;
0346 
0347     if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
0348         return -EINVAL;
0349 
0350     switch (info->query_hw_ip.type) {
0351     case AMDGPU_HW_IP_GFX:
0352         type = AMD_IP_BLOCK_TYPE_GFX;
0353         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
0354             if (adev->gfx.gfx_ring[i].sched.ready)
0355                 ++num_rings;
0356         ib_start_alignment = 32;
0357         ib_size_alignment = 32;
0358         break;
0359     case AMDGPU_HW_IP_COMPUTE:
0360         type = AMD_IP_BLOCK_TYPE_GFX;
0361         for (i = 0; i < adev->gfx.num_compute_rings; i++)
0362             if (adev->gfx.compute_ring[i].sched.ready)
0363                 ++num_rings;
0364         ib_start_alignment = 32;
0365         ib_size_alignment = 32;
0366         break;
0367     case AMDGPU_HW_IP_DMA:
0368         type = AMD_IP_BLOCK_TYPE_SDMA;
0369         for (i = 0; i < adev->sdma.num_instances; i++)
0370             if (adev->sdma.instance[i].ring.sched.ready)
0371                 ++num_rings;
0372         ib_start_alignment = 256;
0373         ib_size_alignment = 4;
0374         break;
0375     case AMDGPU_HW_IP_UVD:
0376         type = AMD_IP_BLOCK_TYPE_UVD;
0377         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
0378             if (adev->uvd.harvest_config & (1 << i))
0379                 continue;
0380 
0381             if (adev->uvd.inst[i].ring.sched.ready)
0382                 ++num_rings;
0383         }
0384         ib_start_alignment = 64;
0385         ib_size_alignment = 64;
0386         break;
0387     case AMDGPU_HW_IP_VCE:
0388         type = AMD_IP_BLOCK_TYPE_VCE;
0389         for (i = 0; i < adev->vce.num_rings; i++)
0390             if (adev->vce.ring[i].sched.ready)
0391                 ++num_rings;
0392         ib_start_alignment = 4;
0393         ib_size_alignment = 1;
0394         break;
0395     case AMDGPU_HW_IP_UVD_ENC:
0396         type = AMD_IP_BLOCK_TYPE_UVD;
0397         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
0398             if (adev->uvd.harvest_config & (1 << i))
0399                 continue;
0400 
0401             for (j = 0; j < adev->uvd.num_enc_rings; j++)
0402                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
0403                     ++num_rings;
0404         }
0405         ib_start_alignment = 64;
0406         ib_size_alignment = 64;
0407         break;
0408     case AMDGPU_HW_IP_VCN_DEC:
0409         type = AMD_IP_BLOCK_TYPE_VCN;
0410         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
0411             if (adev->uvd.harvest_config & (1 << i))
0412                 continue;
0413 
0414             if (adev->vcn.inst[i].ring_dec.sched.ready)
0415                 ++num_rings;
0416         }
0417         ib_start_alignment = 16;
0418         ib_size_alignment = 16;
0419         break;
0420     case AMDGPU_HW_IP_VCN_ENC:
0421         type = AMD_IP_BLOCK_TYPE_VCN;
0422         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
0423             if (adev->uvd.harvest_config & (1 << i))
0424                 continue;
0425 
0426             for (j = 0; j < adev->vcn.num_enc_rings; j++)
0427                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
0428                     ++num_rings;
0429         }
0430         ib_start_alignment = 64;
0431         ib_size_alignment = 1;
0432         break;
0433     case AMDGPU_HW_IP_VCN_JPEG:
0434         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
0435             AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
0436 
0437         for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
0438             if (adev->jpeg.harvest_config & (1 << i))
0439                 continue;
0440 
0441             if (adev->jpeg.inst[i].ring_dec.sched.ready)
0442                 ++num_rings;
0443         }
0444         ib_start_alignment = 16;
0445         ib_size_alignment = 16;
0446         break;
0447     default:
0448         return -EINVAL;
0449     }
0450 
0451     for (i = 0; i < adev->num_ip_blocks; i++)
0452         if (adev->ip_blocks[i].version->type == type &&
0453             adev->ip_blocks[i].status.valid)
0454             break;
0455 
0456     if (i == adev->num_ip_blocks)
0457         return 0;
0458 
0459     num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
0460             num_rings);
0461 
0462     result->hw_ip_version_major = adev->ip_blocks[i].version->major;
0463     result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
0464 
0465     if (adev->asic_type >= CHIP_VEGA10) {
0466         switch (type) {
0467         case AMD_IP_BLOCK_TYPE_GFX:
0468             result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
0469             break;
0470         case AMD_IP_BLOCK_TYPE_SDMA:
0471             result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
0472             break;
0473         case AMD_IP_BLOCK_TYPE_UVD:
0474         case AMD_IP_BLOCK_TYPE_VCN:
0475         case AMD_IP_BLOCK_TYPE_JPEG:
0476             result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
0477             break;
0478         case AMD_IP_BLOCK_TYPE_VCE:
0479             result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
0480             break;
0481         default:
0482             result->ip_discovery_version = 0;
0483             break;
0484         }
0485     } else {
0486         result->ip_discovery_version = 0;
0487     }
0488     result->capabilities_flags = 0;
0489     result->available_rings = (1 << num_rings) - 1;
0490     result->ib_start_alignment = ib_start_alignment;
0491     result->ib_size_alignment = ib_size_alignment;
0492     return 0;
0493 }
0494 
0495 /*
0496  * Userspace get information ioctl
0497  */
0498 /**
0499  * amdgpu_info_ioctl - answer a device specific request.
0500  *
0501  * @dev: drm device pointer
0502  * @data: request object
0503  * @filp: drm filp
0504  *
0505  * This function is used to pass device specific parameters to the userspace
0506  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
0507  * etc. (all asics).
0508  * Returns 0 on success, -EINVAL on failure.
0509  */
0510 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
0511 {
0512     struct amdgpu_device *adev = drm_to_adev(dev);
0513     struct drm_amdgpu_info *info = data;
0514     struct amdgpu_mode_info *minfo = &adev->mode_info;
0515     void __user *out = (void __user *)(uintptr_t)info->return_pointer;
0516     uint32_t size = info->return_size;
0517     struct drm_crtc *crtc;
0518     uint32_t ui32 = 0;
0519     uint64_t ui64 = 0;
0520     int i, found;
0521     int ui32_size = sizeof(ui32);
0522 
0523     if (!info->return_size || !info->return_pointer)
0524         return -EINVAL;
0525 
0526     switch (info->query) {
0527     case AMDGPU_INFO_ACCEL_WORKING:
0528         ui32 = adev->accel_working;
0529         return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
0530     case AMDGPU_INFO_CRTC_FROM_ID:
0531         for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
0532             crtc = (struct drm_crtc *)minfo->crtcs[i];
0533             if (crtc && crtc->base.id == info->mode_crtc.id) {
0534                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
0535                 ui32 = amdgpu_crtc->crtc_id;
0536                 found = 1;
0537                 break;
0538             }
0539         }
0540         if (!found) {
0541             DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
0542             return -EINVAL;
0543         }
0544         return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
0545     case AMDGPU_INFO_HW_IP_INFO: {
0546         struct drm_amdgpu_info_hw_ip ip = {};
0547         int ret;
0548 
0549         ret = amdgpu_hw_ip_info(adev, info, &ip);
0550         if (ret)
0551             return ret;
0552 
0553         ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
0554         return ret ? -EFAULT : 0;
0555     }
0556     case AMDGPU_INFO_HW_IP_COUNT: {
0557         enum amd_ip_block_type type;
0558         uint32_t count = 0;
0559 
0560         switch (info->query_hw_ip.type) {
0561         case AMDGPU_HW_IP_GFX:
0562             type = AMD_IP_BLOCK_TYPE_GFX;
0563             break;
0564         case AMDGPU_HW_IP_COMPUTE:
0565             type = AMD_IP_BLOCK_TYPE_GFX;
0566             break;
0567         case AMDGPU_HW_IP_DMA:
0568             type = AMD_IP_BLOCK_TYPE_SDMA;
0569             break;
0570         case AMDGPU_HW_IP_UVD:
0571             type = AMD_IP_BLOCK_TYPE_UVD;
0572             break;
0573         case AMDGPU_HW_IP_VCE:
0574             type = AMD_IP_BLOCK_TYPE_VCE;
0575             break;
0576         case AMDGPU_HW_IP_UVD_ENC:
0577             type = AMD_IP_BLOCK_TYPE_UVD;
0578             break;
0579         case AMDGPU_HW_IP_VCN_DEC:
0580         case AMDGPU_HW_IP_VCN_ENC:
0581             type = AMD_IP_BLOCK_TYPE_VCN;
0582             break;
0583         case AMDGPU_HW_IP_VCN_JPEG:
0584             type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
0585                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
0586             break;
0587         default:
0588             return -EINVAL;
0589         }
0590 
0591         for (i = 0; i < adev->num_ip_blocks; i++)
0592             if (adev->ip_blocks[i].version->type == type &&
0593                 adev->ip_blocks[i].status.valid &&
0594                 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
0595                 count++;
0596 
0597         return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
0598     }
0599     case AMDGPU_INFO_TIMESTAMP:
0600         ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
0601         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0602     case AMDGPU_INFO_FW_VERSION: {
0603         struct drm_amdgpu_info_firmware fw_info;
0604         int ret;
0605 
0606         /* We only support one instance of each IP block right now. */
0607         if (info->query_fw.ip_instance != 0)
0608             return -EINVAL;
0609 
0610         ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
0611         if (ret)
0612             return ret;
0613 
0614         return copy_to_user(out, &fw_info,
0615                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
0616     }
0617     case AMDGPU_INFO_NUM_BYTES_MOVED:
0618         ui64 = atomic64_read(&adev->num_bytes_moved);
0619         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0620     case AMDGPU_INFO_NUM_EVICTIONS:
0621         ui64 = atomic64_read(&adev->num_evictions);
0622         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0623     case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
0624         ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
0625         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0626     case AMDGPU_INFO_VRAM_USAGE:
0627         ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
0628         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0629     case AMDGPU_INFO_VIS_VRAM_USAGE:
0630         ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
0631         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0632     case AMDGPU_INFO_GTT_USAGE:
0633         ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
0634         return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
0635     case AMDGPU_INFO_GDS_CONFIG: {
0636         struct drm_amdgpu_info_gds gds_info;
0637 
0638         memset(&gds_info, 0, sizeof(gds_info));
0639         gds_info.compute_partition_size = adev->gds.gds_size;
0640         gds_info.gds_total_size = adev->gds.gds_size;
0641         gds_info.gws_per_compute_partition = adev->gds.gws_size;
0642         gds_info.oa_per_compute_partition = adev->gds.oa_size;
0643         return copy_to_user(out, &gds_info,
0644                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
0645     }
0646     case AMDGPU_INFO_VRAM_GTT: {
0647         struct drm_amdgpu_info_vram_gtt vram_gtt;
0648 
0649         vram_gtt.vram_size = adev->gmc.real_vram_size -
0650             atomic64_read(&adev->vram_pin_size) -
0651             AMDGPU_VM_RESERVED_VRAM;
0652         vram_gtt.vram_cpu_accessible_size =
0653             min(adev->gmc.visible_vram_size -
0654                 atomic64_read(&adev->visible_pin_size),
0655                 vram_gtt.vram_size);
0656         vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
0657         vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
0658         return copy_to_user(out, &vram_gtt,
0659                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
0660     }
0661     case AMDGPU_INFO_MEMORY: {
0662         struct drm_amdgpu_memory_info mem;
0663         struct ttm_resource_manager *gtt_man =
0664             &adev->mman.gtt_mgr.manager;
0665         struct ttm_resource_manager *vram_man =
0666             &adev->mman.vram_mgr.manager;
0667 
0668         memset(&mem, 0, sizeof(mem));
0669         mem.vram.total_heap_size = adev->gmc.real_vram_size;
0670         mem.vram.usable_heap_size = adev->gmc.real_vram_size -
0671             atomic64_read(&adev->vram_pin_size) -
0672             AMDGPU_VM_RESERVED_VRAM;
0673         mem.vram.heap_usage =
0674             ttm_resource_manager_usage(vram_man);
0675         mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
0676 
0677         mem.cpu_accessible_vram.total_heap_size =
0678             adev->gmc.visible_vram_size;
0679         mem.cpu_accessible_vram.usable_heap_size =
0680             min(adev->gmc.visible_vram_size -
0681                 atomic64_read(&adev->visible_pin_size),
0682                 mem.vram.usable_heap_size);
0683         mem.cpu_accessible_vram.heap_usage =
0684             amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
0685         mem.cpu_accessible_vram.max_allocation =
0686             mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
0687 
0688         mem.gtt.total_heap_size = gtt_man->size;
0689         mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
0690             atomic64_read(&adev->gart_pin_size);
0691         mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
0692         mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
0693 
0694         return copy_to_user(out, &mem,
0695                     min((size_t)size, sizeof(mem)))
0696                     ? -EFAULT : 0;
0697     }
0698     case AMDGPU_INFO_READ_MMR_REG: {
0699         unsigned n, alloc_size;
0700         uint32_t *regs;
0701         unsigned se_num = (info->read_mmr_reg.instance >>
0702                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
0703                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
0704         unsigned sh_num = (info->read_mmr_reg.instance >>
0705                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
0706                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
0707 
0708         /* set full masks if the userspace set all bits
0709          * in the bitfields */
0710         if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
0711             se_num = 0xffffffff;
0712         else if (se_num >= AMDGPU_GFX_MAX_SE)
0713             return -EINVAL;
0714         if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
0715             sh_num = 0xffffffff;
0716         else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
0717             return -EINVAL;
0718 
0719         if (info->read_mmr_reg.count > 128)
0720             return -EINVAL;
0721 
0722         regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
0723         if (!regs)
0724             return -ENOMEM;
0725         alloc_size = info->read_mmr_reg.count * sizeof(*regs);
0726 
0727         amdgpu_gfx_off_ctrl(adev, false);
0728         for (i = 0; i < info->read_mmr_reg.count; i++) {
0729             if (amdgpu_asic_read_register(adev, se_num, sh_num,
0730                               info->read_mmr_reg.dword_offset + i,
0731                               &regs[i])) {
0732                 DRM_DEBUG_KMS("unallowed offset %#x\n",
0733                           info->read_mmr_reg.dword_offset + i);
0734                 kfree(regs);
0735                 amdgpu_gfx_off_ctrl(adev, true);
0736                 return -EFAULT;
0737             }
0738         }
0739         amdgpu_gfx_off_ctrl(adev, true);
0740         n = copy_to_user(out, regs, min(size, alloc_size));
0741         kfree(regs);
0742         return n ? -EFAULT : 0;
0743     }
0744     case AMDGPU_INFO_DEV_INFO: {
0745         struct drm_amdgpu_info_device *dev_info;
0746         uint64_t vm_size;
0747         int ret;
0748 
0749         dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
0750         if (!dev_info)
0751             return -ENOMEM;
0752 
0753         dev_info->device_id = adev->pdev->device;
0754         dev_info->chip_rev = adev->rev_id;
0755         dev_info->external_rev = adev->external_rev_id;
0756         dev_info->pci_rev = adev->pdev->revision;
0757         dev_info->family = adev->family;
0758         dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
0759         dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
0760         /* return all clocks in KHz */
0761         dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
0762         if (adev->pm.dpm_enabled) {
0763             dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
0764             dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
0765         } else {
0766             dev_info->max_engine_clock = adev->clock.default_sclk * 10;
0767             dev_info->max_memory_clock = adev->clock.default_mclk * 10;
0768         }
0769         dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
0770         dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
0771             adev->gfx.config.max_shader_engines;
0772         dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
0773         dev_info->_pad = 0;
0774         dev_info->ids_flags = 0;
0775         if (adev->flags & AMD_IS_APU)
0776             dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
0777         if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
0778             dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
0779         if (amdgpu_is_tmz(adev))
0780             dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
0781 
0782         vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
0783         vm_size -= AMDGPU_VA_RESERVED_SIZE;
0784 
0785         /* Older VCE FW versions are buggy and can handle only 40bits */
0786         if (adev->vce.fw_version &&
0787             adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
0788             vm_size = min(vm_size, 1ULL << 40);
0789 
0790         dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
0791         dev_info->virtual_address_max =
0792             min(vm_size, AMDGPU_GMC_HOLE_START);
0793 
0794         if (vm_size > AMDGPU_GMC_HOLE_START) {
0795             dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
0796             dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
0797         }
0798         dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
0799         dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
0800         dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
0801         dev_info->cu_active_number = adev->gfx.cu_info.number;
0802         dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
0803         dev_info->ce_ram_size = adev->gfx.ce_ram_size;
0804         memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
0805                sizeof(adev->gfx.cu_info.ao_cu_bitmap));
0806         memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
0807                sizeof(adev->gfx.cu_info.bitmap));
0808         dev_info->vram_type = adev->gmc.vram_type;
0809         dev_info->vram_bit_width = adev->gmc.vram_width;
0810         dev_info->vce_harvest_config = adev->vce.harvest_config;
0811         dev_info->gc_double_offchip_lds_buf =
0812             adev->gfx.config.double_offchip_lds_buf;
0813         dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
0814         dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
0815         dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
0816         dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
0817         dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
0818         dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
0819         dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
0820 
0821         if (adev->family >= AMDGPU_FAMILY_NV)
0822             dev_info->pa_sc_tile_steering_override =
0823                 adev->gfx.config.pa_sc_tile_steering_override;
0824 
0825         dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
0826 
0827         ret = copy_to_user(out, dev_info,
0828                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
0829         kfree(dev_info);
0830         return ret;
0831     }
0832     case AMDGPU_INFO_VCE_CLOCK_TABLE: {
0833         unsigned i;
0834         struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
0835         struct amd_vce_state *vce_state;
0836 
0837         for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
0838             vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
0839             if (vce_state) {
0840                 vce_clk_table.entries[i].sclk = vce_state->sclk;
0841                 vce_clk_table.entries[i].mclk = vce_state->mclk;
0842                 vce_clk_table.entries[i].eclk = vce_state->evclk;
0843                 vce_clk_table.num_valid_entries++;
0844             }
0845         }
0846 
0847         return copy_to_user(out, &vce_clk_table,
0848                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
0849     }
0850     case AMDGPU_INFO_VBIOS: {
0851         uint32_t bios_size = adev->bios_size;
0852 
0853         switch (info->vbios_info.type) {
0854         case AMDGPU_INFO_VBIOS_SIZE:
0855             return copy_to_user(out, &bios_size,
0856                     min((size_t)size, sizeof(bios_size)))
0857                     ? -EFAULT : 0;
0858         case AMDGPU_INFO_VBIOS_IMAGE: {
0859             uint8_t *bios;
0860             uint32_t bios_offset = info->vbios_info.offset;
0861 
0862             if (bios_offset >= bios_size)
0863                 return -EINVAL;
0864 
0865             bios = adev->bios + bios_offset;
0866             return copy_to_user(out, bios,
0867                         min((size_t)size, (size_t)(bios_size - bios_offset)))
0868                     ? -EFAULT : 0;
0869         }
0870         case AMDGPU_INFO_VBIOS_INFO: {
0871             struct drm_amdgpu_info_vbios vbios_info = {};
0872             struct atom_context *atom_context;
0873 
0874             atom_context = adev->mode_info.atom_context;
0875             memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
0876             memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
0877             vbios_info.version = atom_context->version;
0878             memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
0879                         sizeof(atom_context->vbios_ver_str));
0880             memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
0881 
0882             return copy_to_user(out, &vbios_info,
0883                         min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
0884         }
0885         default:
0886             DRM_DEBUG_KMS("Invalid request %d\n",
0887                     info->vbios_info.type);
0888             return -EINVAL;
0889         }
0890     }
0891     case AMDGPU_INFO_NUM_HANDLES: {
0892         struct drm_amdgpu_info_num_handles handle;
0893 
0894         switch (info->query_hw_ip.type) {
0895         case AMDGPU_HW_IP_UVD:
0896             /* Starting Polaris, we support unlimited UVD handles */
0897             if (adev->asic_type < CHIP_POLARIS10) {
0898                 handle.uvd_max_handles = adev->uvd.max_handles;
0899                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
0900 
0901                 return copy_to_user(out, &handle,
0902                     min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
0903             } else {
0904                 return -ENODATA;
0905             }
0906 
0907             break;
0908         default:
0909             return -EINVAL;
0910         }
0911     }
0912     case AMDGPU_INFO_SENSOR: {
0913         if (!adev->pm.dpm_enabled)
0914             return -ENOENT;
0915 
0916         switch (info->sensor_info.type) {
0917         case AMDGPU_INFO_SENSOR_GFX_SCLK:
0918             /* get sclk in Mhz */
0919             if (amdgpu_dpm_read_sensor(adev,
0920                            AMDGPU_PP_SENSOR_GFX_SCLK,
0921                            (void *)&ui32, &ui32_size)) {
0922                 return -EINVAL;
0923             }
0924             ui32 /= 100;
0925             break;
0926         case AMDGPU_INFO_SENSOR_GFX_MCLK:
0927             /* get mclk in Mhz */
0928             if (amdgpu_dpm_read_sensor(adev,
0929                            AMDGPU_PP_SENSOR_GFX_MCLK,
0930                            (void *)&ui32, &ui32_size)) {
0931                 return -EINVAL;
0932             }
0933             ui32 /= 100;
0934             break;
0935         case AMDGPU_INFO_SENSOR_GPU_TEMP:
0936             /* get temperature in millidegrees C */
0937             if (amdgpu_dpm_read_sensor(adev,
0938                            AMDGPU_PP_SENSOR_GPU_TEMP,
0939                            (void *)&ui32, &ui32_size)) {
0940                 return -EINVAL;
0941             }
0942             break;
0943         case AMDGPU_INFO_SENSOR_GPU_LOAD:
0944             /* get GPU load */
0945             if (amdgpu_dpm_read_sensor(adev,
0946                            AMDGPU_PP_SENSOR_GPU_LOAD,
0947                            (void *)&ui32, &ui32_size)) {
0948                 return -EINVAL;
0949             }
0950             break;
0951         case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
0952             /* get average GPU power */
0953             if (amdgpu_dpm_read_sensor(adev,
0954                            AMDGPU_PP_SENSOR_GPU_POWER,
0955                            (void *)&ui32, &ui32_size)) {
0956                 return -EINVAL;
0957             }
0958             ui32 >>= 8;
0959             break;
0960         case AMDGPU_INFO_SENSOR_VDDNB:
0961             /* get VDDNB in millivolts */
0962             if (amdgpu_dpm_read_sensor(adev,
0963                            AMDGPU_PP_SENSOR_VDDNB,
0964                            (void *)&ui32, &ui32_size)) {
0965                 return -EINVAL;
0966             }
0967             break;
0968         case AMDGPU_INFO_SENSOR_VDDGFX:
0969             /* get VDDGFX in millivolts */
0970             if (amdgpu_dpm_read_sensor(adev,
0971                            AMDGPU_PP_SENSOR_VDDGFX,
0972                            (void *)&ui32, &ui32_size)) {
0973                 return -EINVAL;
0974             }
0975             break;
0976         case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
0977             /* get stable pstate sclk in Mhz */
0978             if (amdgpu_dpm_read_sensor(adev,
0979                            AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
0980                            (void *)&ui32, &ui32_size)) {
0981                 return -EINVAL;
0982             }
0983             ui32 /= 100;
0984             break;
0985         case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
0986             /* get stable pstate mclk in Mhz */
0987             if (amdgpu_dpm_read_sensor(adev,
0988                            AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
0989                            (void *)&ui32, &ui32_size)) {
0990                 return -EINVAL;
0991             }
0992             ui32 /= 100;
0993             break;
0994         default:
0995             DRM_DEBUG_KMS("Invalid request %d\n",
0996                       info->sensor_info.type);
0997             return -EINVAL;
0998         }
0999         return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1000     }
1001     case AMDGPU_INFO_VRAM_LOST_COUNTER:
1002         ui32 = atomic_read(&adev->vram_lost_counter);
1003         return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1004     case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1005         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1006         uint64_t ras_mask;
1007 
1008         if (!ras)
1009             return -EINVAL;
1010         ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1011 
1012         return copy_to_user(out, &ras_mask,
1013                 min_t(u64, size, sizeof(ras_mask))) ?
1014             -EFAULT : 0;
1015     }
1016     case AMDGPU_INFO_VIDEO_CAPS: {
1017         const struct amdgpu_video_codecs *codecs;
1018         struct drm_amdgpu_info_video_caps *caps;
1019         int r;
1020 
1021         switch (info->video_cap.type) {
1022         case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1023             r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1024             if (r)
1025                 return -EINVAL;
1026             break;
1027         case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1028             r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1029             if (r)
1030                 return -EINVAL;
1031             break;
1032         default:
1033             DRM_DEBUG_KMS("Invalid request %d\n",
1034                       info->video_cap.type);
1035             return -EINVAL;
1036         }
1037 
1038         caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1039         if (!caps)
1040             return -ENOMEM;
1041 
1042         for (i = 0; i < codecs->codec_count; i++) {
1043             int idx = codecs->codec_array[i].codec_type;
1044 
1045             switch (idx) {
1046             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1047             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1048             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1049             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1050             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1051             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1052             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1053             case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1054                 caps->codec_info[idx].valid = 1;
1055                 caps->codec_info[idx].max_width =
1056                     codecs->codec_array[i].max_width;
1057                 caps->codec_info[idx].max_height =
1058                     codecs->codec_array[i].max_height;
1059                 caps->codec_info[idx].max_pixels_per_frame =
1060                     codecs->codec_array[i].max_pixels_per_frame;
1061                 caps->codec_info[idx].max_level =
1062                     codecs->codec_array[i].max_level;
1063                 break;
1064             default:
1065                 break;
1066             }
1067         }
1068         r = copy_to_user(out, caps,
1069                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1070         kfree(caps);
1071         return r;
1072     }
1073     default:
1074         DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1075         return -EINVAL;
1076     }
1077     return 0;
1078 }
1079 
1080 
1081 /*
1082  * Outdated mess for old drm with Xorg being in charge (void function now).
1083  */
1084 /**
1085  * amdgpu_driver_lastclose_kms - drm callback for last close
1086  *
1087  * @dev: drm dev pointer
1088  *
1089  * Switch vga_switcheroo state after last close (all asics).
1090  */
1091 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1092 {
1093     drm_fb_helper_lastclose(dev);
1094     vga_switcheroo_process_delayed_switch();
1095 }
1096 
1097 /**
1098  * amdgpu_driver_open_kms - drm callback for open
1099  *
1100  * @dev: drm dev pointer
1101  * @file_priv: drm file
1102  *
1103  * On device open, init vm on cayman+ (all asics).
1104  * Returns 0 on success, error on failure.
1105  */
1106 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1107 {
1108     struct amdgpu_device *adev = drm_to_adev(dev);
1109     struct amdgpu_fpriv *fpriv;
1110     int r, pasid;
1111 
1112     /* Ensure IB tests are run on ring */
1113     flush_delayed_work(&adev->delayed_init_work);
1114 
1115 
1116     if (amdgpu_ras_intr_triggered()) {
1117         DRM_ERROR("RAS Intr triggered, device disabled!!");
1118         return -EHWPOISON;
1119     }
1120 
1121     file_priv->driver_priv = NULL;
1122 
1123     r = pm_runtime_get_sync(dev->dev);
1124     if (r < 0)
1125         goto pm_put;
1126 
1127     fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1128     if (unlikely(!fpriv)) {
1129         r = -ENOMEM;
1130         goto out_suspend;
1131     }
1132 
1133     pasid = amdgpu_pasid_alloc(16);
1134     if (pasid < 0) {
1135         dev_warn(adev->dev, "No more PASIDs available!");
1136         pasid = 0;
1137     }
1138 
1139     r = amdgpu_vm_init(adev, &fpriv->vm);
1140     if (r)
1141         goto error_pasid;
1142 
1143     r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1144     if (r)
1145         goto error_vm;
1146 
1147     fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1148     if (!fpriv->prt_va) {
1149         r = -ENOMEM;
1150         goto error_vm;
1151     }
1152 
1153     if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1154         uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1155 
1156         r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1157                         &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1158         if (r)
1159             goto error_vm;
1160     }
1161 
1162     mutex_init(&fpriv->bo_list_lock);
1163     idr_init(&fpriv->bo_list_handles);
1164 
1165     amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1166 
1167     file_priv->driver_priv = fpriv;
1168     goto out_suspend;
1169 
1170 error_vm:
1171     amdgpu_vm_fini(adev, &fpriv->vm);
1172 
1173 error_pasid:
1174     if (pasid) {
1175         amdgpu_pasid_free(pasid);
1176         amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1177     }
1178 
1179     kfree(fpriv);
1180 
1181 out_suspend:
1182     pm_runtime_mark_last_busy(dev->dev);
1183 pm_put:
1184     pm_runtime_put_autosuspend(dev->dev);
1185 
1186     return r;
1187 }
1188 
1189 /**
1190  * amdgpu_driver_postclose_kms - drm callback for post close
1191  *
1192  * @dev: drm dev pointer
1193  * @file_priv: drm file
1194  *
1195  * On device post close, tear down vm on cayman+ (all asics).
1196  */
1197 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1198                  struct drm_file *file_priv)
1199 {
1200     struct amdgpu_device *adev = drm_to_adev(dev);
1201     struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1202     struct amdgpu_bo_list *list;
1203     struct amdgpu_bo *pd;
1204     u32 pasid;
1205     int handle;
1206 
1207     if (!fpriv)
1208         return;
1209 
1210     pm_runtime_get_sync(dev->dev);
1211 
1212     if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1213         amdgpu_uvd_free_handles(adev, file_priv);
1214     if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1215         amdgpu_vce_free_handles(adev, file_priv);
1216 
1217     if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1218         /* TODO: how to handle reserve failure */
1219         BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1220         amdgpu_vm_bo_del(adev, fpriv->csa_va);
1221         fpriv->csa_va = NULL;
1222         amdgpu_bo_unreserve(adev->virt.csa_obj);
1223     }
1224 
1225     pasid = fpriv->vm.pasid;
1226     pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1227     if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1228         amdgpu_vm_bo_del(adev, fpriv->prt_va);
1229         amdgpu_bo_unreserve(pd);
1230     }
1231 
1232     amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1233     amdgpu_vm_fini(adev, &fpriv->vm);
1234 
1235     if (pasid)
1236         amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1237     amdgpu_bo_unref(&pd);
1238 
1239     idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1240         amdgpu_bo_list_put(list);
1241 
1242     idr_destroy(&fpriv->bo_list_handles);
1243     mutex_destroy(&fpriv->bo_list_lock);
1244 
1245     kfree(fpriv);
1246     file_priv->driver_priv = NULL;
1247 
1248     pm_runtime_mark_last_busy(dev->dev);
1249     pm_runtime_put_autosuspend(dev->dev);
1250 }
1251 
1252 
1253 void amdgpu_driver_release_kms(struct drm_device *dev)
1254 {
1255     struct amdgpu_device *adev = drm_to_adev(dev);
1256 
1257     amdgpu_device_fini_sw(adev);
1258     pci_set_drvdata(adev->pdev, NULL);
1259 }
1260 
1261 /*
1262  * VBlank related functions.
1263  */
1264 /**
1265  * amdgpu_get_vblank_counter_kms - get frame count
1266  *
1267  * @crtc: crtc to get the frame count from
1268  *
1269  * Gets the frame count on the requested crtc (all asics).
1270  * Returns frame count on success, -EINVAL on failure.
1271  */
1272 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1273 {
1274     struct drm_device *dev = crtc->dev;
1275     unsigned int pipe = crtc->index;
1276     struct amdgpu_device *adev = drm_to_adev(dev);
1277     int vpos, hpos, stat;
1278     u32 count;
1279 
1280     if (pipe >= adev->mode_info.num_crtc) {
1281         DRM_ERROR("Invalid crtc %u\n", pipe);
1282         return -EINVAL;
1283     }
1284 
1285     /* The hw increments its frame counter at start of vsync, not at start
1286      * of vblank, as is required by DRM core vblank counter handling.
1287      * Cook the hw count here to make it appear to the caller as if it
1288      * incremented at start of vblank. We measure distance to start of
1289      * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1290      * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1291      * result by 1 to give the proper appearance to caller.
1292      */
1293     if (adev->mode_info.crtcs[pipe]) {
1294         /* Repeat readout if needed to provide stable result if
1295          * we cross start of vsync during the queries.
1296          */
1297         do {
1298             count = amdgpu_display_vblank_get_counter(adev, pipe);
1299             /* Ask amdgpu_display_get_crtc_scanoutpos to return
1300              * vpos as distance to start of vblank, instead of
1301              * regular vertical scanout pos.
1302              */
1303             stat = amdgpu_display_get_crtc_scanoutpos(
1304                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1305                 &vpos, &hpos, NULL, NULL,
1306                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1307         } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1308 
1309         if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1310             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1311             DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1312         } else {
1313             DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1314                       pipe, vpos);
1315 
1316             /* Bump counter if we are at >= leading edge of vblank,
1317              * but before vsync where vpos would turn negative and
1318              * the hw counter really increments.
1319              */
1320             if (vpos >= 0)
1321                 count++;
1322         }
1323     } else {
1324         /* Fallback to use value as is. */
1325         count = amdgpu_display_vblank_get_counter(adev, pipe);
1326         DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1327     }
1328 
1329     return count;
1330 }
1331 
1332 /**
1333  * amdgpu_enable_vblank_kms - enable vblank interrupt
1334  *
1335  * @crtc: crtc to enable vblank interrupt for
1336  *
1337  * Enable the interrupt on the requested crtc (all asics).
1338  * Returns 0 on success, -EINVAL on failure.
1339  */
1340 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1341 {
1342     struct drm_device *dev = crtc->dev;
1343     unsigned int pipe = crtc->index;
1344     struct amdgpu_device *adev = drm_to_adev(dev);
1345     int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1346 
1347     return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1348 }
1349 
1350 /**
1351  * amdgpu_disable_vblank_kms - disable vblank interrupt
1352  *
1353  * @crtc: crtc to disable vblank interrupt for
1354  *
1355  * Disable the interrupt on the requested crtc (all asics).
1356  */
1357 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1358 {
1359     struct drm_device *dev = crtc->dev;
1360     unsigned int pipe = crtc->index;
1361     struct amdgpu_device *adev = drm_to_adev(dev);
1362     int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1363 
1364     amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1365 }
1366 
1367 /*
1368  * Debugfs info
1369  */
1370 #if defined(CONFIG_DEBUG_FS)
1371 
1372 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1373 {
1374     struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1375     struct drm_amdgpu_info_firmware fw_info;
1376     struct drm_amdgpu_query_fw query_fw;
1377     struct atom_context *ctx = adev->mode_info.atom_context;
1378     uint8_t smu_program, smu_major, smu_minor, smu_debug;
1379     int ret, i;
1380 
1381     static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1382 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1383         TA_FW_NAME(XGMI),
1384         TA_FW_NAME(RAS),
1385         TA_FW_NAME(HDCP),
1386         TA_FW_NAME(DTM),
1387         TA_FW_NAME(RAP),
1388         TA_FW_NAME(SECUREDISPLAY),
1389 #undef TA_FW_NAME
1390     };
1391 
1392     /* VCE */
1393     query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1394     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395     if (ret)
1396         return ret;
1397     seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1398            fw_info.feature, fw_info.ver);
1399 
1400     /* UVD */
1401     query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1402     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1403     if (ret)
1404         return ret;
1405     seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1406            fw_info.feature, fw_info.ver);
1407 
1408     /* GMC */
1409     query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1410     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1411     if (ret)
1412         return ret;
1413     seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1414            fw_info.feature, fw_info.ver);
1415 
1416     /* ME */
1417     query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1418     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1419     if (ret)
1420         return ret;
1421     seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1422            fw_info.feature, fw_info.ver);
1423 
1424     /* PFP */
1425     query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1426     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1427     if (ret)
1428         return ret;
1429     seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1430            fw_info.feature, fw_info.ver);
1431 
1432     /* CE */
1433     query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1434     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1435     if (ret)
1436         return ret;
1437     seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1438            fw_info.feature, fw_info.ver);
1439 
1440     /* RLC */
1441     query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1442     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1443     if (ret)
1444         return ret;
1445     seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1446            fw_info.feature, fw_info.ver);
1447 
1448     /* RLC SAVE RESTORE LIST CNTL */
1449     query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1450     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451     if (ret)
1452         return ret;
1453     seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1454            fw_info.feature, fw_info.ver);
1455 
1456     /* RLC SAVE RESTORE LIST GPM MEM */
1457     query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1458     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459     if (ret)
1460         return ret;
1461     seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1462            fw_info.feature, fw_info.ver);
1463 
1464     /* RLC SAVE RESTORE LIST SRM MEM */
1465     query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1466     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467     if (ret)
1468         return ret;
1469     seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1470            fw_info.feature, fw_info.ver);
1471 
1472     /* MEC */
1473     query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1474     query_fw.index = 0;
1475     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1476     if (ret)
1477         return ret;
1478     seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1479            fw_info.feature, fw_info.ver);
1480 
1481     /* MEC2 */
1482     if (adev->gfx.mec2_fw) {
1483         query_fw.index = 1;
1484         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485         if (ret)
1486             return ret;
1487         seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1488                fw_info.feature, fw_info.ver);
1489     }
1490 
1491     /* PSP SOS */
1492     query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1493     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1494     if (ret)
1495         return ret;
1496     seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1497            fw_info.feature, fw_info.ver);
1498 
1499 
1500     /* PSP ASD */
1501     query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1502     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1503     if (ret)
1504         return ret;
1505     seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1506            fw_info.feature, fw_info.ver);
1507 
1508     query_fw.fw_type = AMDGPU_INFO_FW_TA;
1509     for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1510         query_fw.index = i;
1511         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1512         if (ret)
1513             continue;
1514 
1515         seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1516                ta_fw_name[i], fw_info.feature, fw_info.ver);
1517     }
1518 
1519     /* SMC */
1520     query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1521     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1522     if (ret)
1523         return ret;
1524     smu_program = (fw_info.ver >> 24) & 0xff;
1525     smu_major = (fw_info.ver >> 16) & 0xff;
1526     smu_minor = (fw_info.ver >> 8) & 0xff;
1527     smu_debug = (fw_info.ver >> 0) & 0xff;
1528     seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1529            fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1530 
1531     /* SDMA */
1532     query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1533     for (i = 0; i < adev->sdma.num_instances; i++) {
1534         query_fw.index = i;
1535         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1536         if (ret)
1537             return ret;
1538         seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1539                i, fw_info.feature, fw_info.ver);
1540     }
1541 
1542     /* VCN */
1543     query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1544     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1545     if (ret)
1546         return ret;
1547     seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1548            fw_info.feature, fw_info.ver);
1549 
1550     /* DMCU */
1551     query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1552     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1553     if (ret)
1554         return ret;
1555     seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1556            fw_info.feature, fw_info.ver);
1557 
1558     /* DMCUB */
1559     query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1560     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1561     if (ret)
1562         return ret;
1563     seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1564            fw_info.feature, fw_info.ver);
1565 
1566     /* TOC */
1567     query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1568     ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1569     if (ret)
1570         return ret;
1571     seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1572            fw_info.feature, fw_info.ver);
1573 
1574     /* CAP */
1575     if (adev->psp.cap_fw) {
1576         query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1577         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1578         if (ret)
1579             return ret;
1580         seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1581                 fw_info.feature, fw_info.ver);
1582     }
1583 
1584     seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1585 
1586     return 0;
1587 }
1588 
1589 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1590 
1591 #endif
1592 
1593 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1594 {
1595 #if defined(CONFIG_DEBUG_FS)
1596     struct drm_minor *minor = adev_to_drm(adev)->primary;
1597     struct dentry *root = minor->debugfs_root;
1598 
1599     debugfs_create_file("amdgpu_firmware_info", 0444, root,
1600                 adev, &amdgpu_debugfs_firmware_info_fops);
1601 
1602 #endif
1603 }
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