amd/amdgpu/amdgpu_job.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_JOB_H__
0024 #define __AMDGPU_JOB_H__
0025
0026 #include <drm/gpu_scheduler.h>
0027 #include "amdgpu_sync.h"
0028 #include "amdgpu_ring.h"
0029
0030 /* bit set means command submit involves a preamble IB */
0031 #define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0)
0032 /* bit set means preamble IB is first presented in belonging context */
0033 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1)
0034 /* bit set means context switch occured */
0035 #define AMDGPU_HAVE_CTX_SWITCH              (1 << 2)
0036 /* bit set means IB is preempted */
0037 #define AMDGPU_IB_PREEMPTED                 (1 << 3)
0038
0039 #define to_amdgpu_job(sched_job)        \
0040         container_of((sched_job), struct amdgpu_job, base)
0041
0042 #define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
0043
0044 struct amdgpu_fence;
0045 enum amdgpu_ib_pool_type;
0046
0047 struct amdgpu_job {
0048     struct drm_sched_job    base;
0049     struct amdgpu_vm    *vm;
0050     struct amdgpu_sync  sync;
0051     struct amdgpu_sync  sched_sync;
0052     struct dma_fence    hw_fence;
0053     uint32_t        preamble_status;
0054     uint32_t                preemption_status;
0055     bool                    vm_needs_flush;
0056     uint64_t        vm_pd_addr;
0057     unsigned        vmid;
0058     unsigned        pasid;
0059     uint32_t        gds_base, gds_size;
0060     uint32_t        gws_base, gws_size;
0061     uint32_t        oa_base, oa_size;
0062     uint32_t        vram_lost_counter;
0063
0064     /* user fence handling */
0065     uint64_t        uf_addr;
0066     uint64_t        uf_sequence;
0067
0068     /* job_run_counter >= 1 means a resubmit job */
0069     uint32_t        job_run_counter;
0070
0071     uint32_t        num_ibs;
0072     struct amdgpu_ib    ibs[];
0073 };
0074
0075 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
0076              struct amdgpu_job **job, struct amdgpu_vm *vm);
0077 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
0078         enum amdgpu_ib_pool_type pool, struct amdgpu_job **job);
0079 void amdgpu_job_free_resources(struct amdgpu_job *job);
0080 void amdgpu_job_free(struct amdgpu_job *job);
0081 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
0082               void *owner, struct dma_fence **f);
0083 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
0084                  struct dma_fence **fence);
0085
0086 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
0087
0088 #endif