amd/amdgpu/amdgpu_irq.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_IRQ_H__
0025 #define __AMDGPU_IRQ_H__
0026
0027 #include <linux/irqdomain.h>
0028 #include "soc15_ih_clientid.h"
0029 #include "amdgpu_ih.h"
0030
0031 #define AMDGPU_MAX_IRQ_SRC_ID       0x100
0032 #define AMDGPU_MAX_IRQ_CLIENT_ID    0x100
0033
0034 #define AMDGPU_IRQ_CLIENTID_LEGACY  0
0035 #define AMDGPU_IRQ_CLIENTID_MAX     SOC15_IH_CLIENTID_MAX
0036
0037 #define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
0038
0039 struct amdgpu_device;
0040
0041 enum amdgpu_interrupt_state {
0042     AMDGPU_IRQ_STATE_DISABLE,
0043     AMDGPU_IRQ_STATE_ENABLE,
0044 };
0045
0046 struct amdgpu_iv_entry {
0047     struct amdgpu_ih_ring *ih;
0048     unsigned client_id;
0049     unsigned src_id;
0050     unsigned ring_id;
0051     unsigned vmid;
0052     unsigned vmid_src;
0053     uint64_t timestamp;
0054     unsigned timestamp_src;
0055     unsigned pasid;
0056     unsigned pasid_src;
0057     unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
0058     const uint32_t *iv_entry;
0059 };
0060
0061 struct amdgpu_irq_src {
0062     unsigned                num_types;
0063     atomic_t                *enabled_types;
0064     const struct amdgpu_irq_src_funcs   *funcs;
0065 };
0066
0067 struct amdgpu_irq_client {
0068     struct amdgpu_irq_src **sources;
0069 };
0070
0071 /* provided by interrupt generating IP blocks */
0072 struct amdgpu_irq_src_funcs {
0073     int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
0074            unsigned type, enum amdgpu_interrupt_state state);
0075
0076     int (*process)(struct amdgpu_device *adev,
0077                struct amdgpu_irq_src *source,
0078                struct amdgpu_iv_entry *entry);
0079 };
0080
0081 struct amdgpu_irq {
0082     bool                installed;
0083     unsigned int            irq;
0084     spinlock_t          lock;
0085     /* interrupt sources */
0086     struct amdgpu_irq_client    client[AMDGPU_IRQ_CLIENTID_MAX];
0087
0088     /* status, etc. */
0089     bool                msi_enabled; /* msi enabled */
0090
0091     /* interrupt rings */
0092     struct amdgpu_ih_ring       ih, ih1, ih2, ih_soft;
0093     const struct amdgpu_ih_funcs    *ih_funcs;
0094     struct work_struct      ih1_work, ih2_work, ih_soft_work;
0095     struct amdgpu_irq_src       self_irq;
0096
0097     /* gen irq stuff */
0098     struct irq_domain       *domain; /* GPU irq controller domain */
0099     unsigned            virq[AMDGPU_MAX_IRQ_SRC_ID];
0100     uint32_t                        srbm_soft_reset;
0101 };
0102
0103 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
0104
0105 int amdgpu_irq_init(struct amdgpu_device *adev);
0106 void amdgpu_irq_fini_sw(struct amdgpu_device *adev);
0107 void amdgpu_irq_fini_hw(struct amdgpu_device *adev);
0108 int amdgpu_irq_add_id(struct amdgpu_device *adev,
0109               unsigned client_id, unsigned src_id,
0110               struct amdgpu_irq_src *source);
0111 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
0112              struct amdgpu_ih_ring *ih);
0113 void amdgpu_irq_delegate(struct amdgpu_device *adev,
0114              struct amdgpu_iv_entry *entry,
0115              unsigned int num_dw);
0116 int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
0117               unsigned type);
0118 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
0119            unsigned type);
0120 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
0121            unsigned type);
0122 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
0123             unsigned type);
0124 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
0125
0126 int amdgpu_irq_add_domain(struct amdgpu_device *adev);
0127 void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
0128 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
0129
0130 #endif