amd/amdgpu/amdgpu_ih.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_IH_H__
0025 #define __AMDGPU_IH_H__
0026
0027 /* Maximum number of IVs processed at once */
0028 #define AMDGPU_IH_MAX_NUM_IVS   32
0029
0030 struct amdgpu_device;
0031 struct amdgpu_iv_entry;
0032
0033 struct amdgpu_ih_regs {
0034     uint32_t ih_rb_base;
0035     uint32_t ih_rb_base_hi;
0036     uint32_t ih_rb_cntl;
0037     uint32_t ih_rb_wptr;
0038     uint32_t ih_rb_rptr;
0039     uint32_t ih_doorbell_rptr;
0040     uint32_t ih_rb_wptr_addr_lo;
0041     uint32_t ih_rb_wptr_addr_hi;
0042     uint32_t psp_reg_id;
0043 };
0044
0045 /*
0046  * R6xx+ IH ring
0047  */
0048 struct amdgpu_ih_ring {
0049     unsigned        ring_size;
0050     uint32_t        ptr_mask;
0051     u32         doorbell_index;
0052     bool            use_doorbell;
0053     bool            use_bus_addr;
0054
0055     struct amdgpu_bo    *ring_obj;
0056     volatile uint32_t   *ring;
0057     uint64_t        gpu_addr;
0058
0059     uint64_t        wptr_addr;
0060     volatile uint32_t   *wptr_cpu;
0061
0062     uint64_t        rptr_addr;
0063     volatile uint32_t   *rptr_cpu;
0064
0065     bool                    enabled;
0066     unsigned        rptr;
0067     struct amdgpu_ih_regs   ih_regs;
0068
0069     /* For waiting on IH processing at checkpoint. */
0070     wait_queue_head_t wait_process;
0071     uint64_t        processed_timestamp;
0072 };
0073
0074 /* return true if time stamp t2 is after t1 with 48bit wrap around */
0075 #define amdgpu_ih_ts_after(t1, t2) \
0076         (((int64_t)((t2) << 16) - (int64_t)((t1) << 16)) > 0LL)
0077
0078 /* provided by the ih block */
0079 struct amdgpu_ih_funcs {
0080     /* ring read/write ptr handling, called from interrupt context */
0081     u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
0082     void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
0083               struct amdgpu_iv_entry *entry);
0084     uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
0085                  signed int offset);
0086     void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
0087 };
0088
0089 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
0090 #define amdgpu_ih_decode_iv(adev, iv) \
0091     (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
0092 #define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \
0093     (WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \
0094     (adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset)))
0095 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
0096
0097 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
0098             unsigned ring_size, bool use_bus_addr);
0099 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
0100 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
0101               unsigned int num_dw);
0102 int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
0103                         struct amdgpu_ih_ring *ih);
0104 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
0105 void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
0106                 struct amdgpu_ih_ring *ih,
0107                 struct amdgpu_iv_entry *entry);
0108 uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
0109                        signed int offset);
0110 #endif