amd/amdgpu/amdgpu_ids.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_IDS_H__
0024 #define __AMDGPU_IDS_H__
0025
0026 #include <linux/types.h>
0027 #include <linux/mutex.h>
0028 #include <linux/list.h>
0029 #include <linux/dma-fence.h>
0030
0031 #include "amdgpu_sync.h"
0032
0033 /* maximum number of VMIDs */
0034 #define AMDGPU_NUM_VMID 16
0035
0036 struct amdgpu_device;
0037 struct amdgpu_vm;
0038 struct amdgpu_ring;
0039 struct amdgpu_sync;
0040 struct amdgpu_job;
0041
0042 struct amdgpu_vmid {
0043     struct list_head    list;
0044     struct amdgpu_sync  active;
0045     struct dma_fence    *last_flush;
0046     uint64_t        owner;
0047
0048     uint64_t        pd_gpu_addr;
0049     /* last flushed PD/PT update */
0050     uint64_t        flushed_updates;
0051
0052     uint32_t                current_gpu_reset_count;
0053
0054     uint32_t        gds_base;
0055     uint32_t        gds_size;
0056     uint32_t        gws_base;
0057     uint32_t        gws_size;
0058     uint32_t        oa_base;
0059     uint32_t        oa_size;
0060
0061     unsigned        pasid;
0062     struct dma_fence    *pasid_mapping;
0063 };
0064
0065 struct amdgpu_vmid_mgr {
0066     struct mutex        lock;
0067     unsigned        num_ids;
0068     struct list_head    ids_lru;
0069     struct amdgpu_vmid  ids[AMDGPU_NUM_VMID];
0070     atomic_t        reserved_vmid_num;
0071 };
0072
0073 int amdgpu_pasid_alloc(unsigned int bits);
0074 void amdgpu_pasid_free(u32 pasid);
0075 void amdgpu_pasid_free_delayed(struct dma_resv *resv,
0076                    u32 pasid);
0077
0078 bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
0079                    struct amdgpu_vmid *id);
0080 int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
0081                    struct amdgpu_vm *vm,
0082                    unsigned vmhub);
0083 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
0084                    struct amdgpu_vm *vm,
0085                    unsigned vmhub);
0086 int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
0087              struct amdgpu_sync *sync, struct dma_fence *fence,
0088              struct amdgpu_job *job);
0089 void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
0090                unsigned vmid);
0091 void amdgpu_vmid_reset_all(struct amdgpu_device *adev);
0092
0093 void amdgpu_vmid_mgr_init(struct amdgpu_device *adev);
0094 void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev);
0095
0096 #endif