amd/amdgpu/amdgpu_ib.c

0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  *          Christian König
0028  */
0029 #include <linux/seq_file.h>
0030 #include <linux/slab.h>
0031
0032 #include <drm/amdgpu_drm.h>
0033
0034 #include "amdgpu.h"
0035 #include "atom.h"
0036 #include "amdgpu_trace.h"
0037
0038 #define AMDGPU_IB_TEST_TIMEOUT  msecs_to_jiffies(1000)
0039 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000)
0040
0041 /*
0042  * IB
0043  * IBs (Indirect Buffers) and areas of GPU accessible memory where
0044  * commands are stored.  You can put a pointer to the IB in the
0045  * command ring and the hw will fetch the commands from the IB
0046  * and execute them.  Generally userspace acceleration drivers
0047  * produce command buffers which are send to the kernel and
0048  * put in IBs for execution by the requested ring.
0049  */
0050
0051 /**
0052  * amdgpu_ib_get - request an IB (Indirect Buffer)
0053  *
0054  * @adev: amdgpu_device pointer
0055  * @vm: amdgpu_vm pointer
0056  * @size: requested IB size
0057  * @pool_type: IB pool type (delayed, immediate, direct)
0058  * @ib: IB object returned
0059  *
0060  * Request an IB (all asics).  IBs are allocated using the
0061  * suballocator.
0062  * Returns 0 on success, error on failure.
0063  */
0064 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
0065           unsigned size, enum amdgpu_ib_pool_type pool_type,
0066           struct amdgpu_ib *ib)
0067 {
0068     int r;
0069
0070     if (size) {
0071         r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type],
0072                       &ib->sa_bo, size, 256);
0073         if (r) {
0074             dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
0075             return r;
0076         }
0077
0078         ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
0079         /* flush the cache before commit the IB */
0080         ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
0081
0082         if (!vm)
0083             ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
0084     }
0085
0086     return 0;
0087 }
0088
0089 /**
0090  * amdgpu_ib_free - free an IB (Indirect Buffer)
0091  *
0092  * @adev: amdgpu_device pointer
0093  * @ib: IB object to free
0094  * @f: the fence SA bo need wait on for the ib alloation
0095  *
0096  * Free an IB (all asics).
0097  */
0098 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
0099             struct dma_fence *f)
0100 {
0101     amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
0102 }
0103
0104 /**
0105  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
0106  *
0107  * @ring: ring index the IB is associated with
0108  * @num_ibs: number of IBs to schedule
0109  * @ibs: IB objects to schedule
0110  * @job: job to schedule
0111  * @f: fence created during this submission
0112  *
0113  * Schedule an IB on the associated ring (all asics).
0114  * Returns 0 on success, error on failure.
0115  *
0116  * On SI, there are two parallel engines fed from the primary ring,
0117  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
0118  * resource descriptors have moved to memory, the CE allows you to
0119  * prime the caches while the DE is updating register state so that
0120  * the resource descriptors will be already in cache when the draw is
0121  * processed.  To accomplish this, the userspace driver submits two
0122  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
0123  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
0124  * to SI there was just a DE IB.
0125  */
0126 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
0127                struct amdgpu_ib *ibs, struct amdgpu_job *job,
0128                struct dma_fence **f)
0129 {
0130     struct amdgpu_device *adev = ring->adev;
0131     struct amdgpu_ib *ib = &ibs[0];
0132     struct dma_fence *tmp = NULL;
0133     bool need_ctx_switch;
0134     unsigned patch_offset = ~0;
0135     struct amdgpu_vm *vm;
0136     uint64_t fence_ctx;
0137     uint32_t status = 0, alloc_size;
0138     unsigned fence_flags = 0;
0139     bool secure;
0140
0141     unsigned i;
0142     int r = 0;
0143     bool need_pipe_sync = false;
0144
0145     if (num_ibs == 0)
0146         return -EINVAL;
0147
0148     /* ring tests don't use a job */
0149     if (job) {
0150         vm = job->vm;
0151         fence_ctx = job->base.s_fence ?
0152             job->base.s_fence->scheduled.context : 0;
0153     } else {
0154         vm = NULL;
0155         fence_ctx = 0;
0156     }
0157
0158     if (!ring->sched.ready && !ring->is_mes_queue) {
0159         dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
0160         return -EINVAL;
0161     }
0162
0163     if (vm && !job->vmid && !ring->is_mes_queue) {
0164         dev_err(adev->dev, "VM IB without ID\n");
0165         return -EINVAL;
0166     }
0167
0168     if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
0169         (!ring->funcs->secure_submission_supported)) {
0170         dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
0171         return -EINVAL;
0172     }
0173
0174     alloc_size = ring->funcs->emit_frame_size + num_ibs *
0175         ring->funcs->emit_ib_size;
0176
0177     r = amdgpu_ring_alloc(ring, alloc_size);
0178     if (r) {
0179         dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
0180         return r;
0181     }
0182
0183     need_ctx_switch = ring->current_ctx != fence_ctx;
0184     if (ring->funcs->emit_pipeline_sync && job &&
0185         ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
0186          (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
0187          amdgpu_vm_need_pipeline_sync(ring, job))) {
0188         need_pipe_sync = true;
0189
0190         if (tmp)
0191             trace_amdgpu_ib_pipe_sync(job, tmp);
0192
0193         dma_fence_put(tmp);
0194     }
0195
0196     if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
0197         ring->funcs->emit_mem_sync(ring);
0198
0199     if (ring->funcs->emit_wave_limit &&
0200         ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
0201         ring->funcs->emit_wave_limit(ring, true);
0202
0203     if (ring->funcs->insert_start)
0204         ring->funcs->insert_start(ring);
0205
0206     if (job) {
0207         r = amdgpu_vm_flush(ring, job, need_pipe_sync);
0208         if (r) {
0209             amdgpu_ring_undo(ring);
0210             return r;
0211         }
0212     }
0213
0214     if (job && ring->funcs->init_cond_exec)
0215         patch_offset = amdgpu_ring_init_cond_exec(ring);
0216
0217     amdgpu_device_flush_hdp(adev, ring);
0218
0219     if (need_ctx_switch)
0220         status |= AMDGPU_HAVE_CTX_SWITCH;
0221
0222     if (job && ring->funcs->emit_cntxcntl) {
0223         status |= job->preamble_status;
0224         status |= job->preemption_status;
0225         amdgpu_ring_emit_cntxcntl(ring, status);
0226     }
0227
0228     /* Setup initial TMZiness and send it off.
0229      */
0230     secure = false;
0231     if (job && ring->funcs->emit_frame_cntl) {
0232         secure = ib->flags & AMDGPU_IB_FLAGS_SECURE;
0233         amdgpu_ring_emit_frame_cntl(ring, true, secure);
0234     }
0235
0236     for (i = 0; i < num_ibs; ++i) {
0237         ib = &ibs[i];
0238
0239         if (job && ring->funcs->emit_frame_cntl) {
0240             if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
0241                 amdgpu_ring_emit_frame_cntl(ring, false, secure);
0242                 secure = !secure;
0243                 amdgpu_ring_emit_frame_cntl(ring, true, secure);
0244             }
0245         }
0246
0247         amdgpu_ring_emit_ib(ring, job, ib, status);
0248         status &= ~AMDGPU_HAVE_CTX_SWITCH;
0249     }
0250
0251     if (job && ring->funcs->emit_frame_cntl)
0252         amdgpu_ring_emit_frame_cntl(ring, false, secure);
0253
0254     amdgpu_device_invalidate_hdp(adev, ring);
0255
0256     if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
0257         fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
0258
0259     /* wrap the last IB with fence */
0260     if (job && job->uf_addr) {
0261         amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
0262                        fence_flags | AMDGPU_FENCE_FLAG_64BIT);
0263     }
0264
0265     r = amdgpu_fence_emit(ring, f, job, fence_flags);
0266     if (r) {
0267         dev_err(adev->dev, "failed to emit fence (%d)\n", r);
0268         if (job && job->vmid)
0269             amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
0270         amdgpu_ring_undo(ring);
0271         return r;
0272     }
0273
0274     if (ring->funcs->insert_end)
0275         ring->funcs->insert_end(ring);
0276
0277     if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
0278         amdgpu_ring_patch_cond_exec(ring, patch_offset);
0279
0280     ring->current_ctx = fence_ctx;
0281     if (vm && ring->funcs->emit_switch_buffer)
0282         amdgpu_ring_emit_switch_buffer(ring);
0283
0284     if (ring->funcs->emit_wave_limit &&
0285         ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
0286         ring->funcs->emit_wave_limit(ring, false);
0287
0288     amdgpu_ring_commit(ring);
0289     return 0;
0290 }
0291
0292 /**
0293  * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
0294  *
0295  * @adev: amdgpu_device pointer
0296  *
0297  * Initialize the suballocator to manage a pool of memory
0298  * for use as IBs (all asics).
0299  * Returns 0 on success, error on failure.
0300  */
0301 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
0302 {
0303     int r, i;
0304
0305     if (adev->ib_pool_ready)
0306         return 0;
0307
0308     for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
0309         r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i],
0310                           AMDGPU_IB_POOL_SIZE,
0311                           AMDGPU_GPU_PAGE_SIZE,
0312                           AMDGPU_GEM_DOMAIN_GTT);
0313         if (r)
0314             goto error;
0315     }
0316     adev->ib_pool_ready = true;
0317
0318     return 0;
0319
0320 error:
0321     while (i--)
0322         amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
0323     return r;
0324 }
0325
0326 /**
0327  * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
0328  *
0329  * @adev: amdgpu_device pointer
0330  *
0331  * Tear down the suballocator managing the pool of memory
0332  * for use as IBs (all asics).
0333  */
0334 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
0335 {
0336     int i;
0337
0338     if (!adev->ib_pool_ready)
0339         return;
0340
0341     for (i = 0; i < AMDGPU_IB_POOL_MAX; i++)
0342         amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
0343     adev->ib_pool_ready = false;
0344 }
0345
0346 /**
0347  * amdgpu_ib_ring_tests - test IBs on the rings
0348  *
0349  * @adev: amdgpu_device pointer
0350  *
0351  * Test an IB (Indirect Buffer) on each ring.
0352  * If the test fails, disable the ring.
0353  * Returns 0 on success, error if the primary GFX ring
0354  * IB test fails.
0355  */
0356 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
0357 {
0358     long tmo_gfx, tmo_mm;
0359     int r, ret = 0;
0360     unsigned i;
0361
0362     tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
0363     if (amdgpu_sriov_vf(adev)) {
0364         /* for MM engines in hypervisor side they are not scheduled together
0365          * with CP and SDMA engines, so even in exclusive mode MM engine could
0366          * still running on other VF thus the IB TEST TIMEOUT for MM engines
0367          * under SR-IOV should be set to a long time. 8 sec should be enough
0368          * for the MM comes back to this VF.
0369          */
0370         tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
0371     }
0372
0373     if (amdgpu_sriov_runtime(adev)) {
0374         /* for CP & SDMA engines since they are scheduled together so
0375          * need to make the timeout width enough to cover the time
0376          * cost waiting for it coming back under RUNTIME only
0377         */
0378         tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
0379     } else if (adev->gmc.xgmi.hive_id) {
0380         tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
0381     }
0382
0383     for (i = 0; i < adev->num_rings; ++i) {
0384         struct amdgpu_ring *ring = adev->rings[i];
0385         long tmo;
0386
0387         /* KIQ rings don't have an IB test because we never submit IBs
0388          * to them and they have no interrupt support.
0389          */
0390         if (!ring->sched.ready || !ring->funcs->test_ib)
0391             continue;
0392
0393         if (adev->enable_mes &&
0394             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
0395             continue;
0396
0397         /* MM engine need more time */
0398         if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
0399             ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
0400             ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
0401             ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
0402             ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
0403             ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
0404             tmo = tmo_mm;
0405         else
0406             tmo = tmo_gfx;
0407
0408         r = amdgpu_ring_test_ib(ring, tmo);
0409         if (!r) {
0410             DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n",
0411                       ring->name);
0412             continue;
0413         }
0414
0415         ring->sched.ready = false;
0416         DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n",
0417               ring->name, r);
0418
0419         if (ring == &adev->gfx.gfx_ring[0]) {
0420             /* oh, oh, that's really bad */
0421             adev->accel_working = false;
0422             return r;
0423
0424         } else {
0425             ret = r;
0426         }
0427     }
0428     return ret;
0429 }
0430
0431 /*
0432  * Debugfs info
0433  */
0434 #if defined(CONFIG_DEBUG_FS)
0435
0436 static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused)
0437 {
0438     struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
0439
0440     seq_printf(m, "--------------------- DELAYED --------------------- \n");
0441     amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED],
0442                      m);
0443     seq_printf(m, "-------------------- IMMEDIATE -------------------- \n");
0444     amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE],
0445                      m);
0446     seq_printf(m, "--------------------- DIRECT ---------------------- \n");
0447     amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m);
0448
0449     return 0;
0450 }
0451
0452 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info);
0453
0454 #endif
0455
0456 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
0457 {
0458 #if defined(CONFIG_DEBUG_FS)
0459     struct drm_minor *minor = adev_to_drm(adev)->primary;
0460     struct dentry *root = minor->debugfs_root;
0461
0462     debugfs_create_file("amdgpu_sa_info", 0444, root, adev,
0463                 &amdgpu_debugfs_sa_info_fops);
0464
0465 #endif
0466 }