amd/amdgpu/amdgpu_i2c.c

0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026
0027 #include <linux/export.h>
0028 #include <linux/pci.h>
0029
0030 #include <drm/drm_edid.h>
0031 #include <drm/amdgpu_drm.h>
0032 #include "amdgpu.h"
0033 #include "amdgpu_i2c.h"
0034 #include "amdgpu_atombios.h"
0035 #include "atom.h"
0036 #include "atombios_dp.h"
0037 #include "atombios_i2c.h"
0038
0039 /* bit banging i2c */
0040 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
0041 {
0042     struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0043     struct amdgpu_device *adev = drm_to_adev(i2c->dev);
0044     struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
0045     uint32_t temp;
0046
0047     mutex_lock(&i2c->mutex);
0048
0049     /* switch the pads to ddc mode */
0050     if (rec->hw_capable) {
0051         temp = RREG32(rec->mask_clk_reg);
0052         temp &= ~(1 << 16);
0053         WREG32(rec->mask_clk_reg, temp);
0054     }
0055
0056     /* clear the output pin values */
0057     temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
0058     WREG32(rec->a_clk_reg, temp);
0059
0060     temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
0061     WREG32(rec->a_data_reg, temp);
0062
0063     /* set the pins to input */
0064     temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
0065     WREG32(rec->en_clk_reg, temp);
0066
0067     temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
0068     WREG32(rec->en_data_reg, temp);
0069
0070     /* mask the gpio pins for software use */
0071     temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
0072     WREG32(rec->mask_clk_reg, temp);
0073     temp = RREG32(rec->mask_clk_reg);
0074
0075     temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
0076     WREG32(rec->mask_data_reg, temp);
0077     temp = RREG32(rec->mask_data_reg);
0078
0079     return 0;
0080 }
0081
0082 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
0083 {
0084     struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
0085     struct amdgpu_device *adev = drm_to_adev(i2c->dev);
0086     struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
0087     uint32_t temp;
0088
0089     /* unmask the gpio pins for software use */
0090     temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
0091     WREG32(rec->mask_clk_reg, temp);
0092     temp = RREG32(rec->mask_clk_reg);
0093
0094     temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
0095     WREG32(rec->mask_data_reg, temp);
0096     temp = RREG32(rec->mask_data_reg);
0097
0098     mutex_unlock(&i2c->mutex);
0099 }
0100
0101 static int amdgpu_i2c_get_clock(void *i2c_priv)
0102 {
0103     struct amdgpu_i2c_chan *i2c = i2c_priv;
0104     struct amdgpu_device *adev = drm_to_adev(i2c->dev);
0105     struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
0106     uint32_t val;
0107
0108     /* read the value off the pin */
0109     val = RREG32(rec->y_clk_reg);
0110     val &= rec->y_clk_mask;
0111
0112     return (val != 0);
0113 }
0114
0115
0116 static int amdgpu_i2c_get_data(void *i2c_priv)
0117 {
0118     struct amdgpu_i2c_chan *i2c = i2c_priv;
0119     struct amdgpu_device *adev = drm_to_adev(i2c->dev);
0120     struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
0121     uint32_t val;
0122
0123     /* read the value off the pin */
0124     val = RREG32(rec->y_data_reg);
0125     val &= rec->y_data_mask;
0126
0127     return (val != 0);
0128 }
0129
0130 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
0131 {
0132     struct amdgpu_i2c_chan *i2c = i2c_priv;
0133     struct amdgpu_device *adev = drm_to_adev(i2c->dev);
0134     struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
0135     uint32_t val;
0136
0137     /* set pin direction */
0138     val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
0139     val |= clock ? 0 : rec->en_clk_mask;
0140     WREG32(rec->en_clk_reg, val);
0141 }
0142
0143 static void amdgpu_i2c_set_data(void *i2c_priv, int data)
0144 {
0145     struct amdgpu_i2c_chan *i2c = i2c_priv;
0146     struct amdgpu_device *adev = drm_to_adev(i2c->dev);
0147     struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
0148     uint32_t val;
0149
0150     /* set pin direction */
0151     val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
0152     val |= data ? 0 : rec->en_data_mask;
0153     WREG32(rec->en_data_reg, val);
0154 }
0155
0156 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
0157     .master_xfer = amdgpu_atombios_i2c_xfer,
0158     .functionality = amdgpu_atombios_i2c_func,
0159 };
0160
0161 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
0162                       const struct amdgpu_i2c_bus_rec *rec,
0163                       const char *name)
0164 {
0165     struct amdgpu_i2c_chan *i2c;
0166     int ret;
0167
0168     /* don't add the mm_i2c bus unless hw_i2c is enabled */
0169     if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
0170         return NULL;
0171
0172     i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
0173     if (i2c == NULL)
0174         return NULL;
0175
0176     i2c->rec = *rec;
0177     i2c->adapter.owner = THIS_MODULE;
0178     i2c->adapter.class = I2C_CLASS_DDC;
0179     i2c->adapter.dev.parent = dev->dev;
0180     i2c->dev = dev;
0181     i2c_set_adapdata(&i2c->adapter, i2c);
0182     mutex_init(&i2c->mutex);
0183     if (rec->hw_capable &&
0184         amdgpu_hw_i2c) {
0185         /* hw i2c using atom */
0186         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
0187              "AMDGPU i2c hw bus %s", name);
0188         i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
0189         ret = i2c_add_adapter(&i2c->adapter);
0190         if (ret)
0191             goto out_free;
0192     } else {
0193         /* set the amdgpu bit adapter */
0194         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
0195              "AMDGPU i2c bit bus %s", name);
0196         i2c->adapter.algo_data = &i2c->bit;
0197         i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
0198         i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
0199         i2c->bit.setsda = amdgpu_i2c_set_data;
0200         i2c->bit.setscl = amdgpu_i2c_set_clock;
0201         i2c->bit.getsda = amdgpu_i2c_get_data;
0202         i2c->bit.getscl = amdgpu_i2c_get_clock;
0203         i2c->bit.udelay = 10;
0204         i2c->bit.timeout = usecs_to_jiffies(2200);  /* from VESA */
0205         i2c->bit.data = i2c;
0206         ret = i2c_bit_add_bus(&i2c->adapter);
0207         if (ret) {
0208             DRM_ERROR("Failed to register bit i2c %s\n", name);
0209             goto out_free;
0210         }
0211     }
0212
0213     return i2c;
0214 out_free:
0215     kfree(i2c);
0216     return NULL;
0217
0218 }
0219
0220 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
0221 {
0222     if (!i2c)
0223         return;
0224     WARN_ON(i2c->has_aux);
0225     i2c_del_adapter(&i2c->adapter);
0226     kfree(i2c);
0227 }
0228
0229 /* Add the default buses */
0230 void amdgpu_i2c_init(struct amdgpu_device *adev)
0231 {
0232     if (amdgpu_hw_i2c)
0233         DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
0234
0235     amdgpu_atombios_i2c_init(adev);
0236 }
0237
0238 /* remove all the buses */
0239 void amdgpu_i2c_fini(struct amdgpu_device *adev)
0240 {
0241     int i;
0242
0243     for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
0244         if (adev->i2c_bus[i]) {
0245             amdgpu_i2c_destroy(adev->i2c_bus[i]);
0246             adev->i2c_bus[i] = NULL;
0247         }
0248     }
0249 }
0250
0251 /* Add additional buses */
0252 void amdgpu_i2c_add(struct amdgpu_device *adev,
0253             const struct amdgpu_i2c_bus_rec *rec,
0254             const char *name)
0255 {
0256     struct drm_device *dev = adev_to_drm(adev);
0257     int i;
0258
0259     for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
0260         if (!adev->i2c_bus[i]) {
0261             adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
0262             return;
0263         }
0264     }
0265 }
0266
0267 /* looks up bus based on id */
0268 struct amdgpu_i2c_chan *
0269 amdgpu_i2c_lookup(struct amdgpu_device *adev,
0270           const struct amdgpu_i2c_bus_rec *i2c_bus)
0271 {
0272     int i;
0273
0274     for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
0275         if (adev->i2c_bus[i] &&
0276             (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
0277             return adev->i2c_bus[i];
0278         }
0279     }
0280     return NULL;
0281 }
0282
0283 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
0284                  u8 slave_addr,
0285                  u8 addr,
0286                  u8 *val)
0287 {
0288     u8 out_buf[2];
0289     u8 in_buf[2];
0290     struct i2c_msg msgs[] = {
0291         {
0292             .addr = slave_addr,
0293             .flags = 0,
0294             .len = 1,
0295             .buf = out_buf,
0296         },
0297         {
0298             .addr = slave_addr,
0299             .flags = I2C_M_RD,
0300             .len = 1,
0301             .buf = in_buf,
0302         }
0303     };
0304
0305     out_buf[0] = addr;
0306     out_buf[1] = 0;
0307
0308     if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
0309         *val = in_buf[0];
0310         DRM_DEBUG("val = 0x%02x\n", *val);
0311     } else {
0312         DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
0313               addr, *val);
0314     }
0315 }
0316
0317 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
0318                  u8 slave_addr,
0319                  u8 addr,
0320                  u8 val)
0321 {
0322     uint8_t out_buf[2];
0323     struct i2c_msg msg = {
0324         .addr = slave_addr,
0325         .flags = 0,
0326         .len = 2,
0327         .buf = out_buf,
0328     };
0329
0330     out_buf[0] = addr;
0331     out_buf[1] = val;
0332
0333     if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
0334         DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
0335               addr, val);
0336 }
0337
0338 /* ddc router switching */
0339 void
0340 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
0341 {
0342     u8 val = 0;
0343
0344     if (!amdgpu_connector->router.ddc_valid)
0345         return;
0346
0347     if (!amdgpu_connector->router_bus)
0348         return;
0349
0350     amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
0351                 amdgpu_connector->router.i2c_addr,
0352                 0x3, &val);
0353     val &= ~amdgpu_connector->router.ddc_mux_control_pin;
0354     amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
0355                 amdgpu_connector->router.i2c_addr,
0356                 0x3, val);
0357     amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
0358                 amdgpu_connector->router.i2c_addr,
0359                 0x1, &val);
0360     val &= ~amdgpu_connector->router.ddc_mux_control_pin;
0361     val |= amdgpu_connector->router.ddc_mux_state;
0362     amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
0363                 amdgpu_connector->router.i2c_addr,
0364                 0x1, val);
0365 }
0366
0367 /* clock/data router switching */
0368 void
0369 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
0370 {
0371     u8 val;
0372
0373     if (!amdgpu_connector->router.cd_valid)
0374         return;
0375
0376     if (!amdgpu_connector->router_bus)
0377         return;
0378
0379     amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
0380                 amdgpu_connector->router.i2c_addr,
0381                 0x3, &val);
0382     val &= ~amdgpu_connector->router.cd_mux_control_pin;
0383     amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
0384                 amdgpu_connector->router.i2c_addr,
0385                 0x3, val);
0386     amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
0387                 amdgpu_connector->router.i2c_addr,
0388                 0x1, &val);
0389     val &= ~amdgpu_connector->router.cd_mux_control_pin;
0390     val |= amdgpu_connector->router.cd_mux_state;
0391     amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
0392                 amdgpu_connector->router.i2c_addr,
0393                 0x1, val);
0394 }