amd/amdgpu/amdgpu_gmc.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  * All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the
0007  * "Software"), to deal in the Software without restriction, including
0008  * without limitation the rights to use, copy, modify, merge, publish,
0009  * distribute, sub license, and/or sell copies of the Software, and to
0010  * permit persons to whom the Software is furnished to do so, subject to
0011  * the following conditions:
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0017  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0018  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0019  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * The above copyright notice and this permission notice (including the
0022  * next paragraph) shall be included in all copies or substantial portions
0023  * of the Software.
0024  *
0025  */
0026 #ifndef __AMDGPU_GMC_H__
0027 #define __AMDGPU_GMC_H__
0028
0029 #include <linux/types.h>
0030
0031 #include "amdgpu_irq.h"
0032 #include "amdgpu_ras.h"
0033
0034 /* VA hole for 48bit addresses on Vega10 */
0035 #define AMDGPU_GMC_HOLE_START   0x0000800000000000ULL
0036 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
0037
0038 /*
0039  * Hardware is programmed as if the hole doesn't exists with start and end
0040  * address values.
0041  *
0042  * This mask is used to remove the upper 16bits of the VA and so come up with
0043  * the linear addr value.
0044  */
0045 #define AMDGPU_GMC_HOLE_MASK    0x0000ffffffffffffULL
0046
0047 /*
0048  * Ring size as power of two for the log of recent faults.
0049  */
0050 #define AMDGPU_GMC_FAULT_RING_ORDER 8
0051 #define AMDGPU_GMC_FAULT_RING_SIZE  (1 << AMDGPU_GMC_FAULT_RING_ORDER)
0052
0053 /*
0054  * Hash size as power of two for the log of recent faults
0055  */
0056 #define AMDGPU_GMC_FAULT_HASH_ORDER 8
0057 #define AMDGPU_GMC_FAULT_HASH_SIZE  (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
0058
0059 /*
0060  * Number of IH timestamp ticks until a fault is considered handled
0061  */
0062 #define AMDGPU_GMC_FAULT_TIMEOUT    5000ULL
0063
0064 struct firmware;
0065
0066 /*
0067  * GMC page fault information
0068  */
0069 struct amdgpu_gmc_fault {
0070     uint64_t    timestamp:48;
0071     uint64_t    next:AMDGPU_GMC_FAULT_RING_ORDER;
0072     atomic64_t  key;
0073 };
0074
0075 /*
0076  * VMHUB structures, functions & helpers
0077  */
0078 struct amdgpu_vmhub_funcs {
0079     void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
0080                          uint32_t status);
0081     uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
0082 };
0083
0084 struct amdgpu_vmhub {
0085     uint32_t    ctx0_ptb_addr_lo32;
0086     uint32_t    ctx0_ptb_addr_hi32;
0087     uint32_t    vm_inv_eng0_sem;
0088     uint32_t    vm_inv_eng0_req;
0089     uint32_t    vm_inv_eng0_ack;
0090     uint32_t    vm_context0_cntl;
0091     uint32_t    vm_l2_pro_fault_status;
0092     uint32_t    vm_l2_pro_fault_cntl;
0093
0094     /*
0095      * store the register distances between two continuous context domain
0096      * and invalidation engine.
0097      */
0098     uint32_t    ctx_distance;
0099     uint32_t    ctx_addr_distance; /* include LO32/HI32 */
0100     uint32_t    eng_distance;
0101     uint32_t    eng_addr_distance; /* include LO32/HI32 */
0102
0103     uint32_t        vm_cntx_cntl;
0104     uint32_t    vm_cntx_cntl_vm_fault;
0105     uint32_t    vm_l2_bank_select_reserved_cid2;
0106
0107     const struct amdgpu_vmhub_funcs *vmhub_funcs;
0108 };
0109
0110 /*
0111  * GPU MC structures, functions & helpers
0112  */
0113 struct amdgpu_gmc_funcs {
0114     /* flush the vm tlb via mmio */
0115     void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
0116                 uint32_t vmhub, uint32_t flush_type);
0117     /* flush the vm tlb via pasid */
0118     int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
0119                     uint32_t flush_type, bool all_hub);
0120     /* flush the vm tlb via ring */
0121     uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
0122                        uint64_t pd_addr);
0123     /* Change the VMID -> PASID mapping */
0124     void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
0125                    unsigned pasid);
0126     /* enable/disable PRT support */
0127     void (*set_prt)(struct amdgpu_device *adev, bool enable);
0128     /* map mtype to hardware flags */
0129     uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
0130     /* get the pde for a given mc addr */
0131     void (*get_vm_pde)(struct amdgpu_device *adev, int level,
0132                u64 *dst, u64 *flags);
0133     /* get the pte flags to use for a BO VA mapping */
0134     void (*get_vm_pte)(struct amdgpu_device *adev,
0135                struct amdgpu_bo_va_mapping *mapping,
0136                uint64_t *flags);
0137     /* get the amount of memory used by the vbios for pre-OS console */
0138     unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
0139 };
0140
0141 struct amdgpu_xgmi_ras {
0142     struct amdgpu_ras_block_object ras_block;
0143 };
0144
0145 struct amdgpu_xgmi {
0146     /* from psp */
0147     u64 node_id;
0148     u64 hive_id;
0149     /* fixed per family */
0150     u64 node_segment_size;
0151     /* physical node (0-3) */
0152     unsigned physical_node_id;
0153     /* number of nodes (0-4) */
0154     unsigned num_physical_nodes;
0155     /* gpu list in the same hive */
0156     struct list_head head;
0157     bool supported;
0158     struct ras_common_if *ras_if;
0159     bool connected_to_cpu;
0160     bool pending_reset;
0161     struct amdgpu_xgmi_ras *ras;
0162 };
0163
0164 struct amdgpu_gmc {
0165     /* FB's physical address in MMIO space (for CPU to
0166      * map FB). This is different compared to the agp/
0167      * gart/vram_start/end field as the later is from
0168      * GPU's view and aper_base is from CPU's view.
0169      */
0170     resource_size_t     aper_size;
0171     resource_size_t     aper_base;
0172     /* for some chips with <= 32MB we need to lie
0173      * about vram size near mc fb location */
0174     u64         mc_vram_size;
0175     u64         visible_vram_size;
0176     /* AGP aperture start and end in MC address space
0177      * Driver find a hole in the MC address space
0178      * to place AGP by setting MC_VM_AGP_BOT/TOP registers
0179      * Under VMID0, logical address == MC address. AGP
0180      * aperture maps to physical bus or IOVA addressed.
0181      * AGP aperture is used to simulate FB in ZFB case.
0182      * AGP aperture is also used for page table in system
0183      * memory (mainly for APU).
0184      *
0185      */
0186     u64         agp_size;
0187     u64         agp_start;
0188     u64         agp_end;
0189     /* GART aperture start and end in MC address space
0190      * Driver find a hole in the MC address space
0191      * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
0192      * registers
0193      * Under VMID0, logical address inside GART aperture will
0194      * be translated through gpuvm gart page table to access
0195      * paged system memory
0196      */
0197     u64         gart_size;
0198     u64         gart_start;
0199     u64         gart_end;
0200     /* Frame buffer aperture of this GPU device. Different from
0201      * fb_start (see below), this only covers the local GPU device.
0202      * If driver uses FB aperture to access FB, driver get fb_start from
0203      * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start
0204      * of this local device by adding an offset inside the XGMI hive.
0205      * If driver uses GART table for VMID0 FB access, driver finds a hole in
0206      * VMID0's virtual address space to place the SYSVM aperture inside
0207      * which the first part is vram and the second part is gart (covering
0208      * system ram).
0209      */
0210     u64         vram_start;
0211     u64         vram_end;
0212     /* FB region , it's same as local vram region in single GPU, in XGMI
0213      * configuration, this region covers all GPUs in the same hive ,
0214      * each GPU in the hive has the same view of this FB region .
0215      * GPU0's vram starts at offset (0 * segment size) ,
0216      * GPU1 starts at offset (1 * segment size), etc.
0217      */
0218     u64         fb_start;
0219     u64         fb_end;
0220     unsigned        vram_width;
0221     u64         real_vram_size;
0222     int         vram_mtrr;
0223     u64                     mc_mask;
0224     const struct firmware   *fw;    /* MC firmware */
0225     uint32_t                fw_version;
0226     struct amdgpu_irq_src   vm_fault;
0227     uint32_t        vram_type;
0228     uint8_t         vram_vendor;
0229     uint32_t                srbm_soft_reset;
0230     bool            prt_warning;
0231     uint32_t        sdpif_register;
0232     /* apertures */
0233     u64         shared_aperture_start;
0234     u64         shared_aperture_end;
0235     u64         private_aperture_start;
0236     u64         private_aperture_end;
0237     /* protects concurrent invalidation */
0238     spinlock_t      invalidate_lock;
0239     bool            translate_further;
0240     struct kfd_vm_fault_info *vm_fault_info;
0241     atomic_t        vm_fault_info_updated;
0242
0243     struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
0244     struct {
0245         uint64_t    idx:AMDGPU_GMC_FAULT_RING_ORDER;
0246     } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
0247     uint64_t        last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
0248
0249     bool tmz_enabled;
0250
0251     const struct amdgpu_gmc_funcs   *gmc_funcs;
0252
0253     struct amdgpu_xgmi xgmi;
0254     struct amdgpu_irq_src   ecc_irq;
0255     int noretry;
0256
0257     uint32_t    vmid0_page_table_block_size;
0258     uint32_t    vmid0_page_table_depth;
0259     struct amdgpu_bo        *pdb0_bo;
0260     /* CPU kmapped address of pdb0*/
0261     void                *ptr_pdb0;
0262
0263     /* MALL size */
0264     u64 mall_size;
0265     /* number of UMC instances */
0266     int num_umc;
0267 };
0268
0269 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
0270 #define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
0271     ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
0272     ((adev), (pasid), (type), (allhub)))
0273 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
0274 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
0275 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
0276 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
0277 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
0278 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
0279
0280 /**
0281  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
0282  *
0283  * @adev: amdgpu_device pointer
0284  *
0285  * Returns:
0286  * True if full VRAM is visible through the BAR
0287  */
0288 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
0289 {
0290     WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
0291
0292     return (gmc->real_vram_size == gmc->visible_vram_size);
0293 }
0294
0295 /**
0296  * amdgpu_gmc_sign_extend - sign extend the given gmc address
0297  *
0298  * @addr: address to extend
0299  */
0300 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
0301 {
0302     if (addr >= AMDGPU_GMC_HOLE_START)
0303         addr |= AMDGPU_GMC_HOLE_END;
0304
0305     return addr;
0306 }
0307
0308 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);
0309 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
0310                    uint64_t *addr, uint64_t *flags);
0311 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
0312                 uint32_t gpu_page_idx, uint64_t addr,
0313                 uint64_t flags);
0314 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
0315 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
0316 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc);
0317 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
0318                   u64 base);
0319 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
0320                   struct amdgpu_gmc *mc);
0321 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
0322                  struct amdgpu_gmc *mc);
0323 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
0324                   struct amdgpu_ih_ring *ih, uint64_t addr,
0325                   uint16_t pasid, uint64_t timestamp);
0326 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
0327                      uint16_t pasid);
0328 int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev);
0329 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
0330 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
0331 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
0332
0333 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev);
0334 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev);
0335
0336 extern void
0337 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
0338                   bool enable);
0339
0340 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
0341
0342 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
0343 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
0344 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
0345 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
0346 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
0347 #endif