amd/amdgpu/amdgpu_gfx.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_GFX_H__
0025 #define __AMDGPU_GFX_H__
0026
0027 /*
0028  * GFX stuff
0029  */
0030 #include "clearstate_defs.h"
0031 #include "amdgpu_ring.h"
0032 #include "amdgpu_rlc.h"
0033 #include "amdgpu_imu.h"
0034 #include "soc15.h"
0035 #include "amdgpu_ras.h"
0036
0037 /* GFX current status */
0038 #define AMDGPU_GFX_NORMAL_MODE          0x00000000L
0039 #define AMDGPU_GFX_SAFE_MODE            0x00000001L
0040 #define AMDGPU_GFX_PG_DISABLED_MODE     0x00000002L
0041 #define AMDGPU_GFX_CG_DISABLED_MODE     0x00000004L
0042 #define AMDGPU_GFX_LBPW_DISABLED_MODE       0x00000008L
0043
0044 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
0045 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
0046
0047 enum amdgpu_gfx_pipe_priority {
0048     AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
0049     AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
0050 };
0051
0052 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
0053 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
0054
0055 struct amdgpu_mec {
0056     struct amdgpu_bo    *hpd_eop_obj;
0057     u64         hpd_eop_gpu_addr;
0058     struct amdgpu_bo    *mec_fw_obj;
0059     u64         mec_fw_gpu_addr;
0060     struct amdgpu_bo    *mec_fw_data_obj;
0061     u64         mec_fw_data_gpu_addr;
0062
0063     u32 num_mec;
0064     u32 num_pipe_per_mec;
0065     u32 num_queue_per_pipe;
0066     void            *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
0067
0068     /* These are the resources for which amdgpu takes ownership */
0069     DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
0070 };
0071
0072 enum amdgpu_unmap_queues_action {
0073     PREEMPT_QUEUES = 0,
0074     RESET_QUEUES,
0075     DISABLE_PROCESS_QUEUES,
0076     PREEMPT_QUEUES_NO_UNMAP,
0077 };
0078
0079 struct kiq_pm4_funcs {
0080     /* Support ASIC-specific kiq pm4 packets*/
0081     void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
0082                     uint64_t queue_mask);
0083     void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
0084                     struct amdgpu_ring *ring);
0085     void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
0086                  struct amdgpu_ring *ring,
0087                  enum amdgpu_unmap_queues_action action,
0088                  u64 gpu_addr, u64 seq);
0089     void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
0090                     struct amdgpu_ring *ring,
0091                     u64 addr,
0092                     u64 seq);
0093     void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
0094                 uint16_t pasid, uint32_t flush_type,
0095                 bool all_hub);
0096     /* Packet sizes */
0097     int set_resources_size;
0098     int map_queues_size;
0099     int unmap_queues_size;
0100     int query_status_size;
0101     int invalidate_tlbs_size;
0102 };
0103
0104 struct amdgpu_kiq {
0105     u64         eop_gpu_addr;
0106     struct amdgpu_bo    *eop_obj;
0107     spinlock_t              ring_lock;
0108     struct amdgpu_ring  ring;
0109     struct amdgpu_irq_src   irq;
0110     const struct kiq_pm4_funcs *pmf;
0111 };
0112
0113 /*
0114  * GFX configurations
0115  */
0116 #define AMDGPU_GFX_MAX_SE 4
0117 #define AMDGPU_GFX_MAX_SH_PER_SE 2
0118
0119 struct amdgpu_rb_config {
0120     uint32_t rb_backend_disable;
0121     uint32_t user_rb_backend_disable;
0122     uint32_t raster_config;
0123     uint32_t raster_config_1;
0124 };
0125
0126 struct gb_addr_config {
0127     uint16_t pipe_interleave_size;
0128     uint8_t num_pipes;
0129     uint8_t max_compress_frags;
0130     uint8_t num_banks;
0131     uint8_t num_se;
0132     uint8_t num_rb_per_se;
0133     uint8_t num_pkrs;
0134 };
0135
0136 struct amdgpu_gfx_config {
0137     unsigned max_shader_engines;
0138     unsigned max_tile_pipes;
0139     unsigned max_cu_per_sh;
0140     unsigned max_sh_per_se;
0141     unsigned max_backends_per_se;
0142     unsigned max_texture_channel_caches;
0143     unsigned max_gprs;
0144     unsigned max_gs_threads;
0145     unsigned max_hw_contexts;
0146     unsigned sc_prim_fifo_size_frontend;
0147     unsigned sc_prim_fifo_size_backend;
0148     unsigned sc_hiz_tile_fifo_size;
0149     unsigned sc_earlyz_tile_fifo_size;
0150
0151     unsigned num_tile_pipes;
0152     unsigned backend_enable_mask;
0153     unsigned mem_max_burst_length_bytes;
0154     unsigned mem_row_size_in_kb;
0155     unsigned shader_engine_tile_size;
0156     unsigned num_gpus;
0157     unsigned multi_gpu_tile_size;
0158     unsigned mc_arb_ramcfg;
0159     unsigned num_banks;
0160     unsigned num_ranks;
0161     unsigned gb_addr_config;
0162     unsigned num_rbs;
0163     unsigned gs_vgt_table_depth;
0164     unsigned gs_prim_buffer_depth;
0165
0166     uint32_t tile_mode_array[32];
0167     uint32_t macrotile_mode_array[16];
0168
0169     struct gb_addr_config gb_addr_config_fields;
0170     struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
0171
0172     /* gfx configure feature */
0173     uint32_t double_offchip_lds_buf;
0174     /* cached value of DB_DEBUG2 */
0175     uint32_t db_debug2;
0176     /* gfx10 specific config */
0177     uint32_t num_sc_per_sh;
0178     uint32_t num_packer_per_sc;
0179     uint32_t pa_sc_tile_steering_override;
0180     uint64_t tcc_disabled_mask;
0181     uint32_t gc_num_tcp_per_sa;
0182     uint32_t gc_num_sdp_interface;
0183     uint32_t gc_num_tcps;
0184     uint32_t gc_num_tcp_per_wpg;
0185     uint32_t gc_tcp_l1_size;
0186     uint32_t gc_num_sqc_per_wgp;
0187     uint32_t gc_l1_instruction_cache_size_per_sqc;
0188     uint32_t gc_l1_data_cache_size_per_sqc;
0189     uint32_t gc_gl1c_per_sa;
0190     uint32_t gc_gl1c_size_per_instance;
0191     uint32_t gc_gl2c_per_gpu;
0192 };
0193
0194 struct amdgpu_cu_info {
0195     uint32_t simd_per_cu;
0196     uint32_t max_waves_per_simd;
0197     uint32_t wave_front_size;
0198     uint32_t max_scratch_slots_per_cu;
0199     uint32_t lds_size;
0200
0201     /* total active CU number */
0202     uint32_t number;
0203     uint32_t ao_cu_mask;
0204     uint32_t ao_cu_bitmap[4][4];
0205     uint32_t bitmap[4][4];
0206 };
0207
0208 struct amdgpu_gfx_ras {
0209     struct amdgpu_ras_block_object  ras_block;
0210     void (*enable_watchdog_timer)(struct amdgpu_device *adev);
0211     bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
0212 };
0213
0214 struct amdgpu_gfx_funcs {
0215     /* get the gpu clock counter */
0216     uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
0217     void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
0218                  u32 sh_num, u32 instance);
0219     void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
0220                    uint32_t wave, uint32_t *dst, int *no_fields);
0221     void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
0222                 uint32_t wave, uint32_t thread, uint32_t start,
0223                 uint32_t size, uint32_t *dst);
0224     void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
0225                 uint32_t wave, uint32_t start, uint32_t size,
0226                 uint32_t *dst);
0227     void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
0228                  u32 queue, u32 vmid);
0229     void (*init_spm_golden)(struct amdgpu_device *adev);
0230     void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
0231 };
0232
0233 struct sq_work {
0234     struct work_struct  work;
0235     unsigned ih_data;
0236 };
0237
0238 struct amdgpu_pfp {
0239     struct amdgpu_bo        *pfp_fw_obj;
0240     uint64_t            pfp_fw_gpu_addr;
0241     uint32_t            *pfp_fw_ptr;
0242
0243     struct amdgpu_bo        *pfp_fw_data_obj;
0244     uint64_t            pfp_fw_data_gpu_addr;
0245     uint32_t            *pfp_fw_data_ptr;
0246 };
0247
0248 struct amdgpu_ce {
0249     struct amdgpu_bo        *ce_fw_obj;
0250     uint64_t            ce_fw_gpu_addr;
0251     uint32_t            *ce_fw_ptr;
0252 };
0253
0254 struct amdgpu_me {
0255     struct amdgpu_bo        *me_fw_obj;
0256     uint64_t            me_fw_gpu_addr;
0257     uint32_t            *me_fw_ptr;
0258
0259     struct amdgpu_bo        *me_fw_data_obj;
0260     uint64_t            me_fw_data_gpu_addr;
0261     uint32_t            *me_fw_data_ptr;
0262
0263     uint32_t            num_me;
0264     uint32_t            num_pipe_per_me;
0265     uint32_t            num_queue_per_pipe;
0266     void                *mqd_backup[AMDGPU_MAX_GFX_RINGS];
0267
0268     /* These are the resources for which amdgpu takes ownership */
0269     DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
0270 };
0271
0272 struct amdgpu_gfx {
0273     struct mutex            gpu_clock_mutex;
0274     struct amdgpu_gfx_config    config;
0275     struct amdgpu_rlc       rlc;
0276     struct amdgpu_pfp       pfp;
0277     struct amdgpu_ce        ce;
0278     struct amdgpu_me        me;
0279     struct amdgpu_mec       mec;
0280     struct amdgpu_kiq       kiq;
0281     struct amdgpu_imu       imu;
0282     bool                rs64_enable; /* firmware format */
0283     const struct firmware       *me_fw; /* ME firmware */
0284     uint32_t            me_fw_version;
0285     const struct firmware       *pfp_fw; /* PFP firmware */
0286     uint32_t            pfp_fw_version;
0287     const struct firmware       *ce_fw; /* CE firmware */
0288     uint32_t            ce_fw_version;
0289     const struct firmware       *rlc_fw; /* RLC firmware */
0290     uint32_t            rlc_fw_version;
0291     const struct firmware       *mec_fw; /* MEC firmware */
0292     uint32_t            mec_fw_version;
0293     const struct firmware       *mec2_fw; /* MEC2 firmware */
0294     uint32_t            mec2_fw_version;
0295     const struct firmware       *imu_fw; /* IMU firmware */
0296     uint32_t            imu_fw_version;
0297     uint32_t            me_feature_version;
0298     uint32_t            ce_feature_version;
0299     uint32_t            pfp_feature_version;
0300     uint32_t            rlc_feature_version;
0301     uint32_t            rlc_srlc_fw_version;
0302     uint32_t            rlc_srlc_feature_version;
0303     uint32_t            rlc_srlg_fw_version;
0304     uint32_t            rlc_srlg_feature_version;
0305     uint32_t            rlc_srls_fw_version;
0306     uint32_t            rlc_srls_feature_version;
0307     uint32_t            rlcp_ucode_version;
0308     uint32_t            rlcp_ucode_feature_version;
0309     uint32_t            rlcv_ucode_version;
0310     uint32_t            rlcv_ucode_feature_version;
0311     uint32_t            mec_feature_version;
0312     uint32_t            mec2_feature_version;
0313     bool                mec_fw_write_wait;
0314     bool                me_fw_write_wait;
0315     bool                cp_fw_write_wait;
0316     struct amdgpu_ring      gfx_ring[AMDGPU_MAX_GFX_RINGS];
0317     unsigned            num_gfx_rings;
0318     struct amdgpu_ring      compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
0319     unsigned            num_compute_rings;
0320     struct amdgpu_irq_src       eop_irq;
0321     struct amdgpu_irq_src       priv_reg_irq;
0322     struct amdgpu_irq_src       priv_inst_irq;
0323     struct amdgpu_irq_src       cp_ecc_error_irq;
0324     struct amdgpu_irq_src       sq_irq;
0325     struct sq_work          sq_work;
0326
0327     /* gfx status */
0328     uint32_t            gfx_current_status;
0329     /* ce ram size*/
0330     unsigned            ce_ram_size;
0331     struct amdgpu_cu_info       cu_info;
0332     const struct amdgpu_gfx_funcs   *funcs;
0333
0334     /* reset mask */
0335     uint32_t                        grbm_soft_reset;
0336     uint32_t                        srbm_soft_reset;
0337
0338     /* gfx off */
0339     bool                            gfx_off_state; /* true: enabled, false: disabled */
0340     struct mutex                    gfx_off_mutex;
0341     uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
0342     struct delayed_work             gfx_off_delay_work;
0343
0344     /* pipe reservation */
0345     struct mutex            pipe_reserve_mutex;
0346     DECLARE_BITMAP          (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
0347
0348     /*ras */
0349     struct ras_common_if        *ras_if;
0350     struct amdgpu_gfx_ras       *ras;
0351
0352     bool                is_poweron;
0353 };
0354
0355 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
0356 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
0357 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
0358 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
0359
0360 /**
0361  * amdgpu_gfx_create_bitmask - create a bitmask
0362  *
0363  * @bit_width: length of the mask
0364  *
0365  * create a variable length bit mask.
0366  * Returns the bitmask.
0367  */
0368 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
0369 {
0370     return (u32)((1ULL << bit_width) - 1);
0371 }
0372
0373 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
0374                  unsigned max_sh);
0375
0376 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
0377                  struct amdgpu_ring *ring,
0378                  struct amdgpu_irq_src *irq);
0379
0380 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
0381
0382 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
0383 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
0384             unsigned hpd_size);
0385
0386 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
0387                unsigned mqd_size);
0388 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
0389 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
0390 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
0391
0392 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
0393 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
0394
0395 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
0396                 int pipe, int queue);
0397 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
0398                  int *mec, int *pipe, int *queue);
0399 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
0400                      int pipe, int queue);
0401 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
0402                            struct amdgpu_ring *ring);
0403 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
0404                         struct amdgpu_ring *ring);
0405 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
0406                    int pipe, int queue);
0407 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
0408                 int *me, int *pipe, int *queue);
0409 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
0410                     int pipe, int queue);
0411 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
0412 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
0413 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
0414 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
0415         void *err_data,
0416         struct amdgpu_iv_entry *entry);
0417 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
0418                   struct amdgpu_irq_src *source,
0419                   struct amdgpu_iv_entry *entry);
0420 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
0421 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
0422 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
0423 #endif