amd/amdgpu/amdgpu_gart.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_GART_H__
0025 #define __AMDGPU_GART_H__
0026
0027 #include <linux/types.h>
0028
0029 /*
0030  * GART structures, functions & helpers
0031  */
0032 struct amdgpu_device;
0033 struct amdgpu_bo;
0034
0035 #define AMDGPU_GPU_PAGE_SIZE 4096
0036 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
0037 #define AMDGPU_GPU_PAGE_SHIFT 12
0038 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
0039
0040 #define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
0041
0042 struct amdgpu_gart {
0043     struct amdgpu_bo        *bo;
0044     /* CPU kmapped address of gart table */
0045     void                *ptr;
0046     unsigned            num_gpu_pages;
0047     unsigned            num_cpu_pages;
0048     unsigned            table_size;
0049
0050     /* Asic default pte flags */
0051     uint64_t            gart_pte_flags;
0052 };
0053
0054 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
0055 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
0056 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
0057 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
0058 int amdgpu_gart_init(struct amdgpu_device *adev);
0059 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
0060 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
0061             int pages);
0062 void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
0063              int pages, dma_addr_t *dma_addr, uint64_t flags,
0064              void *dst);
0065 void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
0066               int pages, dma_addr_t *dma_addr, uint64_t flags);
0067 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
0068 #endif