amd/amdgpu/amdgpu_df.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_DF_H__
0025 #define __AMDGPU_DF_H__
0026
0027 struct amdgpu_df_hash_status {
0028     bool hash_64k;
0029     bool hash_2m;
0030     bool hash_1g;
0031 };
0032
0033 struct amdgpu_df_funcs {
0034     void (*sw_init)(struct amdgpu_device *adev);
0035     void (*sw_fini)(struct amdgpu_device *adev);
0036     void (*enable_broadcast_mode)(struct amdgpu_device *adev,
0037                       bool enable);
0038     u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
0039     u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
0040     void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
0041                          bool enable);
0042     void (*get_clockgating_state)(struct amdgpu_device *adev,
0043                       u64 *flags);
0044     void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
0045                         bool enable);
0046     int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
0047                      int counter_idx, int is_add);
0048     int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
0049                      int counter_idx, int is_remove);
0050     void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
0051                      int counter_idx, uint64_t *count);
0052     uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
0053     void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
0054              uint32_t ficadl_val, uint32_t ficadh_val);
0055     bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
0056 };
0057
0058 struct amdgpu_df {
0059     struct amdgpu_df_hash_status    hash_status;
0060     const struct amdgpu_df_funcs    *funcs;
0061 };
0062
0063 #endif /* __AMDGPU_DF_H__ */