amd/amdgpu/amdgpu_ctx.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_CTX_H__
0024 #define __AMDGPU_CTX_H__
0025
0026 #include <linux/ktime.h>
0027 #include <linux/types.h>
0028
0029 #include "amdgpu_ring.h"
0030
0031 struct drm_device;
0032 struct drm_file;
0033 struct amdgpu_fpriv;
0034 struct amdgpu_ctx_mgr;
0035
0036 #define AMDGPU_MAX_ENTITY_NUM 4
0037
0038 struct amdgpu_ctx_entity {
0039     uint32_t        hw_ip;
0040     uint64_t        sequence;
0041     struct drm_sched_entity entity;
0042     struct dma_fence    *fences[];
0043 };
0044
0045 struct amdgpu_ctx {
0046     struct kref         refcount;
0047     struct amdgpu_ctx_mgr       *mgr;
0048     unsigned            reset_counter;
0049     unsigned            reset_counter_query;
0050     uint32_t            vram_lost_counter;
0051     spinlock_t          ring_lock;
0052     struct amdgpu_ctx_entity    *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
0053     bool                preamble_presented;
0054     int32_t             init_priority;
0055     int32_t             override_priority;
0056     struct mutex            lock;
0057     atomic_t            guilty;
0058     unsigned long           ras_counter_ce;
0059     unsigned long           ras_counter_ue;
0060     uint32_t            stable_pstate;
0061 };
0062
0063 struct amdgpu_ctx_mgr {
0064     struct amdgpu_device    *adev;
0065     struct mutex        lock;
0066     /* protected by lock */
0067     struct idr      ctx_handles;
0068     atomic64_t      time_spend[AMDGPU_HW_IP_NUM];
0069 };
0070
0071 extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
0072
0073 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
0074 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
0075
0076 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
0077               u32 ring, struct drm_sched_entity **entity);
0078 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
0079                   struct drm_sched_entity *entity,
0080                   struct dma_fence *fence);
0081 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
0082                        struct drm_sched_entity *entity,
0083                        uint64_t seq);
0084 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
0085 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, int32_t ctx_prio);
0086
0087 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
0088              struct drm_file *filp);
0089
0090 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
0091                    struct drm_sched_entity *entity);
0092
0093 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr,
0094              struct amdgpu_device *adev);
0095 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
0096 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
0097 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0098 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr,
0099               ktime_t usage[AMDGPU_HW_IP_NUM]);
0100
0101 #endif