amd/amdgpu/amdgpu_connectors.c

0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026
0027 #include <drm/display/drm_dp_helper.h>
0028 #include <drm/drm_edid.h>
0029 #include <drm/drm_fb_helper.h>
0030 #include <drm/drm_probe_helper.h>
0031 #include <drm/amdgpu_drm.h>
0032 #include "amdgpu.h"
0033 #include "atom.h"
0034 #include "atombios_encoders.h"
0035 #include "atombios_dp.h"
0036 #include "amdgpu_connectors.h"
0037 #include "amdgpu_i2c.h"
0038 #include "amdgpu_display.h"
0039
0040 #include <linux/pm_runtime.h>
0041
0042 void amdgpu_connector_hotplug(struct drm_connector *connector)
0043 {
0044     struct drm_device *dev = connector->dev;
0045     struct amdgpu_device *adev = drm_to_adev(dev);
0046     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0047
0048     /* bail if the connector does not have hpd pin, e.g.,
0049      * VGA, TV, etc.
0050      */
0051     if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
0052         return;
0053
0054     amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
0055
0056     /* if the connector is already off, don't turn it back on */
0057     if (connector->dpms != DRM_MODE_DPMS_ON)
0058         return;
0059
0060     /* just deal with DP (not eDP) here. */
0061     if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
0062         struct amdgpu_connector_atom_dig *dig_connector =
0063             amdgpu_connector->con_priv;
0064
0065         /* if existing sink type was not DP no need to retrain */
0066         if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
0067             return;
0068
0069         /* first get sink type as it may be reset after (un)plug */
0070         dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
0071         /* don't do anything if sink is not display port, i.e.,
0072          * passive dp->(dvi|hdmi) adaptor
0073          */
0074         if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
0075             amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
0076             amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
0077             /* Don't start link training before we have the DPCD */
0078             if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
0079                 return;
0080
0081             /* Turn the connector off and back on immediately, which
0082              * will trigger link training
0083              */
0084             drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
0085             drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
0086         }
0087     }
0088 }
0089
0090 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
0091 {
0092     struct drm_crtc *crtc = encoder->crtc;
0093
0094     if (crtc && crtc->enabled) {
0095         drm_crtc_helper_set_mode(crtc, &crtc->mode,
0096                      crtc->x, crtc->y, crtc->primary->fb);
0097     }
0098 }
0099
0100 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
0101 {
0102     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0103     struct amdgpu_connector_atom_dig *dig_connector;
0104     int bpc = 8;
0105     unsigned mode_clock, max_tmds_clock;
0106
0107     switch (connector->connector_type) {
0108     case DRM_MODE_CONNECTOR_DVII:
0109     case DRM_MODE_CONNECTOR_HDMIB:
0110         if (amdgpu_connector->use_digital) {
0111             if (connector->display_info.is_hdmi) {
0112                 if (connector->display_info.bpc)
0113                     bpc = connector->display_info.bpc;
0114             }
0115         }
0116         break;
0117     case DRM_MODE_CONNECTOR_DVID:
0118     case DRM_MODE_CONNECTOR_HDMIA:
0119         if (connector->display_info.is_hdmi) {
0120             if (connector->display_info.bpc)
0121                 bpc = connector->display_info.bpc;
0122         }
0123         break;
0124     case DRM_MODE_CONNECTOR_DisplayPort:
0125         dig_connector = amdgpu_connector->con_priv;
0126         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
0127             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
0128             connector->display_info.is_hdmi) {
0129             if (connector->display_info.bpc)
0130                 bpc = connector->display_info.bpc;
0131         }
0132         break;
0133     case DRM_MODE_CONNECTOR_eDP:
0134     case DRM_MODE_CONNECTOR_LVDS:
0135         if (connector->display_info.bpc)
0136             bpc = connector->display_info.bpc;
0137         else {
0138             const struct drm_connector_helper_funcs *connector_funcs =
0139                 connector->helper_private;
0140             struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
0141             struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
0142             struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
0143
0144             if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
0145                 bpc = 6;
0146             else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
0147                 bpc = 8;
0148         }
0149         break;
0150     }
0151
0152     if (connector->display_info.is_hdmi) {
0153         /*
0154          * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
0155          * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
0156          * 12 bpc is always supported on hdmi deep color sinks, as this is
0157          * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
0158          */
0159         if (bpc > 12) {
0160             DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
0161                   connector->name, bpc);
0162             bpc = 12;
0163         }
0164
0165         /* Any defined maximum tmds clock limit we must not exceed? */
0166         if (connector->display_info.max_tmds_clock > 0) {
0167             /* mode_clock is clock in kHz for mode to be modeset on this connector */
0168             mode_clock = amdgpu_connector->pixelclock_for_modeset;
0169
0170             /* Maximum allowable input clock in kHz */
0171             max_tmds_clock = connector->display_info.max_tmds_clock;
0172
0173             DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
0174                   connector->name, mode_clock, max_tmds_clock);
0175
0176             /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
0177             if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
0178                 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
0179                     (mode_clock * 5/4 <= max_tmds_clock))
0180                     bpc = 10;
0181                 else
0182                     bpc = 8;
0183
0184                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
0185                       connector->name, bpc);
0186             }
0187
0188             if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
0189                 bpc = 8;
0190                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
0191                       connector->name, bpc);
0192             }
0193         } else if (bpc > 8) {
0194             /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
0195             DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
0196                   connector->name);
0197             bpc = 8;
0198         }
0199     }
0200
0201     if ((amdgpu_deep_color == 0) && (bpc > 8)) {
0202         DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
0203               connector->name);
0204         bpc = 8;
0205     }
0206
0207     DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
0208           connector->name, connector->display_info.bpc, bpc);
0209
0210     return bpc;
0211 }
0212
0213 static void
0214 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
0215                       enum drm_connector_status status)
0216 {
0217     struct drm_encoder *best_encoder;
0218     struct drm_encoder *encoder;
0219     const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
0220     bool connected;
0221
0222     best_encoder = connector_funcs->best_encoder(connector);
0223
0224     drm_connector_for_each_possible_encoder(connector, encoder) {
0225         if ((encoder == best_encoder) && (status == connector_status_connected))
0226             connected = true;
0227         else
0228             connected = false;
0229
0230         amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
0231     }
0232 }
0233
0234 static struct drm_encoder *
0235 amdgpu_connector_find_encoder(struct drm_connector *connector,
0236                    int encoder_type)
0237 {
0238     struct drm_encoder *encoder;
0239
0240     drm_connector_for_each_possible_encoder(connector, encoder) {
0241         if (encoder->encoder_type == encoder_type)
0242             return encoder;
0243     }
0244
0245     return NULL;
0246 }
0247
0248 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
0249 {
0250     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0251     struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
0252
0253     if (amdgpu_connector->edid) {
0254         return amdgpu_connector->edid;
0255     } else if (edid_blob) {
0256         struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
0257         if (edid)
0258             amdgpu_connector->edid = edid;
0259     }
0260     return amdgpu_connector->edid;
0261 }
0262
0263 static struct edid *
0264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
0265 {
0266     struct edid *edid;
0267
0268     if (adev->mode_info.bios_hardcoded_edid) {
0269         edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
0270         if (edid) {
0271             memcpy((unsigned char *)edid,
0272                    (unsigned char *)adev->mode_info.bios_hardcoded_edid,
0273                    adev->mode_info.bios_hardcoded_edid_size);
0274             return edid;
0275         }
0276     }
0277     return NULL;
0278 }
0279
0280 static void amdgpu_connector_get_edid(struct drm_connector *connector)
0281 {
0282     struct drm_device *dev = connector->dev;
0283     struct amdgpu_device *adev = drm_to_adev(dev);
0284     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0285
0286     if (amdgpu_connector->edid)
0287         return;
0288
0289     /* on hw with routers, select right port */
0290     if (amdgpu_connector->router.ddc_valid)
0291         amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
0292
0293     if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
0294          ENCODER_OBJECT_ID_NONE) &&
0295         amdgpu_connector->ddc_bus->has_aux) {
0296         amdgpu_connector->edid = drm_get_edid(connector,
0297                               &amdgpu_connector->ddc_bus->aux.ddc);
0298     } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
0299            (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
0300         struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
0301
0302         if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
0303              dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
0304             amdgpu_connector->ddc_bus->has_aux)
0305             amdgpu_connector->edid = drm_get_edid(connector,
0306                                   &amdgpu_connector->ddc_bus->aux.ddc);
0307         else if (amdgpu_connector->ddc_bus)
0308             amdgpu_connector->edid = drm_get_edid(connector,
0309                                   &amdgpu_connector->ddc_bus->adapter);
0310     } else if (amdgpu_connector->ddc_bus) {
0311         amdgpu_connector->edid = drm_get_edid(connector,
0312                               &amdgpu_connector->ddc_bus->adapter);
0313     }
0314
0315     if (!amdgpu_connector->edid) {
0316         /* some laptops provide a hardcoded edid in rom for LCDs */
0317         if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
0318              (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
0319             amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
0320             drm_connector_update_edid_property(connector, amdgpu_connector->edid);
0321         }
0322     }
0323 }
0324
0325 static void amdgpu_connector_free_edid(struct drm_connector *connector)
0326 {
0327     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0328
0329     kfree(amdgpu_connector->edid);
0330     amdgpu_connector->edid = NULL;
0331     drm_connector_update_edid_property(connector, NULL);
0332 }
0333
0334 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
0335 {
0336     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0337     int ret;
0338
0339     if (amdgpu_connector->edid) {
0340         drm_connector_update_edid_property(connector, amdgpu_connector->edid);
0341         ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
0342         return ret;
0343     }
0344     drm_connector_update_edid_property(connector, NULL);
0345     return 0;
0346 }
0347
0348 static struct drm_encoder *
0349 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
0350 {
0351     struct drm_encoder *encoder;
0352
0353     /* pick the first one */
0354     drm_connector_for_each_possible_encoder(connector, encoder)
0355         return encoder;
0356
0357     return NULL;
0358 }
0359
0360 static void amdgpu_get_native_mode(struct drm_connector *connector)
0361 {
0362     struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
0363     struct amdgpu_encoder *amdgpu_encoder;
0364
0365     if (encoder == NULL)
0366         return;
0367
0368     amdgpu_encoder = to_amdgpu_encoder(encoder);
0369
0370     if (!list_empty(&connector->probed_modes)) {
0371         struct drm_display_mode *preferred_mode =
0372             list_first_entry(&connector->probed_modes,
0373                      struct drm_display_mode, head);
0374
0375         amdgpu_encoder->native_mode = *preferred_mode;
0376     } else {
0377         amdgpu_encoder->native_mode.clock = 0;
0378     }
0379 }
0380
0381 static struct drm_display_mode *
0382 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
0383 {
0384     struct drm_device *dev = encoder->dev;
0385     struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
0386     struct drm_display_mode *mode = NULL;
0387     struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
0388
0389     if (native_mode->hdisplay != 0 &&
0390         native_mode->vdisplay != 0 &&
0391         native_mode->clock != 0) {
0392         mode = drm_mode_duplicate(dev, native_mode);
0393         if (!mode)
0394             return NULL;
0395
0396         mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
0397         drm_mode_set_name(mode);
0398
0399         DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
0400     } else if (native_mode->hdisplay != 0 &&
0401            native_mode->vdisplay != 0) {
0402         /* mac laptops without an edid */
0403         /* Note that this is not necessarily the exact panel mode,
0404          * but an approximation based on the cvt formula.  For these
0405          * systems we should ideally read the mode info out of the
0406          * registers or add a mode table, but this works and is much
0407          * simpler.
0408          */
0409         mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
0410         if (!mode)
0411             return NULL;
0412
0413         mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
0414         DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
0415     }
0416     return mode;
0417 }
0418
0419 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
0420                            struct drm_connector *connector)
0421 {
0422     struct drm_device *dev = encoder->dev;
0423     struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
0424     struct drm_display_mode *mode = NULL;
0425     struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
0426     int i;
0427     static const struct mode_size {
0428         int w;
0429         int h;
0430     } common_modes[17] = {
0431         { 640,  480},
0432         { 720,  480},
0433         { 800,  600},
0434         { 848,  480},
0435         {1024,  768},
0436         {1152,  768},
0437         {1280,  720},
0438         {1280,  800},
0439         {1280,  854},
0440         {1280,  960},
0441         {1280, 1024},
0442         {1440,  900},
0443         {1400, 1050},
0444         {1680, 1050},
0445         {1600, 1200},
0446         {1920, 1080},
0447         {1920, 1200}
0448     };
0449
0450     for (i = 0; i < 17; i++) {
0451         if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
0452             if (common_modes[i].w > 1024 ||
0453                 common_modes[i].h > 768)
0454                 continue;
0455         }
0456         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
0457             if (common_modes[i].w > native_mode->hdisplay ||
0458                 common_modes[i].h > native_mode->vdisplay ||
0459                 (common_modes[i].w == native_mode->hdisplay &&
0460                  common_modes[i].h == native_mode->vdisplay))
0461                 continue;
0462         }
0463         if (common_modes[i].w < 320 || common_modes[i].h < 200)
0464             continue;
0465
0466         mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
0467         drm_mode_probed_add(connector, mode);
0468     }
0469 }
0470
0471 static int amdgpu_connector_set_property(struct drm_connector *connector,
0472                       struct drm_property *property,
0473                       uint64_t val)
0474 {
0475     struct drm_device *dev = connector->dev;
0476     struct amdgpu_device *adev = drm_to_adev(dev);
0477     struct drm_encoder *encoder;
0478     struct amdgpu_encoder *amdgpu_encoder;
0479
0480     if (property == adev->mode_info.coherent_mode_property) {
0481         struct amdgpu_encoder_atom_dig *dig;
0482         bool new_coherent_mode;
0483
0484         /* need to find digital encoder on connector */
0485         encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
0486         if (!encoder)
0487             return 0;
0488
0489         amdgpu_encoder = to_amdgpu_encoder(encoder);
0490
0491         if (!amdgpu_encoder->enc_priv)
0492             return 0;
0493
0494         dig = amdgpu_encoder->enc_priv;
0495         new_coherent_mode = val ? true : false;
0496         if (dig->coherent_mode != new_coherent_mode) {
0497             dig->coherent_mode = new_coherent_mode;
0498             amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0499         }
0500     }
0501
0502     if (property == adev->mode_info.audio_property) {
0503         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0504         /* need to find digital encoder on connector */
0505         encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
0506         if (!encoder)
0507             return 0;
0508
0509         amdgpu_encoder = to_amdgpu_encoder(encoder);
0510
0511         if (amdgpu_connector->audio != val) {
0512             amdgpu_connector->audio = val;
0513             amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0514         }
0515     }
0516
0517     if (property == adev->mode_info.dither_property) {
0518         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0519         /* need to find digital encoder on connector */
0520         encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
0521         if (!encoder)
0522             return 0;
0523
0524         amdgpu_encoder = to_amdgpu_encoder(encoder);
0525
0526         if (amdgpu_connector->dither != val) {
0527             amdgpu_connector->dither = val;
0528             amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0529         }
0530     }
0531
0532     if (property == adev->mode_info.underscan_property) {
0533         /* need to find digital encoder on connector */
0534         encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
0535         if (!encoder)
0536             return 0;
0537
0538         amdgpu_encoder = to_amdgpu_encoder(encoder);
0539
0540         if (amdgpu_encoder->underscan_type != val) {
0541             amdgpu_encoder->underscan_type = val;
0542             amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0543         }
0544     }
0545
0546     if (property == adev->mode_info.underscan_hborder_property) {
0547         /* need to find digital encoder on connector */
0548         encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
0549         if (!encoder)
0550             return 0;
0551
0552         amdgpu_encoder = to_amdgpu_encoder(encoder);
0553
0554         if (amdgpu_encoder->underscan_hborder != val) {
0555             amdgpu_encoder->underscan_hborder = val;
0556             amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0557         }
0558     }
0559
0560     if (property == adev->mode_info.underscan_vborder_property) {
0561         /* need to find digital encoder on connector */
0562         encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
0563         if (!encoder)
0564             return 0;
0565
0566         amdgpu_encoder = to_amdgpu_encoder(encoder);
0567
0568         if (amdgpu_encoder->underscan_vborder != val) {
0569             amdgpu_encoder->underscan_vborder = val;
0570             amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0571         }
0572     }
0573
0574     if (property == adev->mode_info.load_detect_property) {
0575         struct amdgpu_connector *amdgpu_connector =
0576             to_amdgpu_connector(connector);
0577
0578         if (val == 0)
0579             amdgpu_connector->dac_load_detect = false;
0580         else
0581             amdgpu_connector->dac_load_detect = true;
0582     }
0583
0584     if (property == dev->mode_config.scaling_mode_property) {
0585         enum amdgpu_rmx_type rmx_type;
0586
0587         if (connector->encoder) {
0588             amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
0589         } else {
0590             const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
0591             amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
0592         }
0593
0594         switch (val) {
0595         default:
0596         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
0597         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
0598         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
0599         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
0600         }
0601         if (amdgpu_encoder->rmx_type == rmx_type)
0602             return 0;
0603
0604         if ((rmx_type != DRM_MODE_SCALE_NONE) &&
0605             (amdgpu_encoder->native_mode.clock == 0))
0606             return 0;
0607
0608         amdgpu_encoder->rmx_type = rmx_type;
0609
0610         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0611     }
0612
0613     return 0;
0614 }
0615
0616 static void
0617 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
0618                     struct drm_connector *connector)
0619 {
0620     struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
0621     struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
0622     struct drm_display_mode *t, *mode;
0623
0624     /* If the EDID preferred mode doesn't match the native mode, use it */
0625     list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
0626         if (mode->type & DRM_MODE_TYPE_PREFERRED) {
0627             if (mode->hdisplay != native_mode->hdisplay ||
0628                 mode->vdisplay != native_mode->vdisplay)
0629                 drm_mode_copy(native_mode, mode);
0630         }
0631     }
0632
0633     /* Try to get native mode details from EDID if necessary */
0634     if (!native_mode->clock) {
0635         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
0636             if (mode->hdisplay == native_mode->hdisplay &&
0637                 mode->vdisplay == native_mode->vdisplay) {
0638                 drm_mode_copy(native_mode, mode);
0639                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
0640                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
0641                 break;
0642             }
0643         }
0644     }
0645
0646     if (!native_mode->clock) {
0647         DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
0648         amdgpu_encoder->rmx_type = RMX_OFF;
0649     }
0650 }
0651
0652 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
0653 {
0654     struct drm_encoder *encoder;
0655     int ret = 0;
0656     struct drm_display_mode *mode;
0657
0658     amdgpu_connector_get_edid(connector);
0659     ret = amdgpu_connector_ddc_get_modes(connector);
0660     if (ret > 0) {
0661         encoder = amdgpu_connector_best_single_encoder(connector);
0662         if (encoder) {
0663             amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
0664             /* add scaled modes */
0665             amdgpu_connector_add_common_modes(encoder, connector);
0666         }
0667         return ret;
0668     }
0669
0670     encoder = amdgpu_connector_best_single_encoder(connector);
0671     if (!encoder)
0672         return 0;
0673
0674     /* we have no EDID modes */
0675     mode = amdgpu_connector_lcd_native_mode(encoder);
0676     if (mode) {
0677         ret = 1;
0678         drm_mode_probed_add(connector, mode);
0679         /* add the width/height from vbios tables if available */
0680         connector->display_info.width_mm = mode->width_mm;
0681         connector->display_info.height_mm = mode->height_mm;
0682         /* add scaled modes */
0683         amdgpu_connector_add_common_modes(encoder, connector);
0684     }
0685
0686     return ret;
0687 }
0688
0689 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
0690                          struct drm_display_mode *mode)
0691 {
0692     struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
0693
0694     if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
0695         return MODE_PANEL;
0696
0697     if (encoder) {
0698         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
0699         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
0700
0701         /* AVIVO hardware supports downscaling modes larger than the panel
0702          * to the panel size, but I'm not sure this is desirable.
0703          */
0704         if ((mode->hdisplay > native_mode->hdisplay) ||
0705             (mode->vdisplay > native_mode->vdisplay))
0706             return MODE_PANEL;
0707
0708         /* if scaling is disabled, block non-native modes */
0709         if (amdgpu_encoder->rmx_type == RMX_OFF) {
0710             if ((mode->hdisplay != native_mode->hdisplay) ||
0711                 (mode->vdisplay != native_mode->vdisplay))
0712                 return MODE_PANEL;
0713         }
0714     }
0715
0716     return MODE_OK;
0717 }
0718
0719 static enum drm_connector_status
0720 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
0721 {
0722     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0723     struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
0724     enum drm_connector_status ret = connector_status_disconnected;
0725     int r;
0726
0727     if (!drm_kms_helper_is_poll_worker()) {
0728         r = pm_runtime_get_sync(connector->dev->dev);
0729         if (r < 0) {
0730             pm_runtime_put_autosuspend(connector->dev->dev);
0731             return connector_status_disconnected;
0732         }
0733     }
0734
0735     if (encoder) {
0736         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
0737         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
0738
0739         /* check if panel is valid */
0740         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
0741             ret = connector_status_connected;
0742
0743     }
0744
0745     /* check for edid as well */
0746     amdgpu_connector_get_edid(connector);
0747     if (amdgpu_connector->edid)
0748         ret = connector_status_connected;
0749     /* check acpi lid status ??? */
0750
0751     amdgpu_connector_update_scratch_regs(connector, ret);
0752
0753     if (!drm_kms_helper_is_poll_worker()) {
0754         pm_runtime_mark_last_busy(connector->dev->dev);
0755         pm_runtime_put_autosuspend(connector->dev->dev);
0756     }
0757
0758     return ret;
0759 }
0760
0761 static void amdgpu_connector_unregister(struct drm_connector *connector)
0762 {
0763     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0764
0765     if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
0766         drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
0767         amdgpu_connector->ddc_bus->has_aux = false;
0768     }
0769 }
0770
0771 static void amdgpu_connector_destroy(struct drm_connector *connector)
0772 {
0773     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0774
0775     amdgpu_connector_free_edid(connector);
0776     kfree(amdgpu_connector->con_priv);
0777     drm_connector_unregister(connector);
0778     drm_connector_cleanup(connector);
0779     kfree(connector);
0780 }
0781
0782 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
0783                           struct drm_property *property,
0784                           uint64_t value)
0785 {
0786     struct drm_device *dev = connector->dev;
0787     struct amdgpu_encoder *amdgpu_encoder;
0788     enum amdgpu_rmx_type rmx_type;
0789
0790     DRM_DEBUG_KMS("\n");
0791     if (property != dev->mode_config.scaling_mode_property)
0792         return 0;
0793
0794     if (connector->encoder)
0795         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
0796     else {
0797         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
0798         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
0799     }
0800
0801     switch (value) {
0802     case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
0803     case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
0804     case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
0805     default:
0806     case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
0807     }
0808     if (amdgpu_encoder->rmx_type == rmx_type)
0809         return 0;
0810
0811     amdgpu_encoder->rmx_type = rmx_type;
0812
0813     amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
0814     return 0;
0815 }
0816
0817
0818 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
0819     .get_modes = amdgpu_connector_lvds_get_modes,
0820     .mode_valid = amdgpu_connector_lvds_mode_valid,
0821     .best_encoder = amdgpu_connector_best_single_encoder,
0822 };
0823
0824 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
0825     .dpms = drm_helper_connector_dpms,
0826     .detect = amdgpu_connector_lvds_detect,
0827     .fill_modes = drm_helper_probe_single_connector_modes,
0828     .early_unregister = amdgpu_connector_unregister,
0829     .destroy = amdgpu_connector_destroy,
0830     .set_property = amdgpu_connector_set_lcd_property,
0831 };
0832
0833 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
0834 {
0835     int ret;
0836
0837     amdgpu_connector_get_edid(connector);
0838     ret = amdgpu_connector_ddc_get_modes(connector);
0839     amdgpu_get_native_mode(connector);
0840
0841     return ret;
0842 }
0843
0844 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
0845                         struct drm_display_mode *mode)
0846 {
0847     struct drm_device *dev = connector->dev;
0848     struct amdgpu_device *adev = drm_to_adev(dev);
0849
0850     /* XXX check mode bandwidth */
0851
0852     if ((mode->clock / 10) > adev->clock.max_pixel_clock)
0853         return MODE_CLOCK_HIGH;
0854
0855     return MODE_OK;
0856 }
0857
0858 static enum drm_connector_status
0859 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
0860 {
0861     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0862     struct drm_encoder *encoder;
0863     const struct drm_encoder_helper_funcs *encoder_funcs;
0864     bool dret = false;
0865     enum drm_connector_status ret = connector_status_disconnected;
0866     int r;
0867
0868     if (!drm_kms_helper_is_poll_worker()) {
0869         r = pm_runtime_get_sync(connector->dev->dev);
0870         if (r < 0) {
0871             pm_runtime_put_autosuspend(connector->dev->dev);
0872             return connector_status_disconnected;
0873         }
0874     }
0875
0876     encoder = amdgpu_connector_best_single_encoder(connector);
0877     if (!encoder)
0878         ret = connector_status_disconnected;
0879
0880     if (amdgpu_connector->ddc_bus)
0881         dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
0882     if (dret) {
0883         amdgpu_connector->detected_by_load = false;
0884         amdgpu_connector_free_edid(connector);
0885         amdgpu_connector_get_edid(connector);
0886
0887         if (!amdgpu_connector->edid) {
0888             DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
0889                     connector->name);
0890             ret = connector_status_connected;
0891         } else {
0892             amdgpu_connector->use_digital =
0893                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
0894
0895             /* some oems have boards with separate digital and analog connectors
0896              * with a shared ddc line (often vga + hdmi)
0897              */
0898             if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
0899                 amdgpu_connector_free_edid(connector);
0900                 ret = connector_status_disconnected;
0901             } else {
0902                 ret = connector_status_connected;
0903             }
0904         }
0905     } else {
0906
0907         /* if we aren't forcing don't do destructive polling */
0908         if (!force) {
0909             /* only return the previous status if we last
0910              * detected a monitor via load.
0911              */
0912             if (amdgpu_connector->detected_by_load)
0913                 ret = connector->status;
0914             goto out;
0915         }
0916
0917         if (amdgpu_connector->dac_load_detect && encoder) {
0918             encoder_funcs = encoder->helper_private;
0919             ret = encoder_funcs->detect(encoder, connector);
0920             if (ret != connector_status_disconnected)
0921                 amdgpu_connector->detected_by_load = true;
0922         }
0923     }
0924
0925     amdgpu_connector_update_scratch_regs(connector, ret);
0926
0927 out:
0928     if (!drm_kms_helper_is_poll_worker()) {
0929         pm_runtime_mark_last_busy(connector->dev->dev);
0930         pm_runtime_put_autosuspend(connector->dev->dev);
0931     }
0932
0933     return ret;
0934 }
0935
0936 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
0937     .get_modes = amdgpu_connector_vga_get_modes,
0938     .mode_valid = amdgpu_connector_vga_mode_valid,
0939     .best_encoder = amdgpu_connector_best_single_encoder,
0940 };
0941
0942 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
0943     .dpms = drm_helper_connector_dpms,
0944     .detect = amdgpu_connector_vga_detect,
0945     .fill_modes = drm_helper_probe_single_connector_modes,
0946     .early_unregister = amdgpu_connector_unregister,
0947     .destroy = amdgpu_connector_destroy,
0948     .set_property = amdgpu_connector_set_property,
0949 };
0950
0951 static bool
0952 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
0953 {
0954     struct drm_device *dev = connector->dev;
0955     struct amdgpu_device *adev = drm_to_adev(dev);
0956     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0957     enum drm_connector_status status;
0958
0959     if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
0960         if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
0961             status = connector_status_connected;
0962         else
0963             status = connector_status_disconnected;
0964         if (connector->status == status)
0965             return true;
0966     }
0967
0968     return false;
0969 }
0970
0971 /*
0972  * DVI is complicated
0973  * Do a DDC probe, if DDC probe passes, get the full EDID so
0974  * we can do analog/digital monitor detection at this point.
0975  * If the monitor is an analog monitor or we got no DDC,
0976  * we need to find the DAC encoder object for this connector.
0977  * If we got no DDC, we do load detection on the DAC encoder object.
0978  * If we got analog DDC or load detection passes on the DAC encoder
0979  * we have to check if this analog encoder is shared with anyone else (TV)
0980  * if its shared we have to set the other connector to disconnected.
0981  */
0982 static enum drm_connector_status
0983 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
0984 {
0985     struct drm_device *dev = connector->dev;
0986     struct amdgpu_device *adev = drm_to_adev(dev);
0987     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
0988     const struct drm_encoder_helper_funcs *encoder_funcs;
0989     int r;
0990     enum drm_connector_status ret = connector_status_disconnected;
0991     bool dret = false, broken_edid = false;
0992
0993     if (!drm_kms_helper_is_poll_worker()) {
0994         r = pm_runtime_get_sync(connector->dev->dev);
0995         if (r < 0) {
0996             pm_runtime_put_autosuspend(connector->dev->dev);
0997             return connector_status_disconnected;
0998         }
0999     }
1000
1001     if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1002         ret = connector->status;
1003         goto exit;
1004     }
1005
1006     if (amdgpu_connector->ddc_bus)
1007         dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1008     if (dret) {
1009         amdgpu_connector->detected_by_load = false;
1010         amdgpu_connector_free_edid(connector);
1011         amdgpu_connector_get_edid(connector);
1012
1013         if (!amdgpu_connector->edid) {
1014             DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1015                     connector->name);
1016             ret = connector_status_connected;
1017             broken_edid = true; /* defer use_digital to later */
1018         } else {
1019             amdgpu_connector->use_digital =
1020                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1021
1022             /* some oems have boards with separate digital and analog connectors
1023              * with a shared ddc line (often vga + hdmi)
1024              */
1025             if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1026                 amdgpu_connector_free_edid(connector);
1027                 ret = connector_status_disconnected;
1028             } else {
1029                 ret = connector_status_connected;
1030             }
1031
1032             /* This gets complicated.  We have boards with VGA + HDMI with a
1033              * shared DDC line and we have boards with DVI-D + HDMI with a shared
1034              * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1035              * you don't really know what's connected to which port as both are digital.
1036              */
1037             if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1038                 struct drm_connector *list_connector;
1039                 struct drm_connector_list_iter iter;
1040                 struct amdgpu_connector *list_amdgpu_connector;
1041
1042                 drm_connector_list_iter_begin(dev, &iter);
1043                 drm_for_each_connector_iter(list_connector,
1044                                 &iter) {
1045                     if (connector == list_connector)
1046                         continue;
1047                     list_amdgpu_connector = to_amdgpu_connector(list_connector);
1048                     if (list_amdgpu_connector->shared_ddc &&
1049                         (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1050                          amdgpu_connector->ddc_bus->rec.i2c_id)) {
1051                         /* cases where both connectors are digital */
1052                         if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1053                             /* hpd is our only option in this case */
1054                             if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1055                                 amdgpu_connector_free_edid(connector);
1056                                 ret = connector_status_disconnected;
1057                             }
1058                         }
1059                     }
1060                 }
1061                 drm_connector_list_iter_end(&iter);
1062             }
1063         }
1064     }
1065
1066     if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1067         goto out;
1068
1069     /* DVI-D and HDMI-A are digital only */
1070     if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1071         (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1072         goto out;
1073
1074     /* if we aren't forcing don't do destructive polling */
1075     if (!force) {
1076         /* only return the previous status if we last
1077          * detected a monitor via load.
1078          */
1079         if (amdgpu_connector->detected_by_load)
1080             ret = connector->status;
1081         goto out;
1082     }
1083
1084     /* find analog encoder */
1085     if (amdgpu_connector->dac_load_detect) {
1086         struct drm_encoder *encoder;
1087
1088         drm_connector_for_each_possible_encoder(connector, encoder) {
1089             if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1090                 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1091                 continue;
1092
1093             encoder_funcs = encoder->helper_private;
1094             if (encoder_funcs->detect) {
1095                 if (!broken_edid) {
1096                     if (ret != connector_status_connected) {
1097                         /* deal with analog monitors without DDC */
1098                         ret = encoder_funcs->detect(encoder, connector);
1099                         if (ret == connector_status_connected) {
1100                             amdgpu_connector->use_digital = false;
1101                         }
1102                         if (ret != connector_status_disconnected)
1103                             amdgpu_connector->detected_by_load = true;
1104                     }
1105                 } else {
1106                     enum drm_connector_status lret;
1107                     /* assume digital unless load detected otherwise */
1108                     amdgpu_connector->use_digital = true;
1109                     lret = encoder_funcs->detect(encoder, connector);
1110                     DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1111                     if (lret == connector_status_connected)
1112                         amdgpu_connector->use_digital = false;
1113                 }
1114                 break;
1115             }
1116         }
1117     }
1118
1119 out:
1120     /* updated in get modes as well since we need to know if it's analog or digital */
1121     amdgpu_connector_update_scratch_regs(connector, ret);
1122
1123 exit:
1124     if (!drm_kms_helper_is_poll_worker()) {
1125         pm_runtime_mark_last_busy(connector->dev->dev);
1126         pm_runtime_put_autosuspend(connector->dev->dev);
1127     }
1128
1129     return ret;
1130 }
1131
1132 /* okay need to be smart in here about which encoder to pick */
1133 static struct drm_encoder *
1134 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1135 {
1136     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1137     struct drm_encoder *encoder;
1138
1139     drm_connector_for_each_possible_encoder(connector, encoder) {
1140         if (amdgpu_connector->use_digital == true) {
1141             if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1142                 return encoder;
1143         } else {
1144             if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1145                 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1146                 return encoder;
1147         }
1148     }
1149
1150     /* see if we have a default encoder  TODO */
1151
1152     /* then check use digitial */
1153     /* pick the first one */
1154     drm_connector_for_each_possible_encoder(connector, encoder)
1155         return encoder;
1156
1157     return NULL;
1158 }
1159
1160 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1161 {
1162     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1163     if (connector->force == DRM_FORCE_ON)
1164         amdgpu_connector->use_digital = false;
1165     if (connector->force == DRM_FORCE_ON_DIGITAL)
1166         amdgpu_connector->use_digital = true;
1167 }
1168
1169 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1170                         struct drm_display_mode *mode)
1171 {
1172     struct drm_device *dev = connector->dev;
1173     struct amdgpu_device *adev = drm_to_adev(dev);
1174     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1175
1176     /* XXX check mode bandwidth */
1177
1178     if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1179         if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1180             (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1181             (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1182             return MODE_OK;
1183         } else if (connector->display_info.is_hdmi) {
1184             /* HDMI 1.3+ supports max clock of 340 Mhz */
1185             if (mode->clock > 340000)
1186                 return MODE_CLOCK_HIGH;
1187             else
1188                 return MODE_OK;
1189         } else {
1190             return MODE_CLOCK_HIGH;
1191         }
1192     }
1193
1194     /* check against the max pixel clock */
1195     if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1196         return MODE_CLOCK_HIGH;
1197
1198     return MODE_OK;
1199 }
1200
1201 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1202     .get_modes = amdgpu_connector_vga_get_modes,
1203     .mode_valid = amdgpu_connector_dvi_mode_valid,
1204     .best_encoder = amdgpu_connector_dvi_encoder,
1205 };
1206
1207 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1208     .dpms = drm_helper_connector_dpms,
1209     .detect = amdgpu_connector_dvi_detect,
1210     .fill_modes = drm_helper_probe_single_connector_modes,
1211     .set_property = amdgpu_connector_set_property,
1212     .early_unregister = amdgpu_connector_unregister,
1213     .destroy = amdgpu_connector_destroy,
1214     .force = amdgpu_connector_dvi_force,
1215 };
1216
1217 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1218 {
1219     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1220     struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1221     struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1222     int ret;
1223
1224     if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1225         (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1226         struct drm_display_mode *mode;
1227
1228         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1229             if (!amdgpu_dig_connector->edp_on)
1230                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1231                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1232             amdgpu_connector_get_edid(connector);
1233             ret = amdgpu_connector_ddc_get_modes(connector);
1234             if (!amdgpu_dig_connector->edp_on)
1235                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1236                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1237         } else {
1238             /* need to setup ddc on the bridge */
1239             if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1240                 ENCODER_OBJECT_ID_NONE) {
1241                 if (encoder)
1242                     amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1243             }
1244             amdgpu_connector_get_edid(connector);
1245             ret = amdgpu_connector_ddc_get_modes(connector);
1246         }
1247
1248         if (ret > 0) {
1249             if (encoder) {
1250                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1251                 /* add scaled modes */
1252                 amdgpu_connector_add_common_modes(encoder, connector);
1253             }
1254             return ret;
1255         }
1256
1257         if (!encoder)
1258             return 0;
1259
1260         /* we have no EDID modes */
1261         mode = amdgpu_connector_lcd_native_mode(encoder);
1262         if (mode) {
1263             ret = 1;
1264             drm_mode_probed_add(connector, mode);
1265             /* add the width/height from vbios tables if available */
1266             connector->display_info.width_mm = mode->width_mm;
1267             connector->display_info.height_mm = mode->height_mm;
1268             /* add scaled modes */
1269             amdgpu_connector_add_common_modes(encoder, connector);
1270         }
1271     } else {
1272         /* need to setup ddc on the bridge */
1273         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1274             ENCODER_OBJECT_ID_NONE) {
1275             if (encoder)
1276                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1277         }
1278         amdgpu_connector_get_edid(connector);
1279         ret = amdgpu_connector_ddc_get_modes(connector);
1280
1281         amdgpu_get_native_mode(connector);
1282     }
1283
1284     return ret;
1285 }
1286
1287 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1288 {
1289     struct drm_encoder *encoder;
1290     struct amdgpu_encoder *amdgpu_encoder;
1291
1292     drm_connector_for_each_possible_encoder(connector, encoder) {
1293         amdgpu_encoder = to_amdgpu_encoder(encoder);
1294
1295         switch (amdgpu_encoder->encoder_id) {
1296         case ENCODER_OBJECT_ID_TRAVIS:
1297         case ENCODER_OBJECT_ID_NUTMEG:
1298             return amdgpu_encoder->encoder_id;
1299         default:
1300             break;
1301         }
1302     }
1303
1304     return ENCODER_OBJECT_ID_NONE;
1305 }
1306
1307 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1308 {
1309     struct drm_encoder *encoder;
1310     struct amdgpu_encoder *amdgpu_encoder;
1311     bool found = false;
1312
1313     drm_connector_for_each_possible_encoder(connector, encoder) {
1314         amdgpu_encoder = to_amdgpu_encoder(encoder);
1315         if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1316             found = true;
1317     }
1318
1319     return found;
1320 }
1321
1322 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1323 {
1324     struct drm_device *dev = connector->dev;
1325     struct amdgpu_device *adev = drm_to_adev(dev);
1326
1327     if ((adev->clock.default_dispclk >= 53900) &&
1328         amdgpu_connector_encoder_is_hbr2(connector)) {
1329         return true;
1330     }
1331
1332     return false;
1333 }
1334
1335 static enum drm_connector_status
1336 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1337 {
1338     struct drm_device *dev = connector->dev;
1339     struct amdgpu_device *adev = drm_to_adev(dev);
1340     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1341     enum drm_connector_status ret = connector_status_disconnected;
1342     struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1343     struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1344     int r;
1345
1346     if (!drm_kms_helper_is_poll_worker()) {
1347         r = pm_runtime_get_sync(connector->dev->dev);
1348         if (r < 0) {
1349             pm_runtime_put_autosuspend(connector->dev->dev);
1350             return connector_status_disconnected;
1351         }
1352     }
1353
1354     if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1355         ret = connector->status;
1356         goto out;
1357     }
1358
1359     amdgpu_connector_free_edid(connector);
1360
1361     if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1362         (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1363         if (encoder) {
1364             struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365             struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1366
1367             /* check if panel is valid */
1368             if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1369                 ret = connector_status_connected;
1370         }
1371         /* eDP is always DP */
1372         amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1373         if (!amdgpu_dig_connector->edp_on)
1374             amdgpu_atombios_encoder_set_edp_panel_power(connector,
1375                                  ATOM_TRANSMITTER_ACTION_POWER_ON);
1376         if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1377             ret = connector_status_connected;
1378         if (!amdgpu_dig_connector->edp_on)
1379             amdgpu_atombios_encoder_set_edp_panel_power(connector,
1380                                  ATOM_TRANSMITTER_ACTION_POWER_OFF);
1381     } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1382            ENCODER_OBJECT_ID_NONE) {
1383         /* DP bridges are always DP */
1384         amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1385         /* get the DPCD from the bridge */
1386         amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1387
1388         if (encoder) {
1389             /* setup ddc on the bridge */
1390             amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1391             /* bridge chips are always aux */
1392             /* try DDC */
1393             if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1394                 ret = connector_status_connected;
1395             else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1396                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1397                 ret = encoder_funcs->detect(encoder, connector);
1398             }
1399         }
1400     } else {
1401         amdgpu_dig_connector->dp_sink_type =
1402             amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1403         if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1404             ret = connector_status_connected;
1405             if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1406                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1407         } else {
1408             if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1409                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1410                     ret = connector_status_connected;
1411             } else {
1412                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1413                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1414                                  false))
1415                     ret = connector_status_connected;
1416             }
1417         }
1418     }
1419
1420     amdgpu_connector_update_scratch_regs(connector, ret);
1421 out:
1422     if (!drm_kms_helper_is_poll_worker()) {
1423         pm_runtime_mark_last_busy(connector->dev->dev);
1424         pm_runtime_put_autosuspend(connector->dev->dev);
1425     }
1426
1427     if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1428         connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1429         drm_dp_set_subconnector_property(&amdgpu_connector->base,
1430                          ret,
1431                          amdgpu_dig_connector->dpcd,
1432                          amdgpu_dig_connector->downstream_ports);
1433     return ret;
1434 }
1435
1436 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1437                        struct drm_display_mode *mode)
1438 {
1439     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1440     struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1441
1442     /* XXX check mode bandwidth */
1443
1444     if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1445         (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1446         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1447
1448         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1449             return MODE_PANEL;
1450
1451         if (encoder) {
1452             struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1453             struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1454
1455             /* AVIVO hardware supports downscaling modes larger than the panel
1456              * to the panel size, but I'm not sure this is desirable.
1457              */
1458             if ((mode->hdisplay > native_mode->hdisplay) ||
1459                 (mode->vdisplay > native_mode->vdisplay))
1460                 return MODE_PANEL;
1461
1462             /* if scaling is disabled, block non-native modes */
1463             if (amdgpu_encoder->rmx_type == RMX_OFF) {
1464                 if ((mode->hdisplay != native_mode->hdisplay) ||
1465                     (mode->vdisplay != native_mode->vdisplay))
1466                     return MODE_PANEL;
1467             }
1468         }
1469         return MODE_OK;
1470     } else {
1471         if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1472             (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1473             return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1474         } else {
1475             if (connector->display_info.is_hdmi) {
1476                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1477                 if (mode->clock > 340000)
1478                     return MODE_CLOCK_HIGH;
1479             } else {
1480                 if (mode->clock > 165000)
1481                     return MODE_CLOCK_HIGH;
1482             }
1483         }
1484     }
1485
1486     return MODE_OK;
1487 }
1488
1489 static int
1490 amdgpu_connector_late_register(struct drm_connector *connector)
1491 {
1492     struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1493     int r = 0;
1494
1495     if (amdgpu_connector->ddc_bus->has_aux) {
1496         amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1497         r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1498     }
1499
1500     return r;
1501 }
1502
1503 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1504     .get_modes = amdgpu_connector_dp_get_modes,
1505     .mode_valid = amdgpu_connector_dp_mode_valid,
1506     .best_encoder = amdgpu_connector_dvi_encoder,
1507 };
1508
1509 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1510     .dpms = drm_helper_connector_dpms,
1511     .detect = amdgpu_connector_dp_detect,
1512     .fill_modes = drm_helper_probe_single_connector_modes,
1513     .set_property = amdgpu_connector_set_property,
1514     .early_unregister = amdgpu_connector_unregister,
1515     .destroy = amdgpu_connector_destroy,
1516     .force = amdgpu_connector_dvi_force,
1517     .late_register = amdgpu_connector_late_register,
1518 };
1519
1520 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1521     .dpms = drm_helper_connector_dpms,
1522     .detect = amdgpu_connector_dp_detect,
1523     .fill_modes = drm_helper_probe_single_connector_modes,
1524     .set_property = amdgpu_connector_set_lcd_property,
1525     .early_unregister = amdgpu_connector_unregister,
1526     .destroy = amdgpu_connector_destroy,
1527     .force = amdgpu_connector_dvi_force,
1528     .late_register = amdgpu_connector_late_register,
1529 };
1530
1531 void
1532 amdgpu_connector_add(struct amdgpu_device *adev,
1533               uint32_t connector_id,
1534               uint32_t supported_device,
1535               int connector_type,
1536               struct amdgpu_i2c_bus_rec *i2c_bus,
1537               uint16_t connector_object_id,
1538               struct amdgpu_hpd *hpd,
1539               struct amdgpu_router *router)
1540 {
1541     struct drm_device *dev = adev_to_drm(adev);
1542     struct drm_connector *connector;
1543     struct drm_connector_list_iter iter;
1544     struct amdgpu_connector *amdgpu_connector;
1545     struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1546     struct drm_encoder *encoder;
1547     struct amdgpu_encoder *amdgpu_encoder;
1548     struct i2c_adapter *ddc = NULL;
1549     uint32_t subpixel_order = SubPixelNone;
1550     bool shared_ddc = false;
1551     bool is_dp_bridge = false;
1552     bool has_aux = false;
1553
1554     if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1555         return;
1556
1557     /* see if we already added it */
1558     drm_connector_list_iter_begin(dev, &iter);
1559     drm_for_each_connector_iter(connector, &iter) {
1560         amdgpu_connector = to_amdgpu_connector(connector);
1561         if (amdgpu_connector->connector_id == connector_id) {
1562             amdgpu_connector->devices |= supported_device;
1563             drm_connector_list_iter_end(&iter);
1564             return;
1565         }
1566         if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1567             if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1568                 amdgpu_connector->shared_ddc = true;
1569                 shared_ddc = true;
1570             }
1571             if (amdgpu_connector->router_bus && router->ddc_valid &&
1572                 (amdgpu_connector->router.router_id == router->router_id)) {
1573                 amdgpu_connector->shared_ddc = false;
1574                 shared_ddc = false;
1575             }
1576         }
1577     }
1578     drm_connector_list_iter_end(&iter);
1579
1580     /* check if it's a dp bridge */
1581     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1582         amdgpu_encoder = to_amdgpu_encoder(encoder);
1583         if (amdgpu_encoder->devices & supported_device) {
1584             switch (amdgpu_encoder->encoder_id) {
1585             case ENCODER_OBJECT_ID_TRAVIS:
1586             case ENCODER_OBJECT_ID_NUTMEG:
1587                 is_dp_bridge = true;
1588                 break;
1589             default:
1590                 break;
1591             }
1592         }
1593     }
1594
1595     amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1596     if (!amdgpu_connector)
1597         return;
1598
1599     connector = &amdgpu_connector->base;
1600
1601     amdgpu_connector->connector_id = connector_id;
1602     amdgpu_connector->devices = supported_device;
1603     amdgpu_connector->shared_ddc = shared_ddc;
1604     amdgpu_connector->connector_object_id = connector_object_id;
1605     amdgpu_connector->hpd = *hpd;
1606
1607     amdgpu_connector->router = *router;
1608     if (router->ddc_valid || router->cd_valid) {
1609         amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1610         if (!amdgpu_connector->router_bus)
1611             DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1612     }
1613
1614     if (is_dp_bridge) {
1615         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1616         if (!amdgpu_dig_connector)
1617             goto failed;
1618         amdgpu_connector->con_priv = amdgpu_dig_connector;
1619         if (i2c_bus->valid) {
1620             amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1621             if (amdgpu_connector->ddc_bus) {
1622                 has_aux = true;
1623                 ddc = &amdgpu_connector->ddc_bus->adapter;
1624             } else {
1625                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1626             }
1627         }
1628         switch (connector_type) {
1629         case DRM_MODE_CONNECTOR_VGA:
1630         case DRM_MODE_CONNECTOR_DVIA:
1631         default:
1632             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1633                             &amdgpu_connector_dp_funcs,
1634                             connector_type,
1635                             ddc);
1636             drm_connector_helper_add(&amdgpu_connector->base,
1637                          &amdgpu_connector_dp_helper_funcs);
1638             connector->interlace_allowed = true;
1639             connector->doublescan_allowed = true;
1640             amdgpu_connector->dac_load_detect = true;
1641             drm_object_attach_property(&amdgpu_connector->base.base,
1642                               adev->mode_info.load_detect_property,
1643                               1);
1644             drm_object_attach_property(&amdgpu_connector->base.base,
1645                            dev->mode_config.scaling_mode_property,
1646                            DRM_MODE_SCALE_NONE);
1647             break;
1648         case DRM_MODE_CONNECTOR_DVII:
1649         case DRM_MODE_CONNECTOR_DVID:
1650         case DRM_MODE_CONNECTOR_HDMIA:
1651         case DRM_MODE_CONNECTOR_HDMIB:
1652         case DRM_MODE_CONNECTOR_DisplayPort:
1653             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1654                             &amdgpu_connector_dp_funcs,
1655                             connector_type,
1656                             ddc);
1657             drm_connector_helper_add(&amdgpu_connector->base,
1658                          &amdgpu_connector_dp_helper_funcs);
1659             drm_object_attach_property(&amdgpu_connector->base.base,
1660                               adev->mode_info.underscan_property,
1661                               UNDERSCAN_OFF);
1662             drm_object_attach_property(&amdgpu_connector->base.base,
1663                               adev->mode_info.underscan_hborder_property,
1664                               0);
1665             drm_object_attach_property(&amdgpu_connector->base.base,
1666                               adev->mode_info.underscan_vborder_property,
1667                               0);
1668
1669             drm_object_attach_property(&amdgpu_connector->base.base,
1670                            dev->mode_config.scaling_mode_property,
1671                            DRM_MODE_SCALE_NONE);
1672
1673             drm_object_attach_property(&amdgpu_connector->base.base,
1674                            adev->mode_info.dither_property,
1675                            AMDGPU_FMT_DITHER_DISABLE);
1676
1677             if (amdgpu_audio != 0)
1678                 drm_object_attach_property(&amdgpu_connector->base.base,
1679                                adev->mode_info.audio_property,
1680                                AMDGPU_AUDIO_AUTO);
1681
1682             subpixel_order = SubPixelHorizontalRGB;
1683             connector->interlace_allowed = true;
1684             if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1685                 connector->doublescan_allowed = true;
1686             else
1687                 connector->doublescan_allowed = false;
1688             if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1689                 amdgpu_connector->dac_load_detect = true;
1690                 drm_object_attach_property(&amdgpu_connector->base.base,
1691                                   adev->mode_info.load_detect_property,
1692                                   1);
1693             }
1694             break;
1695         case DRM_MODE_CONNECTOR_LVDS:
1696         case DRM_MODE_CONNECTOR_eDP:
1697             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1698                             &amdgpu_connector_edp_funcs,
1699                             connector_type,
1700                             ddc);
1701             drm_connector_helper_add(&amdgpu_connector->base,
1702                          &amdgpu_connector_dp_helper_funcs);
1703             drm_object_attach_property(&amdgpu_connector->base.base,
1704                               dev->mode_config.scaling_mode_property,
1705                               DRM_MODE_SCALE_FULLSCREEN);
1706             subpixel_order = SubPixelHorizontalRGB;
1707             connector->interlace_allowed = false;
1708             connector->doublescan_allowed = false;
1709             break;
1710         }
1711     } else {
1712         switch (connector_type) {
1713         case DRM_MODE_CONNECTOR_VGA:
1714             if (i2c_bus->valid) {
1715                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1716                 if (!amdgpu_connector->ddc_bus)
1717                     DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1718                 else
1719                     ddc = &amdgpu_connector->ddc_bus->adapter;
1720             }
1721             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1722                             &amdgpu_connector_vga_funcs,
1723                             connector_type,
1724                             ddc);
1725             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1726             amdgpu_connector->dac_load_detect = true;
1727             drm_object_attach_property(&amdgpu_connector->base.base,
1728                               adev->mode_info.load_detect_property,
1729                               1);
1730             drm_object_attach_property(&amdgpu_connector->base.base,
1731                            dev->mode_config.scaling_mode_property,
1732                            DRM_MODE_SCALE_NONE);
1733             /* no HPD on analog connectors */
1734             amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1735             connector->interlace_allowed = true;
1736             connector->doublescan_allowed = true;
1737             break;
1738         case DRM_MODE_CONNECTOR_DVIA:
1739             if (i2c_bus->valid) {
1740                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1741                 if (!amdgpu_connector->ddc_bus)
1742                     DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1743                 else
1744                     ddc = &amdgpu_connector->ddc_bus->adapter;
1745             }
1746             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1747                             &amdgpu_connector_vga_funcs,
1748                             connector_type,
1749                             ddc);
1750             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1751             amdgpu_connector->dac_load_detect = true;
1752             drm_object_attach_property(&amdgpu_connector->base.base,
1753                               adev->mode_info.load_detect_property,
1754                               1);
1755             drm_object_attach_property(&amdgpu_connector->base.base,
1756                            dev->mode_config.scaling_mode_property,
1757                            DRM_MODE_SCALE_NONE);
1758             /* no HPD on analog connectors */
1759             amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1760             connector->interlace_allowed = true;
1761             connector->doublescan_allowed = true;
1762             break;
1763         case DRM_MODE_CONNECTOR_DVII:
1764         case DRM_MODE_CONNECTOR_DVID:
1765             amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1766             if (!amdgpu_dig_connector)
1767                 goto failed;
1768             amdgpu_connector->con_priv = amdgpu_dig_connector;
1769             if (i2c_bus->valid) {
1770                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1771                 if (!amdgpu_connector->ddc_bus)
1772                     DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1773                 else
1774                     ddc = &amdgpu_connector->ddc_bus->adapter;
1775             }
1776             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1777                             &amdgpu_connector_dvi_funcs,
1778                             connector_type,
1779                             ddc);
1780             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1781             subpixel_order = SubPixelHorizontalRGB;
1782             drm_object_attach_property(&amdgpu_connector->base.base,
1783                               adev->mode_info.coherent_mode_property,
1784                               1);
1785             drm_object_attach_property(&amdgpu_connector->base.base,
1786                            adev->mode_info.underscan_property,
1787                            UNDERSCAN_OFF);
1788             drm_object_attach_property(&amdgpu_connector->base.base,
1789                            adev->mode_info.underscan_hborder_property,
1790                            0);
1791             drm_object_attach_property(&amdgpu_connector->base.base,
1792                            adev->mode_info.underscan_vborder_property,
1793                            0);
1794             drm_object_attach_property(&amdgpu_connector->base.base,
1795                            dev->mode_config.scaling_mode_property,
1796                            DRM_MODE_SCALE_NONE);
1797
1798             if (amdgpu_audio != 0) {
1799                 drm_object_attach_property(&amdgpu_connector->base.base,
1800                                adev->mode_info.audio_property,
1801                                AMDGPU_AUDIO_AUTO);
1802             }
1803             drm_object_attach_property(&amdgpu_connector->base.base,
1804                            adev->mode_info.dither_property,
1805                            AMDGPU_FMT_DITHER_DISABLE);
1806             if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1807                 amdgpu_connector->dac_load_detect = true;
1808                 drm_object_attach_property(&amdgpu_connector->base.base,
1809                                adev->mode_info.load_detect_property,
1810                                1);
1811             }
1812             connector->interlace_allowed = true;
1813             if (connector_type == DRM_MODE_CONNECTOR_DVII)
1814                 connector->doublescan_allowed = true;
1815             else
1816                 connector->doublescan_allowed = false;
1817             break;
1818         case DRM_MODE_CONNECTOR_HDMIA:
1819         case DRM_MODE_CONNECTOR_HDMIB:
1820             amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1821             if (!amdgpu_dig_connector)
1822                 goto failed;
1823             amdgpu_connector->con_priv = amdgpu_dig_connector;
1824             if (i2c_bus->valid) {
1825                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1826                 if (!amdgpu_connector->ddc_bus)
1827                     DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1828                 else
1829                     ddc = &amdgpu_connector->ddc_bus->adapter;
1830             }
1831             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1832                             &amdgpu_connector_dvi_funcs,
1833                             connector_type,
1834                             ddc);
1835             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1836             drm_object_attach_property(&amdgpu_connector->base.base,
1837                               adev->mode_info.coherent_mode_property,
1838                               1);
1839             drm_object_attach_property(&amdgpu_connector->base.base,
1840                            adev->mode_info.underscan_property,
1841                            UNDERSCAN_OFF);
1842             drm_object_attach_property(&amdgpu_connector->base.base,
1843                            adev->mode_info.underscan_hborder_property,
1844                            0);
1845             drm_object_attach_property(&amdgpu_connector->base.base,
1846                            adev->mode_info.underscan_vborder_property,
1847                            0);
1848             drm_object_attach_property(&amdgpu_connector->base.base,
1849                            dev->mode_config.scaling_mode_property,
1850                            DRM_MODE_SCALE_NONE);
1851             if (amdgpu_audio != 0) {
1852                 drm_object_attach_property(&amdgpu_connector->base.base,
1853                                adev->mode_info.audio_property,
1854                                AMDGPU_AUDIO_AUTO);
1855             }
1856             drm_object_attach_property(&amdgpu_connector->base.base,
1857                            adev->mode_info.dither_property,
1858                            AMDGPU_FMT_DITHER_DISABLE);
1859             subpixel_order = SubPixelHorizontalRGB;
1860             connector->interlace_allowed = true;
1861             if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1862                 connector->doublescan_allowed = true;
1863             else
1864                 connector->doublescan_allowed = false;
1865             break;
1866         case DRM_MODE_CONNECTOR_DisplayPort:
1867             amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1868             if (!amdgpu_dig_connector)
1869                 goto failed;
1870             amdgpu_connector->con_priv = amdgpu_dig_connector;
1871             if (i2c_bus->valid) {
1872                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1873                 if (amdgpu_connector->ddc_bus) {
1874                     has_aux = true;
1875                     ddc = &amdgpu_connector->ddc_bus->adapter;
1876                 } else {
1877                     DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1878                 }
1879             }
1880             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1881                             &amdgpu_connector_dp_funcs,
1882                             connector_type,
1883                             ddc);
1884             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1885             subpixel_order = SubPixelHorizontalRGB;
1886             drm_object_attach_property(&amdgpu_connector->base.base,
1887                               adev->mode_info.coherent_mode_property,
1888                               1);
1889             drm_object_attach_property(&amdgpu_connector->base.base,
1890                            adev->mode_info.underscan_property,
1891                            UNDERSCAN_OFF);
1892             drm_object_attach_property(&amdgpu_connector->base.base,
1893                            adev->mode_info.underscan_hborder_property,
1894                            0);
1895             drm_object_attach_property(&amdgpu_connector->base.base,
1896                            adev->mode_info.underscan_vborder_property,
1897                            0);
1898             drm_object_attach_property(&amdgpu_connector->base.base,
1899                            dev->mode_config.scaling_mode_property,
1900                            DRM_MODE_SCALE_NONE);
1901             if (amdgpu_audio != 0) {
1902                 drm_object_attach_property(&amdgpu_connector->base.base,
1903                                adev->mode_info.audio_property,
1904                                AMDGPU_AUDIO_AUTO);
1905             }
1906             drm_object_attach_property(&amdgpu_connector->base.base,
1907                            adev->mode_info.dither_property,
1908                            AMDGPU_FMT_DITHER_DISABLE);
1909             connector->interlace_allowed = true;
1910             /* in theory with a DP to VGA converter... */
1911             connector->doublescan_allowed = false;
1912             break;
1913         case DRM_MODE_CONNECTOR_eDP:
1914             amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1915             if (!amdgpu_dig_connector)
1916                 goto failed;
1917             amdgpu_connector->con_priv = amdgpu_dig_connector;
1918             if (i2c_bus->valid) {
1919                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1920                 if (amdgpu_connector->ddc_bus) {
1921                     has_aux = true;
1922                     ddc = &amdgpu_connector->ddc_bus->adapter;
1923                 } else {
1924                     DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1925                 }
1926             }
1927             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1928                             &amdgpu_connector_edp_funcs,
1929                             connector_type,
1930                             ddc);
1931             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1932             drm_object_attach_property(&amdgpu_connector->base.base,
1933                               dev->mode_config.scaling_mode_property,
1934                               DRM_MODE_SCALE_FULLSCREEN);
1935             subpixel_order = SubPixelHorizontalRGB;
1936             connector->interlace_allowed = false;
1937             connector->doublescan_allowed = false;
1938             break;
1939         case DRM_MODE_CONNECTOR_LVDS:
1940             amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1941             if (!amdgpu_dig_connector)
1942                 goto failed;
1943             amdgpu_connector->con_priv = amdgpu_dig_connector;
1944             if (i2c_bus->valid) {
1945                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1946                 if (!amdgpu_connector->ddc_bus)
1947                     DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1948                 else
1949                     ddc = &amdgpu_connector->ddc_bus->adapter;
1950             }
1951             drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1952                             &amdgpu_connector_lvds_funcs,
1953                             connector_type,
1954                             ddc);
1955             drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1956             drm_object_attach_property(&amdgpu_connector->base.base,
1957                               dev->mode_config.scaling_mode_property,
1958                               DRM_MODE_SCALE_FULLSCREEN);
1959             subpixel_order = SubPixelHorizontalRGB;
1960             connector->interlace_allowed = false;
1961             connector->doublescan_allowed = false;
1962             break;
1963         }
1964     }
1965
1966     if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1967         if (i2c_bus->valid) {
1968             connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1969                                 DRM_CONNECTOR_POLL_DISCONNECT;
1970         }
1971     } else
1972         connector->polled = DRM_CONNECTOR_POLL_HPD;
1973
1974     connector->display_info.subpixel_order = subpixel_order;
1975
1976     if (has_aux)
1977         amdgpu_atombios_dp_aux_init(amdgpu_connector);
1978
1979     if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1980         connector_type == DRM_MODE_CONNECTOR_eDP) {
1981         drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
1982     }
1983
1984     return;
1985
1986 failed:
1987     drm_connector_cleanup(connector);
1988     kfree(connector);
1989 }