Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <drm/amdgpu_drm.h>
0025 #include "amdgpu.h"
0026 #include "atomfirmware.h"
0027 #include "amdgpu_atomfirmware.h"
0028 #include "atom.h"
0029 #include "atombios.h"
0030 #include "soc15_hw_ip.h"
0031 
0032 union firmware_info {
0033     struct atom_firmware_info_v3_1 v31;
0034     struct atom_firmware_info_v3_2 v32;
0035     struct atom_firmware_info_v3_3 v33;
0036     struct atom_firmware_info_v3_4 v34;
0037 };
0038 
0039 /*
0040  * Helper function to query firmware capability
0041  *
0042  * @adev: amdgpu_device pointer
0043  *
0044  * Return firmware_capability in firmwareinfo table on success or 0 if not
0045  */
0046 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
0047 {
0048     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0049     int index;
0050     u16 data_offset, size;
0051     union firmware_info *firmware_info;
0052     u8 frev, crev;
0053     u32 fw_cap = 0;
0054 
0055     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0056             firmwareinfo);
0057 
0058     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
0059                 index, &size, &frev, &crev, &data_offset)) {
0060         /* support firmware_info 3.1 + */
0061         if ((frev == 3 && crev >=1) || (frev > 3)) {
0062             firmware_info = (union firmware_info *)
0063                 (mode_info->atom_context->bios + data_offset);
0064             fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
0065         }
0066     }
0067 
0068     return fw_cap;
0069 }
0070 
0071 /*
0072  * Helper function to query gpu virtualizaiton capability
0073  *
0074  * @adev: amdgpu_device pointer
0075  *
0076  * Return true if gpu virtualization is supported or false if not
0077  */
0078 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
0079 {
0080     u32 fw_cap;
0081 
0082     fw_cap = adev->mode_info.firmware_flags;
0083 
0084     return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
0085 }
0086 
0087 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
0088 {
0089     int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0090                         firmwareinfo);
0091     uint16_t data_offset;
0092 
0093     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
0094                       NULL, NULL, &data_offset)) {
0095         struct atom_firmware_info_v3_1 *firmware_info =
0096             (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
0097                                data_offset);
0098 
0099         adev->bios_scratch_reg_offset =
0100             le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
0101     }
0102 }
0103 
0104 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
0105 {
0106     struct atom_context *ctx = adev->mode_info.atom_context;
0107     int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0108                         vram_usagebyfirmware);
0109     struct vram_usagebyfirmware_v2_1 *firmware_usage;
0110     uint32_t start_addr, size;
0111     uint16_t data_offset;
0112     int usage_bytes = 0;
0113 
0114     if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
0115         firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
0116         DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
0117               le32_to_cpu(firmware_usage->start_address_in_kb),
0118               le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
0119               le16_to_cpu(firmware_usage->used_by_driver_in_kb));
0120 
0121         start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
0122         size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
0123 
0124         if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
0125             (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
0126             ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
0127             /* Firmware request VRAM reservation for SR-IOV */
0128             adev->mman.fw_vram_usage_start_offset = (start_addr &
0129                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
0130             adev->mman.fw_vram_usage_size = size << 10;
0131             /* Use the default scratch size */
0132             usage_bytes = 0;
0133         } else {
0134             usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
0135         }
0136     }
0137     ctx->scratch_size_bytes = 0;
0138     if (usage_bytes == 0)
0139         usage_bytes = 20 * 1024;
0140     /* allocate some scratch memory */
0141     ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
0142     if (!ctx->scratch)
0143         return -ENOMEM;
0144     ctx->scratch_size_bytes = usage_bytes;
0145     return 0;
0146 }
0147 
0148 union igp_info {
0149     struct atom_integrated_system_info_v1_11 v11;
0150     struct atom_integrated_system_info_v1_12 v12;
0151     struct atom_integrated_system_info_v2_1 v21;
0152 };
0153 
0154 union umc_info {
0155     struct atom_umc_info_v3_1 v31;
0156     struct atom_umc_info_v3_2 v32;
0157     struct atom_umc_info_v3_3 v33;
0158 };
0159 
0160 union vram_info {
0161     struct atom_vram_info_header_v2_3 v23;
0162     struct atom_vram_info_header_v2_4 v24;
0163     struct atom_vram_info_header_v2_5 v25;
0164     struct atom_vram_info_header_v2_6 v26;
0165     struct atom_vram_info_header_v3_0 v30;
0166 };
0167 
0168 union vram_module {
0169     struct atom_vram_module_v9 v9;
0170     struct atom_vram_module_v10 v10;
0171     struct atom_vram_module_v11 v11;
0172     struct atom_vram_module_v3_0 v30;
0173 };
0174 
0175 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
0176                           int atom_mem_type)
0177 {
0178     int vram_type;
0179 
0180     if (adev->flags & AMD_IS_APU) {
0181         switch (atom_mem_type) {
0182         case Ddr2MemType:
0183         case LpDdr2MemType:
0184             vram_type = AMDGPU_VRAM_TYPE_DDR2;
0185             break;
0186         case Ddr3MemType:
0187         case LpDdr3MemType:
0188             vram_type = AMDGPU_VRAM_TYPE_DDR3;
0189             break;
0190         case Ddr4MemType:
0191             vram_type = AMDGPU_VRAM_TYPE_DDR4;
0192             break;
0193         case LpDdr4MemType:
0194             vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
0195             break;
0196         case Ddr5MemType:
0197             vram_type = AMDGPU_VRAM_TYPE_DDR5;
0198             break;
0199         case LpDdr5MemType:
0200             vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
0201             break;
0202         default:
0203             vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
0204             break;
0205         }
0206     } else {
0207         switch (atom_mem_type) {
0208         case ATOM_DGPU_VRAM_TYPE_GDDR5:
0209             vram_type = AMDGPU_VRAM_TYPE_GDDR5;
0210             break;
0211         case ATOM_DGPU_VRAM_TYPE_HBM2:
0212         case ATOM_DGPU_VRAM_TYPE_HBM2E:
0213             vram_type = AMDGPU_VRAM_TYPE_HBM;
0214             break;
0215         case ATOM_DGPU_VRAM_TYPE_GDDR6:
0216             vram_type = AMDGPU_VRAM_TYPE_GDDR6;
0217             break;
0218         default:
0219             vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
0220             break;
0221         }
0222     }
0223 
0224     return vram_type;
0225 }
0226 
0227 
0228 int
0229 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
0230                   int *vram_width, int *vram_type,
0231                   int *vram_vendor)
0232 {
0233     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0234     int index, i = 0;
0235     u16 data_offset, size;
0236     union igp_info *igp_info;
0237     union vram_info *vram_info;
0238     union vram_module *vram_module;
0239     u8 frev, crev;
0240     u8 mem_type;
0241     u8 mem_vendor;
0242     u32 mem_channel_number;
0243     u32 mem_channel_width;
0244     u32 module_id;
0245 
0246     if (adev->flags & AMD_IS_APU)
0247         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0248                             integratedsysteminfo);
0249     else
0250         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0251                             vram_info);
0252 
0253     if (amdgpu_atom_parse_data_header(mode_info->atom_context,
0254                       index, &size,
0255                       &frev, &crev, &data_offset)) {
0256         if (adev->flags & AMD_IS_APU) {
0257             igp_info = (union igp_info *)
0258                 (mode_info->atom_context->bios + data_offset);
0259             switch (frev) {
0260             case 1:
0261                 switch (crev) {
0262                 case 11:
0263                 case 12:
0264                     mem_channel_number = igp_info->v11.umachannelnumber;
0265                     if (!mem_channel_number)
0266                         mem_channel_number = 1;
0267                     /* channel width is 64 */
0268                     if (vram_width)
0269                         *vram_width = mem_channel_number * 64;
0270                     mem_type = igp_info->v11.memorytype;
0271                     if (vram_type)
0272                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0273                     break;
0274                 default:
0275                     return -EINVAL;
0276                 }
0277                 break;
0278             case 2:
0279                 switch (crev) {
0280                 case 1:
0281                 case 2:
0282                     mem_channel_number = igp_info->v21.umachannelnumber;
0283                     if (!mem_channel_number)
0284                         mem_channel_number = 1;
0285                     /* channel width is 64 */
0286                     if (vram_width)
0287                         *vram_width = mem_channel_number * 64;
0288                     mem_type = igp_info->v21.memorytype;
0289                     if (vram_type)
0290                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0291                     break;
0292                 default:
0293                     return -EINVAL;
0294                 }
0295                 break;
0296             default:
0297                 return -EINVAL;
0298             }
0299         } else {
0300             vram_info = (union vram_info *)
0301                 (mode_info->atom_context->bios + data_offset);
0302             module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
0303             if (frev == 3) {
0304                 switch (crev) {
0305                 /* v30 */
0306                 case 0:
0307                     vram_module = (union vram_module *)vram_info->v30.vram_module;
0308                     mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
0309                     if (vram_vendor)
0310                         *vram_vendor = mem_vendor;
0311                     mem_type = vram_info->v30.memory_type;
0312                     if (vram_type)
0313                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0314                     mem_channel_number = vram_info->v30.channel_num;
0315                     mem_channel_width = vram_info->v30.channel_width;
0316                     if (vram_width)
0317                         *vram_width = mem_channel_number * (1 << mem_channel_width);
0318                     break;
0319                 default:
0320                     return -EINVAL;
0321                 }
0322             } else if (frev == 2) {
0323                 switch (crev) {
0324                 /* v23 */
0325                 case 3:
0326                     if (module_id > vram_info->v23.vram_module_num)
0327                         module_id = 0;
0328                     vram_module = (union vram_module *)vram_info->v23.vram_module;
0329                     while (i < module_id) {
0330                         vram_module = (union vram_module *)
0331                             ((u8 *)vram_module + vram_module->v9.vram_module_size);
0332                         i++;
0333                     }
0334                     mem_type = vram_module->v9.memory_type;
0335                     if (vram_type)
0336                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0337                     mem_channel_number = vram_module->v9.channel_num;
0338                     mem_channel_width = vram_module->v9.channel_width;
0339                     if (vram_width)
0340                         *vram_width = mem_channel_number * (1 << mem_channel_width);
0341                     mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
0342                     if (vram_vendor)
0343                         *vram_vendor = mem_vendor;
0344                     break;
0345                 /* v24 */
0346                 case 4:
0347                     if (module_id > vram_info->v24.vram_module_num)
0348                         module_id = 0;
0349                     vram_module = (union vram_module *)vram_info->v24.vram_module;
0350                     while (i < module_id) {
0351                         vram_module = (union vram_module *)
0352                             ((u8 *)vram_module + vram_module->v10.vram_module_size);
0353                         i++;
0354                     }
0355                     mem_type = vram_module->v10.memory_type;
0356                     if (vram_type)
0357                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0358                     mem_channel_number = vram_module->v10.channel_num;
0359                     mem_channel_width = vram_module->v10.channel_width;
0360                     if (vram_width)
0361                         *vram_width = mem_channel_number * (1 << mem_channel_width);
0362                     mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
0363                     if (vram_vendor)
0364                         *vram_vendor = mem_vendor;
0365                     break;
0366                 /* v25 */
0367                 case 5:
0368                     if (module_id > vram_info->v25.vram_module_num)
0369                         module_id = 0;
0370                     vram_module = (union vram_module *)vram_info->v25.vram_module;
0371                     while (i < module_id) {
0372                         vram_module = (union vram_module *)
0373                             ((u8 *)vram_module + vram_module->v11.vram_module_size);
0374                         i++;
0375                     }
0376                     mem_type = vram_module->v11.memory_type;
0377                     if (vram_type)
0378                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0379                     mem_channel_number = vram_module->v11.channel_num;
0380                     mem_channel_width = vram_module->v11.channel_width;
0381                     if (vram_width)
0382                         *vram_width = mem_channel_number * (1 << mem_channel_width);
0383                     mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
0384                     if (vram_vendor)
0385                         *vram_vendor = mem_vendor;
0386                     break;
0387                 /* v26 */
0388                 case 6:
0389                     if (module_id > vram_info->v26.vram_module_num)
0390                         module_id = 0;
0391                     vram_module = (union vram_module *)vram_info->v26.vram_module;
0392                     while (i < module_id) {
0393                         vram_module = (union vram_module *)
0394                             ((u8 *)vram_module + vram_module->v9.vram_module_size);
0395                         i++;
0396                     }
0397                     mem_type = vram_module->v9.memory_type;
0398                     if (vram_type)
0399                         *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
0400                     mem_channel_number = vram_module->v9.channel_num;
0401                     mem_channel_width = vram_module->v9.channel_width;
0402                     if (vram_width)
0403                         *vram_width = mem_channel_number * (1 << mem_channel_width);
0404                     mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
0405                     if (vram_vendor)
0406                         *vram_vendor = mem_vendor;
0407                     break;
0408                 default:
0409                     return -EINVAL;
0410                 }
0411             } else {
0412                 /* invalid frev */
0413                 return -EINVAL;
0414             }
0415         }
0416 
0417     }
0418 
0419     return 0;
0420 }
0421 
0422 /*
0423  * Return true if vbios enabled ecc by default, if umc info table is available
0424  * or false if ecc is not enabled or umc info table is not available
0425  */
0426 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
0427 {
0428     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0429     int index;
0430     u16 data_offset, size;
0431     union umc_info *umc_info;
0432     u8 frev, crev;
0433     bool ecc_default_enabled = false;
0434     u8 umc_config;
0435     u32 umc_config1;
0436 
0437     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0438             umc_info);
0439 
0440     if (amdgpu_atom_parse_data_header(mode_info->atom_context,
0441                 index, &size, &frev, &crev, &data_offset)) {
0442         if (frev == 3) {
0443             umc_info = (union umc_info *)
0444                 (mode_info->atom_context->bios + data_offset);
0445             switch (crev) {
0446             case 1:
0447                 umc_config = le32_to_cpu(umc_info->v31.umc_config);
0448                 ecc_default_enabled =
0449                     (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
0450                 break;
0451             case 2:
0452                 umc_config = le32_to_cpu(umc_info->v32.umc_config);
0453                 ecc_default_enabled =
0454                     (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
0455                 break;
0456             case 3:
0457                 umc_config = le32_to_cpu(umc_info->v33.umc_config);
0458                 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
0459                 ecc_default_enabled =
0460                     ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
0461                      (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
0462                 break;
0463             default:
0464                 /* unsupported crev */
0465                 return false;
0466             }
0467         }
0468     }
0469 
0470     return ecc_default_enabled;
0471 }
0472 
0473 /*
0474  * Helper function to query sram ecc capablity
0475  *
0476  * @adev: amdgpu_device pointer
0477  *
0478  * Return true if vbios supports sram ecc or false if not
0479  */
0480 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
0481 {
0482     u32 fw_cap;
0483 
0484     fw_cap = adev->mode_info.firmware_flags;
0485 
0486     return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
0487 }
0488 
0489 /*
0490  * Helper function to query dynamic boot config capability
0491  *
0492  * @adev: amdgpu_device pointer
0493  *
0494  * Return true if vbios supports dynamic boot config or false if not
0495  */
0496 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
0497 {
0498     u32 fw_cap;
0499 
0500     fw_cap = adev->mode_info.firmware_flags;
0501 
0502     return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
0503 }
0504 
0505 /**
0506  * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
0507  * @adev: amdgpu_device pointer
0508  * @i2c_address: pointer to u8; if not NULL, will contain
0509  *    the RAS EEPROM address if the function returns true
0510  *
0511  * Return true if VBIOS supports RAS EEPROM address reporting,
0512  * else return false. If true and @i2c_address is not NULL,
0513  * will contain the RAS ROM address.
0514  */
0515 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
0516                       u8 *i2c_address)
0517 {
0518     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0519     int index;
0520     u16 data_offset, size;
0521     union firmware_info *firmware_info;
0522     u8 frev, crev;
0523 
0524     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0525                         firmwareinfo);
0526 
0527     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
0528                       index, &size, &frev, &crev,
0529                       &data_offset)) {
0530         /* support firmware_info 3.4 + */
0531         if ((frev == 3 && crev >=4) || (frev > 3)) {
0532             firmware_info = (union firmware_info *)
0533                 (mode_info->atom_context->bios + data_offset);
0534             /* The ras_rom_i2c_slave_addr should ideally
0535              * be a 19-bit EEPROM address, which would be
0536              * used as is by the driver; see top of
0537              * amdgpu_eeprom.c.
0538              *
0539              * When this is the case, 0 is of course a
0540              * valid RAS EEPROM address, in which case,
0541              * we'll drop the first "if (firm...)" and only
0542              * leave the check for the pointer.
0543              *
0544              * The reason this works right now is because
0545              * ras_rom_i2c_slave_addr contains the EEPROM
0546              * device type qualifier 1010b in the top 4
0547              * bits.
0548              */
0549             if (firmware_info->v34.ras_rom_i2c_slave_addr) {
0550                 if (i2c_address)
0551                     *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
0552                 return true;
0553             }
0554         }
0555     }
0556 
0557     return false;
0558 }
0559 
0560 
0561 union smu_info {
0562     struct atom_smu_info_v3_1 v31;
0563     struct atom_smu_info_v4_0 v40;
0564 };
0565 
0566 union gfx_info {
0567     struct atom_gfx_info_v2_2 v22;
0568     struct atom_gfx_info_v2_4 v24;
0569     struct atom_gfx_info_v2_7 v27;
0570     struct atom_gfx_info_v3_0 v30;
0571 };
0572 
0573 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
0574 {
0575     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0576     struct amdgpu_pll *spll = &adev->clock.spll;
0577     struct amdgpu_pll *mpll = &adev->clock.mpll;
0578     uint8_t frev, crev;
0579     uint16_t data_offset;
0580     int ret = -EINVAL, index;
0581 
0582     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0583                         firmwareinfo);
0584     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0585                    &frev, &crev, &data_offset)) {
0586         union firmware_info *firmware_info =
0587             (union firmware_info *)(mode_info->atom_context->bios +
0588                         data_offset);
0589 
0590         adev->clock.default_sclk =
0591             le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
0592         adev->clock.default_mclk =
0593             le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
0594 
0595         adev->pm.current_sclk = adev->clock.default_sclk;
0596         adev->pm.current_mclk = adev->clock.default_mclk;
0597 
0598         ret = 0;
0599     }
0600 
0601     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0602                         smu_info);
0603     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0604                    &frev, &crev, &data_offset)) {
0605         union smu_info *smu_info =
0606             (union smu_info *)(mode_info->atom_context->bios +
0607                        data_offset);
0608 
0609         /* system clock */
0610         if (frev == 3)
0611             spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
0612         else if (frev == 4)
0613             spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
0614 
0615         spll->reference_div = 0;
0616         spll->min_post_div = 1;
0617         spll->max_post_div = 1;
0618         spll->min_ref_div = 2;
0619         spll->max_ref_div = 0xff;
0620         spll->min_feedback_div = 4;
0621         spll->max_feedback_div = 0xff;
0622         spll->best_vco = 0;
0623 
0624         ret = 0;
0625     }
0626 
0627     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0628                         umc_info);
0629     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0630                    &frev, &crev, &data_offset)) {
0631         union umc_info *umc_info =
0632             (union umc_info *)(mode_info->atom_context->bios +
0633                        data_offset);
0634 
0635         /* memory clock */
0636         mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
0637 
0638         mpll->reference_div = 0;
0639         mpll->min_post_div = 1;
0640         mpll->max_post_div = 1;
0641         mpll->min_ref_div = 2;
0642         mpll->max_ref_div = 0xff;
0643         mpll->min_feedback_div = 4;
0644         mpll->max_feedback_div = 0xff;
0645         mpll->best_vco = 0;
0646 
0647         ret = 0;
0648     }
0649 
0650     /* if asic is Navi+, the rlc reference clock is used for system clock
0651      * from vbios gfx_info table */
0652     if (adev->asic_type >= CHIP_NAVI10) {
0653         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0654                            gfx_info);
0655         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0656                       &frev, &crev, &data_offset)) {
0657             union gfx_info *gfx_info = (union gfx_info *)
0658                 (mode_info->atom_context->bios + data_offset);
0659             if ((frev == 3) ||
0660                 (frev == 2 && crev == 6)) {
0661                 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
0662                 ret = 0;
0663             } else if ((frev == 2) &&
0664                    (crev >= 2) &&
0665                    (crev != 6)) {
0666                 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
0667                 ret = 0;
0668             } else {
0669                 BUG();
0670             }
0671         }
0672     }
0673 
0674     return ret;
0675 }
0676 
0677 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
0678 {
0679     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0680     int index;
0681     uint8_t frev, crev;
0682     uint16_t data_offset;
0683 
0684     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0685                         gfx_info);
0686     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0687                    &frev, &crev, &data_offset)) {
0688         union gfx_info *gfx_info = (union gfx_info *)
0689             (mode_info->atom_context->bios + data_offset);
0690         if (frev == 2) {
0691             switch (crev) {
0692             case 4:
0693                 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
0694                 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
0695                 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
0696                 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
0697                 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
0698                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
0699                 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
0700                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
0701                 adev->gfx.config.gs_prim_buffer_depth =
0702                     le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
0703                 adev->gfx.config.double_offchip_lds_buf =
0704                     gfx_info->v24.gc_double_offchip_lds_buffer;
0705                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
0706                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
0707                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
0708                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
0709                 return 0;
0710             case 7:
0711                 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
0712                 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
0713                 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
0714                 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
0715                 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
0716                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
0717                 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
0718                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
0719                 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
0720                 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
0721                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
0722                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
0723                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
0724                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
0725                 return 0;
0726             default:
0727                 return -EINVAL;
0728             }
0729         } else if (frev == 3) {
0730             switch (crev) {
0731             case 0:
0732                 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
0733                 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
0734                 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
0735                 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
0736                 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
0737                 return 0;
0738             default:
0739                 return -EINVAL;
0740             }
0741         } else {
0742             return -EINVAL;
0743         }
0744 
0745     }
0746     return -EINVAL;
0747 }
0748 
0749 /*
0750  * Helper function to query two stage mem training capability
0751  *
0752  * @adev: amdgpu_device pointer
0753  *
0754  * Return true if two stage mem training is supported or false if not
0755  */
0756 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
0757 {
0758     u32 fw_cap;
0759 
0760     fw_cap = adev->mode_info.firmware_flags;
0761 
0762     return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
0763 }
0764 
0765 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
0766 {
0767     struct atom_context *ctx = adev->mode_info.atom_context;
0768     union firmware_info *firmware_info;
0769     int index;
0770     u16 data_offset, size;
0771     u8 frev, crev;
0772     int fw_reserved_fb_size;
0773 
0774     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0775             firmwareinfo);
0776 
0777     if (!amdgpu_atom_parse_data_header(ctx, index, &size,
0778                 &frev, &crev, &data_offset))
0779         /* fail to parse data_header */
0780         return 0;
0781 
0782     firmware_info = (union firmware_info *)(ctx->bios + data_offset);
0783 
0784     if (frev !=3)
0785         return -EINVAL;
0786 
0787     switch (crev) {
0788     case 4:
0789         fw_reserved_fb_size =
0790             (firmware_info->v34.fw_reserved_size_in_kb << 10);
0791         break;
0792     default:
0793         fw_reserved_fb_size = 0;
0794         break;
0795     }
0796 
0797     return fw_reserved_fb_size;
0798 }
0799 
0800 /*
0801  * Helper function to execute asic_init table
0802  *
0803  * @adev: amdgpu_device pointer
0804  * @fb_reset: flag to indicate whether fb is reset or not
0805  *
0806  * Return 0 if succeed, otherwise failed
0807  */
0808 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
0809 {
0810     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0811     struct atom_context *ctx;
0812     uint8_t frev, crev;
0813     uint16_t data_offset;
0814     uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
0815     struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
0816     int index;
0817 
0818     if (!mode_info)
0819         return -EINVAL;
0820 
0821     ctx = mode_info->atom_context;
0822     if (!ctx)
0823         return -EINVAL;
0824 
0825     /* query bootup sclk/mclk from firmware_info table */
0826     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0827                         firmwareinfo);
0828     if (amdgpu_atom_parse_data_header(ctx, index, NULL,
0829                 &frev, &crev, &data_offset)) {
0830         union firmware_info *firmware_info =
0831             (union firmware_info *)(ctx->bios +
0832                         data_offset);
0833 
0834         bootup_sclk_in10khz =
0835             le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
0836         bootup_mclk_in10khz =
0837             le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
0838     } else {
0839         return -EINVAL;
0840     }
0841 
0842     index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
0843                                             asic_init);
0844     if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
0845         if (frev == 2 && crev >= 1) {
0846             memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
0847             asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
0848             asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
0849             asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
0850             if (!fb_reset)
0851                 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
0852             else
0853                 asic_init_ps_v2_1.param.memparam.memflag = 0;
0854         } else {
0855             return -EINVAL;
0856         }
0857     } else {
0858         return -EINVAL;
0859     }
0860 
0861     return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1);
0862 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!