amd/amdgpu/amdgpu_atombios.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_ATOMBIOS_H__
0025 #define __AMDGPU_ATOMBIOS_H__
0026
0027 struct atom_clock_dividers {
0028     u32 post_div;
0029     union {
0030         struct {
0031 #ifdef __BIG_ENDIAN
0032             u32 reserved : 6;
0033             u32 whole_fb_div : 12;
0034             u32 frac_fb_div : 14;
0035 #else
0036             u32 frac_fb_div : 14;
0037             u32 whole_fb_div : 12;
0038             u32 reserved : 6;
0039 #endif
0040         };
0041         u32 fb_div;
0042     };
0043     u32 ref_div;
0044     bool enable_post_div;
0045     bool enable_dithen;
0046     u32 vco_mode;
0047     u32 real_clock;
0048     /* added for CI */
0049     u32 post_divider;
0050     u32 flags;
0051 };
0052
0053 struct atom_mpll_param {
0054     union {
0055         struct {
0056 #ifdef __BIG_ENDIAN
0057             u32 reserved : 8;
0058             u32 clkfrac : 12;
0059             u32 clkf : 12;
0060 #else
0061             u32 clkf : 12;
0062             u32 clkfrac : 12;
0063             u32 reserved : 8;
0064 #endif
0065         };
0066         u32 fb_div;
0067     };
0068     u32 post_div;
0069     u32 bwcntl;
0070     u32 dll_speed;
0071     u32 vco_mode;
0072     u32 yclk_sel;
0073     u32 qdr;
0074     u32 half_rate;
0075 };
0076
0077 #define MEM_TYPE_GDDR5  0x50
0078 #define MEM_TYPE_GDDR4  0x40
0079 #define MEM_TYPE_GDDR3  0x30
0080 #define MEM_TYPE_DDR2   0x20
0081 #define MEM_TYPE_GDDR1  0x10
0082 #define MEM_TYPE_DDR3   0xb0
0083 #define MEM_TYPE_MASK   0xf0
0084
0085 struct atom_memory_info {
0086     u8 mem_vendor;
0087     u8 mem_type;
0088 };
0089
0090 #define MAX_AC_TIMING_ENTRIES 16
0091
0092 struct atom_memory_clock_range_table
0093 {
0094     u8 num_entries;
0095     u8 rsv[3];
0096     u32 mclk[MAX_AC_TIMING_ENTRIES];
0097 };
0098
0099 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
0100 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
0101
0102 struct atom_mc_reg_entry {
0103     u32 mclk_max;
0104     u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
0105 };
0106
0107 struct atom_mc_register_address {
0108     u16 s1;
0109     u8 pre_reg_data;
0110 };
0111
0112 struct atom_mc_reg_table {
0113     u8 last;
0114     u8 num_entries;
0115     struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
0116     struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
0117 };
0118
0119 #define MAX_VOLTAGE_ENTRIES 32
0120
0121 struct atom_voltage_table_entry
0122 {
0123     u16 value;
0124     u32 smio_low;
0125 };
0126
0127 struct atom_voltage_table
0128 {
0129     u32 count;
0130     u32 mask_low;
0131     u32 phase_delay;
0132     struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
0133 };
0134
0135 struct amdgpu_gpio_rec
0136 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
0137                 u8 id);
0138
0139 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
0140                               uint8_t id);
0141 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev);
0142
0143 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev);
0144
0145 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev);
0146
0147 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev);
0148
0149 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev);
0150
0151 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev);
0152
0153 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
0154                       struct amdgpu_atom_ss *ss,
0155                       int id, u32 clock);
0156
0157 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
0158                        u8 clock_type,
0159                        u32 clock,
0160                        bool strobe_mode,
0161                        struct atom_clock_dividers *dividers);
0162
0163 #ifdef CONFIG_DRM_AMDGPU_SI
0164 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
0165                         u32 clock,
0166                         bool strobe_mode,
0167                         struct atom_mpll_param *mpll_param);
0168
0169 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
0170                          u32 eng_clock, u32 mem_clock);
0171
0172 bool
0173 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
0174                 u8 voltage_type, u8 voltage_mode);
0175
0176 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
0177                       u8 voltage_type, u8 voltage_mode,
0178                       struct atom_voltage_table *voltage_table);
0179
0180 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
0181                       u8 module_index,
0182                       struct atom_mc_reg_table *reg_table);
0183 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
0184                  u16 voltage_id, u16 *voltage);
0185 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
0186                               u16 *voltage,
0187                               u16 leakage_idx);
0188 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
0189                       u16 *vddc, u16 *vddci, u16 *mvdd);
0190 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
0191                   u8 voltage_type,
0192                   u8 *svd_gpio_id, u8 *svc_gpio_id);
0193 #endif
0194
0195 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
0196
0197 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
0198 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
0199                           bool hung);
0200 void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev,
0201                               u32 backlight_level);
0202 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
0203
0204 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
0205 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
0206                        u8 clock_type,
0207                        u32 clock,
0208                        bool strobe_mode,
0209                        struct atom_clock_dividers *dividers);
0210
0211 int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
0212                    uint32_t table,
0213                    uint16_t *size,
0214                    uint8_t *frev,
0215                    uint8_t *crev,
0216                    uint8_t **addr);
0217
0218 void amdgpu_atombios_fini(struct amdgpu_device *adev);
0219 int amdgpu_atombios_init(struct amdgpu_device *adev);
0220
0221 #endif