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0001 /*
0002  * Copyright 2007-8 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: Dave Airlie
0024  *          Alex Deucher
0025  */
0026 
0027 #include <drm/amdgpu_drm.h>
0028 #include "amdgpu.h"
0029 #include "amdgpu_atombios.h"
0030 #include "amdgpu_atomfirmware.h"
0031 #include "amdgpu_i2c.h"
0032 #include "amdgpu_display.h"
0033 
0034 #include "atom.h"
0035 #include "atom-bits.h"
0036 #include "atombios_encoders.h"
0037 #include "bif/bif_4_1_d.h"
0038 
0039 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
0040                       ATOM_GPIO_I2C_ASSIGMENT *gpio,
0041                       u8 index)
0042 {
0043 
0044 }
0045 
0046 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
0047 {
0048     struct amdgpu_i2c_bus_rec i2c;
0049 
0050     memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
0051 
0052     i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
0053     i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
0054     i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
0055     i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
0056     i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
0057     i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
0058     i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
0059     i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
0060     i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
0061     i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
0062     i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
0063     i2c.en_data_mask = (1 << gpio->ucDataEnShift);
0064     i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
0065     i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
0066     i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
0067     i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
0068 
0069     if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
0070         i2c.hw_capable = true;
0071     else
0072         i2c.hw_capable = false;
0073 
0074     if (gpio->sucI2cId.ucAccess == 0xa0)
0075         i2c.mm_i2c = true;
0076     else
0077         i2c.mm_i2c = false;
0078 
0079     i2c.i2c_id = gpio->sucI2cId.ucAccess;
0080 
0081     if (i2c.mask_clk_reg)
0082         i2c.valid = true;
0083     else
0084         i2c.valid = false;
0085 
0086     return i2c;
0087 }
0088 
0089 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
0090                               uint8_t id)
0091 {
0092     struct atom_context *ctx = adev->mode_info.atom_context;
0093     ATOM_GPIO_I2C_ASSIGMENT *gpio;
0094     struct amdgpu_i2c_bus_rec i2c;
0095     int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
0096     struct _ATOM_GPIO_I2C_INFO *i2c_info;
0097     uint16_t data_offset, size;
0098     int i, num_indices;
0099 
0100     memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
0101     i2c.valid = false;
0102 
0103     if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
0104         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
0105 
0106         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
0107             sizeof(ATOM_GPIO_I2C_ASSIGMENT);
0108 
0109         gpio = &i2c_info->asGPIO_Info[0];
0110         for (i = 0; i < num_indices; i++) {
0111 
0112             amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
0113 
0114             if (gpio->sucI2cId.ucAccess == id) {
0115                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
0116                 break;
0117             }
0118             gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
0119                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
0120         }
0121     }
0122 
0123     return i2c;
0124 }
0125 
0126 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
0127 {
0128     struct atom_context *ctx = adev->mode_info.atom_context;
0129     ATOM_GPIO_I2C_ASSIGMENT *gpio;
0130     struct amdgpu_i2c_bus_rec i2c;
0131     int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
0132     struct _ATOM_GPIO_I2C_INFO *i2c_info;
0133     uint16_t data_offset, size;
0134     int i, num_indices;
0135     char stmp[32];
0136 
0137     if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
0138         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
0139 
0140         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
0141             sizeof(ATOM_GPIO_I2C_ASSIGMENT);
0142 
0143         gpio = &i2c_info->asGPIO_Info[0];
0144         for (i = 0; i < num_indices; i++) {
0145             amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
0146 
0147             i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
0148 
0149             if (i2c.valid) {
0150                 sprintf(stmp, "0x%x", i2c.i2c_id);
0151                 adev->i2c_bus[i] = amdgpu_i2c_create(adev_to_drm(adev), &i2c, stmp);
0152             }
0153             gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
0154                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
0155         }
0156     }
0157 }
0158 
0159 struct amdgpu_gpio_rec
0160 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
0161                 u8 id)
0162 {
0163     struct atom_context *ctx = adev->mode_info.atom_context;
0164     struct amdgpu_gpio_rec gpio;
0165     int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
0166     struct _ATOM_GPIO_PIN_LUT *gpio_info;
0167     ATOM_GPIO_PIN_ASSIGNMENT *pin;
0168     u16 data_offset, size;
0169     int i, num_indices;
0170 
0171     memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
0172     gpio.valid = false;
0173 
0174     if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
0175         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
0176 
0177         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
0178             sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
0179 
0180         pin = gpio_info->asGPIO_Pin;
0181         for (i = 0; i < num_indices; i++) {
0182             if (id == pin->ucGPIO_ID) {
0183                 gpio.id = pin->ucGPIO_ID;
0184                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
0185                 gpio.shift = pin->ucGpioPinBitShift;
0186                 gpio.mask = (1 << pin->ucGpioPinBitShift);
0187                 gpio.valid = true;
0188                 break;
0189             }
0190             pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
0191                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
0192         }
0193     }
0194 
0195     return gpio;
0196 }
0197 
0198 static struct amdgpu_hpd
0199 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
0200                        struct amdgpu_gpio_rec *gpio)
0201 {
0202     struct amdgpu_hpd hpd;
0203     u32 reg;
0204 
0205     memset(&hpd, 0, sizeof(struct amdgpu_hpd));
0206 
0207     reg = amdgpu_display_hpd_get_gpio_reg(adev);
0208 
0209     hpd.gpio = *gpio;
0210     if (gpio->reg == reg) {
0211         switch(gpio->mask) {
0212         case (1 << 0):
0213             hpd.hpd = AMDGPU_HPD_1;
0214             break;
0215         case (1 << 8):
0216             hpd.hpd = AMDGPU_HPD_2;
0217             break;
0218         case (1 << 16):
0219             hpd.hpd = AMDGPU_HPD_3;
0220             break;
0221         case (1 << 24):
0222             hpd.hpd = AMDGPU_HPD_4;
0223             break;
0224         case (1 << 26):
0225             hpd.hpd = AMDGPU_HPD_5;
0226             break;
0227         case (1 << 28):
0228             hpd.hpd = AMDGPU_HPD_6;
0229             break;
0230         default:
0231             hpd.hpd = AMDGPU_HPD_NONE;
0232             break;
0233         }
0234     } else
0235         hpd.hpd = AMDGPU_HPD_NONE;
0236     return hpd;
0237 }
0238 
0239 static const int object_connector_convert[] = {
0240     DRM_MODE_CONNECTOR_Unknown,
0241     DRM_MODE_CONNECTOR_DVII,
0242     DRM_MODE_CONNECTOR_DVII,
0243     DRM_MODE_CONNECTOR_DVID,
0244     DRM_MODE_CONNECTOR_DVID,
0245     DRM_MODE_CONNECTOR_VGA,
0246     DRM_MODE_CONNECTOR_Composite,
0247     DRM_MODE_CONNECTOR_SVIDEO,
0248     DRM_MODE_CONNECTOR_Unknown,
0249     DRM_MODE_CONNECTOR_Unknown,
0250     DRM_MODE_CONNECTOR_9PinDIN,
0251     DRM_MODE_CONNECTOR_Unknown,
0252     DRM_MODE_CONNECTOR_HDMIA,
0253     DRM_MODE_CONNECTOR_HDMIB,
0254     DRM_MODE_CONNECTOR_LVDS,
0255     DRM_MODE_CONNECTOR_9PinDIN,
0256     DRM_MODE_CONNECTOR_Unknown,
0257     DRM_MODE_CONNECTOR_Unknown,
0258     DRM_MODE_CONNECTOR_Unknown,
0259     DRM_MODE_CONNECTOR_DisplayPort,
0260     DRM_MODE_CONNECTOR_eDP,
0261     DRM_MODE_CONNECTOR_Unknown
0262 };
0263 
0264 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
0265 {
0266     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0267     struct atom_context *ctx = mode_info->atom_context;
0268     int index = GetIndexIntoMasterTable(DATA, Object_Header);
0269     u16 size, data_offset;
0270     u8 frev, crev;
0271     ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
0272     ATOM_OBJECT_HEADER *obj_header;
0273 
0274     if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
0275         return false;
0276 
0277     if (crev < 2)
0278         return false;
0279 
0280     obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
0281     path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
0282         (ctx->bios + data_offset +
0283          le16_to_cpu(obj_header->usDisplayPathTableOffset));
0284 
0285     if (path_obj->ucNumOfDispPath)
0286         return true;
0287     else
0288         return false;
0289 }
0290 
0291 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
0292 {
0293     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0294     struct atom_context *ctx = mode_info->atom_context;
0295     int index = GetIndexIntoMasterTable(DATA, Object_Header);
0296     u16 size, data_offset;
0297     u8 frev, crev;
0298     ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
0299     ATOM_ENCODER_OBJECT_TABLE *enc_obj;
0300     ATOM_OBJECT_TABLE *router_obj;
0301     ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
0302     ATOM_OBJECT_HEADER *obj_header;
0303     int i, j, k, path_size, device_support;
0304     int connector_type;
0305     u16 conn_id, connector_object_id;
0306     struct amdgpu_i2c_bus_rec ddc_bus;
0307     struct amdgpu_router router;
0308     struct amdgpu_gpio_rec gpio;
0309     struct amdgpu_hpd hpd;
0310 
0311     if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
0312         return false;
0313 
0314     if (crev < 2)
0315         return false;
0316 
0317     obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
0318     path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
0319         (ctx->bios + data_offset +
0320          le16_to_cpu(obj_header->usDisplayPathTableOffset));
0321     con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
0322         (ctx->bios + data_offset +
0323          le16_to_cpu(obj_header->usConnectorObjectTableOffset));
0324     enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
0325         (ctx->bios + data_offset +
0326          le16_to_cpu(obj_header->usEncoderObjectTableOffset));
0327     router_obj = (ATOM_OBJECT_TABLE *)
0328         (ctx->bios + data_offset +
0329          le16_to_cpu(obj_header->usRouterObjectTableOffset));
0330     device_support = le16_to_cpu(obj_header->usDeviceSupport);
0331 
0332     path_size = 0;
0333     for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
0334         uint8_t *addr = (uint8_t *) path_obj->asDispPath;
0335         ATOM_DISPLAY_OBJECT_PATH *path;
0336         addr += path_size;
0337         path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
0338         path_size += le16_to_cpu(path->usSize);
0339 
0340         if (device_support & le16_to_cpu(path->usDeviceTag)) {
0341             uint8_t con_obj_id =
0342                 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
0343                 >> OBJECT_ID_SHIFT;
0344 
0345             /* Skip TV/CV support */
0346             if ((le16_to_cpu(path->usDeviceTag) ==
0347                  ATOM_DEVICE_TV1_SUPPORT) ||
0348                 (le16_to_cpu(path->usDeviceTag) ==
0349                  ATOM_DEVICE_CV_SUPPORT))
0350                 continue;
0351 
0352             if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
0353                 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
0354                       con_obj_id, le16_to_cpu(path->usDeviceTag));
0355                 continue;
0356             }
0357 
0358             connector_type =
0359                 object_connector_convert[con_obj_id];
0360             connector_object_id = con_obj_id;
0361 
0362             if (connector_type == DRM_MODE_CONNECTOR_Unknown)
0363                 continue;
0364 
0365             router.ddc_valid = false;
0366             router.cd_valid = false;
0367             for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
0368                 uint8_t grph_obj_type =
0369                     (le16_to_cpu(path->usGraphicObjIds[j]) &
0370                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
0371 
0372                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
0373                     for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
0374                         u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
0375                         if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
0376                             ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
0377                                 (ctx->bios + data_offset +
0378                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
0379                             ATOM_ENCODER_CAP_RECORD *cap_record;
0380                             u16 caps = 0;
0381 
0382                             while (record->ucRecordSize > 0 &&
0383                                    record->ucRecordType > 0 &&
0384                                    record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
0385                                 switch (record->ucRecordType) {
0386                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
0387                                     cap_record =(ATOM_ENCODER_CAP_RECORD *)
0388                                         record;
0389                                     caps = le16_to_cpu(cap_record->usEncoderCap);
0390                                     break;
0391                                 }
0392                                 record = (ATOM_COMMON_RECORD_HEADER *)
0393                                     ((char *)record + record->ucRecordSize);
0394                             }
0395                             amdgpu_display_add_encoder(adev, encoder_obj,
0396                                             le16_to_cpu(path->usDeviceTag),
0397                                             caps);
0398                         }
0399                     }
0400                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
0401                     for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
0402                         u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
0403                         if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
0404                             ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
0405                                 (ctx->bios + data_offset +
0406                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
0407                             ATOM_I2C_RECORD *i2c_record;
0408                             ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
0409                             ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
0410                             ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
0411                             ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
0412                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
0413                                 (ctx->bios + data_offset +
0414                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
0415                             u8 *num_dst_objs = (u8 *)
0416                                 ((u8 *)router_src_dst_table + 1 +
0417                                  (router_src_dst_table->ucNumberOfSrc * 2));
0418                             u16 *dst_objs = (u16 *)(num_dst_objs + 1);
0419                             int enum_id;
0420 
0421                             router.router_id = router_obj_id;
0422                             for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
0423                                 if (le16_to_cpu(path->usConnObjectId) ==
0424                                     le16_to_cpu(dst_objs[enum_id]))
0425                                     break;
0426                             }
0427 
0428                             while (record->ucRecordSize > 0 &&
0429                                    record->ucRecordType > 0 &&
0430                                    record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
0431                                 switch (record->ucRecordType) {
0432                                 case ATOM_I2C_RECORD_TYPE:
0433                                     i2c_record =
0434                                         (ATOM_I2C_RECORD *)
0435                                         record;
0436                                     i2c_config =
0437                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
0438                                         &i2c_record->sucI2cId;
0439                                     router.i2c_info =
0440                                         amdgpu_atombios_lookup_i2c_gpio(adev,
0441                                                        i2c_config->
0442                                                        ucAccess);
0443                                     router.i2c_addr = i2c_record->ucI2CAddr >> 1;
0444                                     break;
0445                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
0446                                     ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
0447                                         record;
0448                                     router.ddc_valid = true;
0449                                     router.ddc_mux_type = ddc_path->ucMuxType;
0450                                     router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
0451                                     router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
0452                                     break;
0453                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
0454                                     cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
0455                                         record;
0456                                     router.cd_valid = true;
0457                                     router.cd_mux_type = cd_path->ucMuxType;
0458                                     router.cd_mux_control_pin = cd_path->ucMuxControlPin;
0459                                     router.cd_mux_state = cd_path->ucMuxState[enum_id];
0460                                     break;
0461                                 }
0462                                 record = (ATOM_COMMON_RECORD_HEADER *)
0463                                     ((char *)record + record->ucRecordSize);
0464                             }
0465                         }
0466                     }
0467                 }
0468             }
0469 
0470             /* look up gpio for ddc, hpd */
0471             ddc_bus.valid = false;
0472             hpd.hpd = AMDGPU_HPD_NONE;
0473             if ((le16_to_cpu(path->usDeviceTag) &
0474                  (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
0475                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
0476                     if (le16_to_cpu(path->usConnObjectId) ==
0477                         le16_to_cpu(con_obj->asObjects[j].
0478                             usObjectID)) {
0479                         ATOM_COMMON_RECORD_HEADER
0480                             *record =
0481                             (ATOM_COMMON_RECORD_HEADER
0482                              *)
0483                             (ctx->bios + data_offset +
0484                              le16_to_cpu(con_obj->
0485                                  asObjects[j].
0486                                  usRecordOffset));
0487                         ATOM_I2C_RECORD *i2c_record;
0488                         ATOM_HPD_INT_RECORD *hpd_record;
0489                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
0490 
0491                         while (record->ucRecordSize > 0 &&
0492                                record->ucRecordType > 0 &&
0493                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
0494                             switch (record->ucRecordType) {
0495                             case ATOM_I2C_RECORD_TYPE:
0496                                 i2c_record =
0497                                     (ATOM_I2C_RECORD *)
0498                                     record;
0499                                 i2c_config =
0500                                     (ATOM_I2C_ID_CONFIG_ACCESS *)
0501                                     &i2c_record->sucI2cId;
0502                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
0503                                                  i2c_config->
0504                                                  ucAccess);
0505                                 break;
0506                             case ATOM_HPD_INT_RECORD_TYPE:
0507                                 hpd_record =
0508                                     (ATOM_HPD_INT_RECORD *)
0509                                     record;
0510                                 gpio = amdgpu_atombios_lookup_gpio(adev,
0511                                               hpd_record->ucHPDIntGPIOID);
0512                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
0513                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
0514                                 break;
0515                             }
0516                             record =
0517                                 (ATOM_COMMON_RECORD_HEADER
0518                                  *) ((char *)record
0519                                  +
0520                                  record->
0521                                  ucRecordSize);
0522                         }
0523                         break;
0524                     }
0525                 }
0526             }
0527 
0528             /* needed for aux chan transactions */
0529             ddc_bus.hpd = hpd.hpd;
0530 
0531             conn_id = le16_to_cpu(path->usConnObjectId);
0532 
0533             amdgpu_display_add_connector(adev,
0534                               conn_id,
0535                               le16_to_cpu(path->usDeviceTag),
0536                               connector_type, &ddc_bus,
0537                               connector_object_id,
0538                               &hpd,
0539                               &router);
0540 
0541         }
0542     }
0543 
0544     amdgpu_link_encoder_connector(adev_to_drm(adev));
0545 
0546     return true;
0547 }
0548 
0549 union firmware_info {
0550     ATOM_FIRMWARE_INFO info;
0551     ATOM_FIRMWARE_INFO_V1_2 info_12;
0552     ATOM_FIRMWARE_INFO_V1_3 info_13;
0553     ATOM_FIRMWARE_INFO_V1_4 info_14;
0554     ATOM_FIRMWARE_INFO_V2_1 info_21;
0555     ATOM_FIRMWARE_INFO_V2_2 info_22;
0556 };
0557 
0558 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
0559 {
0560     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0561     int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
0562     uint8_t frev, crev;
0563     uint16_t data_offset;
0564     int ret = -EINVAL;
0565 
0566     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0567                    &frev, &crev, &data_offset)) {
0568         int i;
0569         struct amdgpu_pll *ppll = &adev->clock.ppll[0];
0570         struct amdgpu_pll *spll = &adev->clock.spll;
0571         struct amdgpu_pll *mpll = &adev->clock.mpll;
0572         union firmware_info *firmware_info =
0573             (union firmware_info *)(mode_info->atom_context->bios +
0574                         data_offset);
0575         /* pixel clocks */
0576         ppll->reference_freq =
0577             le16_to_cpu(firmware_info->info.usReferenceClock);
0578         ppll->reference_div = 0;
0579 
0580         ppll->pll_out_min =
0581             le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
0582         ppll->pll_out_max =
0583             le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
0584 
0585         ppll->lcd_pll_out_min =
0586             le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
0587         if (ppll->lcd_pll_out_min == 0)
0588             ppll->lcd_pll_out_min = ppll->pll_out_min;
0589         ppll->lcd_pll_out_max =
0590             le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
0591         if (ppll->lcd_pll_out_max == 0)
0592             ppll->lcd_pll_out_max = ppll->pll_out_max;
0593 
0594         if (ppll->pll_out_min == 0)
0595             ppll->pll_out_min = 64800;
0596 
0597         ppll->pll_in_min =
0598             le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
0599         ppll->pll_in_max =
0600             le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
0601 
0602         ppll->min_post_div = 2;
0603         ppll->max_post_div = 0x7f;
0604         ppll->min_frac_feedback_div = 0;
0605         ppll->max_frac_feedback_div = 9;
0606         ppll->min_ref_div = 2;
0607         ppll->max_ref_div = 0x3ff;
0608         ppll->min_feedback_div = 4;
0609         ppll->max_feedback_div = 0xfff;
0610         ppll->best_vco = 0;
0611 
0612         for (i = 1; i < AMDGPU_MAX_PPLL; i++)
0613             adev->clock.ppll[i] = *ppll;
0614 
0615         /* system clock */
0616         spll->reference_freq =
0617             le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
0618         spll->reference_div = 0;
0619 
0620         spll->pll_out_min =
0621             le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
0622         spll->pll_out_max =
0623             le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
0624 
0625         /* ??? */
0626         if (spll->pll_out_min == 0)
0627             spll->pll_out_min = 64800;
0628 
0629         spll->pll_in_min =
0630             le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
0631         spll->pll_in_max =
0632             le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
0633 
0634         spll->min_post_div = 1;
0635         spll->max_post_div = 1;
0636         spll->min_ref_div = 2;
0637         spll->max_ref_div = 0xff;
0638         spll->min_feedback_div = 4;
0639         spll->max_feedback_div = 0xff;
0640         spll->best_vco = 0;
0641 
0642         /* memory clock */
0643         mpll->reference_freq =
0644             le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
0645         mpll->reference_div = 0;
0646 
0647         mpll->pll_out_min =
0648             le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
0649         mpll->pll_out_max =
0650             le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
0651 
0652         /* ??? */
0653         if (mpll->pll_out_min == 0)
0654             mpll->pll_out_min = 64800;
0655 
0656         mpll->pll_in_min =
0657             le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
0658         mpll->pll_in_max =
0659             le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
0660 
0661         adev->clock.default_sclk =
0662             le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
0663         adev->clock.default_mclk =
0664             le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
0665 
0666         mpll->min_post_div = 1;
0667         mpll->max_post_div = 1;
0668         mpll->min_ref_div = 2;
0669         mpll->max_ref_div = 0xff;
0670         mpll->min_feedback_div = 4;
0671         mpll->max_feedback_div = 0xff;
0672         mpll->best_vco = 0;
0673 
0674         /* disp clock */
0675         adev->clock.default_dispclk =
0676             le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
0677         /* set a reasonable default for DP */
0678         if (adev->clock.default_dispclk < 53900) {
0679             DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
0680                   adev->clock.default_dispclk / 100);
0681             adev->clock.default_dispclk = 60000;
0682         } else if (adev->clock.default_dispclk <= 60000) {
0683             DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
0684                   adev->clock.default_dispclk / 100);
0685             adev->clock.default_dispclk = 62500;
0686         }
0687         adev->clock.dp_extclk =
0688             le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
0689         adev->clock.current_dispclk = adev->clock.default_dispclk;
0690 
0691         adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
0692         if (adev->clock.max_pixel_clock == 0)
0693             adev->clock.max_pixel_clock = 40000;
0694 
0695         /* not technically a clock, but... */
0696         adev->mode_info.firmware_flags =
0697             le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
0698 
0699         ret = 0;
0700     }
0701 
0702     adev->pm.current_sclk = adev->clock.default_sclk;
0703     adev->pm.current_mclk = adev->clock.default_mclk;
0704 
0705     return ret;
0706 }
0707 
0708 union gfx_info {
0709     ATOM_GFX_INFO_V2_1 info;
0710 };
0711 
0712 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
0713 {
0714     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0715     int index = GetIndexIntoMasterTable(DATA, GFX_Info);
0716     uint8_t frev, crev;
0717     uint16_t data_offset;
0718     int ret = -EINVAL;
0719 
0720     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
0721                    &frev, &crev, &data_offset)) {
0722         union gfx_info *gfx_info = (union gfx_info *)
0723             (mode_info->atom_context->bios + data_offset);
0724 
0725         adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
0726         adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
0727         adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
0728         adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
0729         adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
0730         adev->gfx.config.max_texture_channel_caches =
0731             gfx_info->info.max_texture_channel_caches;
0732 
0733         ret = 0;
0734     }
0735     return ret;
0736 }
0737 
0738 union igp_info {
0739     struct _ATOM_INTEGRATED_SYSTEM_INFO info;
0740     struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
0741     struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
0742     struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
0743     struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
0744     struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
0745 };
0746 
0747 /*
0748  * Return vram width from integrated system info table, if available,
0749  * or 0 if not.
0750  */
0751 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
0752 {
0753     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0754     int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
0755     u16 data_offset, size;
0756     union igp_info *igp_info;
0757     u8 frev, crev;
0758 
0759     /* get any igp specific overrides */
0760     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
0761                    &frev, &crev, &data_offset)) {
0762         igp_info = (union igp_info *)
0763             (mode_info->atom_context->bios + data_offset);
0764         switch (crev) {
0765         case 8:
0766         case 9:
0767             return igp_info->info_8.ucUMAChannelNumber * 64;
0768         default:
0769             return 0;
0770         }
0771     }
0772 
0773     return 0;
0774 }
0775 
0776 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
0777                          struct amdgpu_atom_ss *ss,
0778                          int id)
0779 {
0780     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0781     int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
0782     u16 data_offset, size;
0783     union igp_info *igp_info;
0784     u8 frev, crev;
0785     u16 percentage = 0, rate = 0;
0786 
0787     /* get any igp specific overrides */
0788     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
0789                    &frev, &crev, &data_offset)) {
0790         igp_info = (union igp_info *)
0791             (mode_info->atom_context->bios + data_offset);
0792         switch (crev) {
0793         case 6:
0794             switch (id) {
0795             case ASIC_INTERNAL_SS_ON_TMDS:
0796                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
0797                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
0798                 break;
0799             case ASIC_INTERNAL_SS_ON_HDMI:
0800                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
0801                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
0802                 break;
0803             case ASIC_INTERNAL_SS_ON_LVDS:
0804                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
0805                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
0806                 break;
0807             }
0808             break;
0809         case 7:
0810             switch (id) {
0811             case ASIC_INTERNAL_SS_ON_TMDS:
0812                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
0813                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
0814                 break;
0815             case ASIC_INTERNAL_SS_ON_HDMI:
0816                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
0817                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
0818                 break;
0819             case ASIC_INTERNAL_SS_ON_LVDS:
0820                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
0821                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
0822                 break;
0823             }
0824             break;
0825         case 8:
0826             switch (id) {
0827             case ASIC_INTERNAL_SS_ON_TMDS:
0828                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
0829                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
0830                 break;
0831             case ASIC_INTERNAL_SS_ON_HDMI:
0832                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
0833                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
0834                 break;
0835             case ASIC_INTERNAL_SS_ON_LVDS:
0836                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
0837                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
0838                 break;
0839             }
0840             break;
0841         case 9:
0842             switch (id) {
0843             case ASIC_INTERNAL_SS_ON_TMDS:
0844                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
0845                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
0846                 break;
0847             case ASIC_INTERNAL_SS_ON_HDMI:
0848                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
0849                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
0850                 break;
0851             case ASIC_INTERNAL_SS_ON_LVDS:
0852                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
0853                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
0854                 break;
0855             }
0856             break;
0857         default:
0858             DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
0859             break;
0860         }
0861         if (percentage)
0862             ss->percentage = percentage;
0863         if (rate)
0864             ss->rate = rate;
0865     }
0866 }
0867 
0868 union asic_ss_info {
0869     struct _ATOM_ASIC_INTERNAL_SS_INFO info;
0870     struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
0871     struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
0872 };
0873 
0874 union asic_ss_assignment {
0875     struct _ATOM_ASIC_SS_ASSIGNMENT v1;
0876     struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
0877     struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
0878 };
0879 
0880 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
0881                       struct amdgpu_atom_ss *ss,
0882                       int id, u32 clock)
0883 {
0884     struct amdgpu_mode_info *mode_info = &adev->mode_info;
0885     int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
0886     uint16_t data_offset, size;
0887     union asic_ss_info *ss_info;
0888     union asic_ss_assignment *ss_assign;
0889     uint8_t frev, crev;
0890     int i, num_indices;
0891 
0892     if (id == ASIC_INTERNAL_MEMORY_SS) {
0893         if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
0894             return false;
0895     }
0896     if (id == ASIC_INTERNAL_ENGINE_SS) {
0897         if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
0898             return false;
0899     }
0900 
0901     memset(ss, 0, sizeof(struct amdgpu_atom_ss));
0902     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
0903                    &frev, &crev, &data_offset)) {
0904 
0905         ss_info =
0906             (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
0907 
0908         switch (frev) {
0909         case 1:
0910             num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
0911                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
0912 
0913             ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
0914             for (i = 0; i < num_indices; i++) {
0915                 if ((ss_assign->v1.ucClockIndication == id) &&
0916                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
0917                     ss->percentage =
0918                         le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
0919                     ss->type = ss_assign->v1.ucSpreadSpectrumMode;
0920                     ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
0921                     ss->percentage_divider = 100;
0922                     return true;
0923                 }
0924                 ss_assign = (union asic_ss_assignment *)
0925                     ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
0926             }
0927             break;
0928         case 2:
0929             num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
0930                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
0931             ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
0932             for (i = 0; i < num_indices; i++) {
0933                 if ((ss_assign->v2.ucClockIndication == id) &&
0934                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
0935                     ss->percentage =
0936                         le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
0937                     ss->type = ss_assign->v2.ucSpreadSpectrumMode;
0938                     ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
0939                     ss->percentage_divider = 100;
0940                     if ((crev == 2) &&
0941                         ((id == ASIC_INTERNAL_ENGINE_SS) ||
0942                          (id == ASIC_INTERNAL_MEMORY_SS)))
0943                         ss->rate /= 100;
0944                     return true;
0945                 }
0946                 ss_assign = (union asic_ss_assignment *)
0947                     ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
0948             }
0949             break;
0950         case 3:
0951             num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
0952                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
0953             ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
0954             for (i = 0; i < num_indices; i++) {
0955                 if ((ss_assign->v3.ucClockIndication == id) &&
0956                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
0957                     ss->percentage =
0958                         le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
0959                     ss->type = ss_assign->v3.ucSpreadSpectrumMode;
0960                     ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
0961                     if (ss_assign->v3.ucSpreadSpectrumMode &
0962                         SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
0963                         ss->percentage_divider = 1000;
0964                     else
0965                         ss->percentage_divider = 100;
0966                     if ((id == ASIC_INTERNAL_ENGINE_SS) ||
0967                         (id == ASIC_INTERNAL_MEMORY_SS))
0968                         ss->rate /= 100;
0969                     if (adev->flags & AMD_IS_APU)
0970                         amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
0971                     return true;
0972                 }
0973                 ss_assign = (union asic_ss_assignment *)
0974                     ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
0975             }
0976             break;
0977         default:
0978             DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
0979             break;
0980         }
0981 
0982     }
0983     return false;
0984 }
0985 
0986 union get_clock_dividers {
0987     struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
0988     struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
0989     struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
0990     struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
0991     struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
0992     struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
0993     struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
0994 };
0995 
0996 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
0997                        u8 clock_type,
0998                        u32 clock,
0999                        bool strobe_mode,
1000                        struct atom_clock_dividers *dividers)
1001 {
1002     union get_clock_dividers args;
1003     int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1004     u8 frev, crev;
1005 
1006     memset(&args, 0, sizeof(args));
1007     memset(dividers, 0, sizeof(struct atom_clock_dividers));
1008 
1009     if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1010         return -EINVAL;
1011 
1012     switch (crev) {
1013     case 2:
1014     case 3:
1015     case 5:
1016         /* r6xx, r7xx, evergreen, ni, si.
1017          * TODO: add support for asic_type <= CHIP_RV770*/
1018         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1019             args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1020 
1021             amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1022 
1023             dividers->post_div = args.v3.ucPostDiv;
1024             dividers->enable_post_div = (args.v3.ucCntlFlag &
1025                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1026             dividers->enable_dithen = (args.v3.ucCntlFlag &
1027                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1028             dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1029             dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1030             dividers->ref_div = args.v3.ucRefDiv;
1031             dividers->vco_mode = (args.v3.ucCntlFlag &
1032                           ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1033         } else {
1034             /* for SI we use ComputeMemoryClockParam for memory plls */
1035             if (adev->asic_type >= CHIP_TAHITI)
1036                 return -EINVAL;
1037             args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1038             if (strobe_mode)
1039                 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1040 
1041             amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1042 
1043             dividers->post_div = args.v5.ucPostDiv;
1044             dividers->enable_post_div = (args.v5.ucCntlFlag &
1045                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1046             dividers->enable_dithen = (args.v5.ucCntlFlag &
1047                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1048             dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1049             dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1050             dividers->ref_div = args.v5.ucRefDiv;
1051             dividers->vco_mode = (args.v5.ucCntlFlag &
1052                           ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1053         }
1054         break;
1055     case 4:
1056         /* fusion */
1057         args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
1058 
1059         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1060 
1061         dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1062         dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1063         break;
1064     case 6:
1065         /* CI */
1066         /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1067         args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1068         args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
1069 
1070         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1071 
1072         dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1073         dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1074         dividers->ref_div = args.v6_out.ucPllRefDiv;
1075         dividers->post_div = args.v6_out.ucPllPostDiv;
1076         dividers->flags = args.v6_out.ucPllCntlFlag;
1077         dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1078         dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1079         break;
1080     default:
1081         return -EINVAL;
1082     }
1083     return 0;
1084 }
1085 
1086 #ifdef CONFIG_DRM_AMDGPU_SI
1087 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1088                         u32 clock,
1089                         bool strobe_mode,
1090                         struct atom_mpll_param *mpll_param)
1091 {
1092     COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1093     int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1094     u8 frev, crev;
1095 
1096     memset(&args, 0, sizeof(args));
1097     memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1098 
1099     if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1100         return -EINVAL;
1101 
1102     switch (frev) {
1103     case 2:
1104         switch (crev) {
1105         case 1:
1106             /* SI */
1107             args.ulClock = cpu_to_le32(clock);  /* 10 khz */
1108             args.ucInputFlag = 0;
1109             if (strobe_mode)
1110                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1111 
1112             amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1113 
1114             mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1115             mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1116             mpll_param->post_div = args.ucPostDiv;
1117             mpll_param->dll_speed = args.ucDllSpeed;
1118             mpll_param->bwcntl = args.ucBWCntl;
1119             mpll_param->vco_mode =
1120                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1121             mpll_param->yclk_sel =
1122                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1123             mpll_param->qdr =
1124                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1125             mpll_param->half_rate =
1126                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1127             break;
1128         default:
1129             return -EINVAL;
1130         }
1131         break;
1132     default:
1133         return -EINVAL;
1134     }
1135     return 0;
1136 }
1137 
1138 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1139                          u32 eng_clock, u32 mem_clock)
1140 {
1141     SET_ENGINE_CLOCK_PS_ALLOCATION args;
1142     int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1143     u32 tmp;
1144 
1145     memset(&args, 0, sizeof(args));
1146 
1147     tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1148     tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1149 
1150     args.ulTargetEngineClock = cpu_to_le32(tmp);
1151     if (mem_clock)
1152         args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1153 
1154     amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1155 }
1156 
1157 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1158                       u16 *vddc, u16 *vddci, u16 *mvdd)
1159 {
1160     struct amdgpu_mode_info *mode_info = &adev->mode_info;
1161     int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1162     u8 frev, crev;
1163     u16 data_offset;
1164     union firmware_info *firmware_info;
1165 
1166     *vddc = 0;
1167     *vddci = 0;
1168     *mvdd = 0;
1169 
1170     if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1171                    &frev, &crev, &data_offset)) {
1172         firmware_info =
1173             (union firmware_info *)(mode_info->atom_context->bios +
1174                         data_offset);
1175         *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1176         if ((frev == 2) && (crev >= 2)) {
1177             *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1178             *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1179         }
1180     }
1181 }
1182 
1183 union set_voltage {
1184     struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1185     struct _SET_VOLTAGE_PARAMETERS v1;
1186     struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1187     struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1188 };
1189 
1190 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1191                  u16 voltage_id, u16 *voltage)
1192 {
1193     union set_voltage args;
1194     int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1195     u8 frev, crev;
1196 
1197     if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1198         return -EINVAL;
1199 
1200     switch (crev) {
1201     case 1:
1202         return -EINVAL;
1203     case 2:
1204         args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1205         args.v2.ucVoltageMode = 0;
1206         args.v2.usVoltageLevel = 0;
1207 
1208         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1209 
1210         *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1211         break;
1212     case 3:
1213         args.v3.ucVoltageType = voltage_type;
1214         args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1215         args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1216 
1217         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1218 
1219         *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1220         break;
1221     default:
1222         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1223         return -EINVAL;
1224     }
1225 
1226     return 0;
1227 }
1228 
1229 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1230                               u16 *voltage,
1231                               u16 leakage_idx)
1232 {
1233     return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1234 }
1235 
1236 union voltage_object_info {
1237     struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1238     struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1239     struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1240 };
1241 
1242 union voltage_object {
1243     struct _ATOM_VOLTAGE_OBJECT v1;
1244     struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1245     union _ATOM_VOLTAGE_OBJECT_V3 v3;
1246 };
1247 
1248 
1249 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1250                                     u8 voltage_type, u8 voltage_mode)
1251 {
1252     u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1253     u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1254     u8 *start = (u8 *)v3;
1255 
1256     while (offset < size) {
1257         ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1258         if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1259             (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1260             return vo;
1261         offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1262     }
1263     return NULL;
1264 }
1265 
1266 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1267                   u8 voltage_type,
1268                   u8 *svd_gpio_id, u8 *svc_gpio_id)
1269 {
1270     int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1271     u8 frev, crev;
1272     u16 data_offset, size;
1273     union voltage_object_info *voltage_info;
1274     union voltage_object *voltage_object = NULL;
1275 
1276     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1277                    &frev, &crev, &data_offset)) {
1278         voltage_info = (union voltage_object_info *)
1279             (adev->mode_info.atom_context->bios + data_offset);
1280 
1281         switch (frev) {
1282         case 3:
1283             switch (crev) {
1284             case 1:
1285                 voltage_object = (union voltage_object *)
1286                     amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1287                                       voltage_type,
1288                                       VOLTAGE_OBJ_SVID2);
1289                 if (voltage_object) {
1290                     *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1291                     *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1292                 } else {
1293                     return -EINVAL;
1294                 }
1295                 break;
1296             default:
1297                 DRM_ERROR("unknown voltage object table\n");
1298                 return -EINVAL;
1299             }
1300             break;
1301         default:
1302             DRM_ERROR("unknown voltage object table\n");
1303             return -EINVAL;
1304         }
1305 
1306     }
1307     return 0;
1308 }
1309 
1310 bool
1311 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1312                 u8 voltage_type, u8 voltage_mode)
1313 {
1314     int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1315     u8 frev, crev;
1316     u16 data_offset, size;
1317     union voltage_object_info *voltage_info;
1318 
1319     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1320                    &frev, &crev, &data_offset)) {
1321         voltage_info = (union voltage_object_info *)
1322             (adev->mode_info.atom_context->bios + data_offset);
1323 
1324         switch (frev) {
1325         case 3:
1326             switch (crev) {
1327             case 1:
1328                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1329                                   voltage_type, voltage_mode))
1330                     return true;
1331                 break;
1332             default:
1333                 DRM_ERROR("unknown voltage object table\n");
1334                 return false;
1335             }
1336             break;
1337         default:
1338             DRM_ERROR("unknown voltage object table\n");
1339             return false;
1340         }
1341 
1342     }
1343     return false;
1344 }
1345 
1346 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1347                       u8 voltage_type, u8 voltage_mode,
1348                       struct atom_voltage_table *voltage_table)
1349 {
1350     int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1351     u8 frev, crev;
1352     u16 data_offset, size;
1353     int i;
1354     union voltage_object_info *voltage_info;
1355     union voltage_object *voltage_object = NULL;
1356 
1357     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1358                    &frev, &crev, &data_offset)) {
1359         voltage_info = (union voltage_object_info *)
1360             (adev->mode_info.atom_context->bios + data_offset);
1361 
1362         switch (frev) {
1363         case 3:
1364             switch (crev) {
1365             case 1:
1366                 voltage_object = (union voltage_object *)
1367                     amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1368                                       voltage_type, voltage_mode);
1369                 if (voltage_object) {
1370                     ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1371                         &voltage_object->v3.asGpioVoltageObj;
1372                     VOLTAGE_LUT_ENTRY_V2 *lut;
1373                     if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1374                         return -EINVAL;
1375                     lut = &gpio->asVolGpioLut[0];
1376                     for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1377                         voltage_table->entries[i].value =
1378                             le16_to_cpu(lut->usVoltageValue);
1379                         voltage_table->entries[i].smio_low =
1380                             le32_to_cpu(lut->ulVoltageId);
1381                         lut = (VOLTAGE_LUT_ENTRY_V2 *)
1382                             ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1383                     }
1384                     voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1385                     voltage_table->count = gpio->ucGpioEntryNum;
1386                     voltage_table->phase_delay = gpio->ucPhaseDelay;
1387                     return 0;
1388                 }
1389                 break;
1390             default:
1391                 DRM_ERROR("unknown voltage object table\n");
1392                 return -EINVAL;
1393             }
1394             break;
1395         default:
1396             DRM_ERROR("unknown voltage object table\n");
1397             return -EINVAL;
1398         }
1399     }
1400     return -EINVAL;
1401 }
1402 
1403 union vram_info {
1404     struct _ATOM_VRAM_INFO_V3 v1_3;
1405     struct _ATOM_VRAM_INFO_V4 v1_4;
1406     struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1407 };
1408 
1409 #define MEM_ID_MASK           0xff000000
1410 #define MEM_ID_SHIFT          24
1411 #define CLOCK_RANGE_MASK      0x00ffffff
1412 #define CLOCK_RANGE_SHIFT     0
1413 #define LOW_NIBBLE_MASK       0xf
1414 #define DATA_EQU_PREV         0
1415 #define DATA_FROM_TABLE       4
1416 
1417 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1418                       u8 module_index,
1419                       struct atom_mc_reg_table *reg_table)
1420 {
1421     int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1422     u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1423     u32 i = 0, j;
1424     u16 data_offset, size;
1425     union vram_info *vram_info;
1426 
1427     memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1428 
1429     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1430                    &frev, &crev, &data_offset)) {
1431         vram_info = (union vram_info *)
1432             (adev->mode_info.atom_context->bios + data_offset);
1433         switch (frev) {
1434         case 1:
1435             DRM_ERROR("old table version %d, %d\n", frev, crev);
1436             return -EINVAL;
1437         case 2:
1438             switch (crev) {
1439             case 1:
1440                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1441                     ATOM_INIT_REG_BLOCK *reg_block =
1442                         (ATOM_INIT_REG_BLOCK *)
1443                         ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1444                     ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1445                         (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1446                         ((u8 *)reg_block + (2 * sizeof(u16)) +
1447                          le16_to_cpu(reg_block->usRegIndexTblSize));
1448                     ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1449                     num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1450                                sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1451                     if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1452                         return -EINVAL;
1453                     while (i < num_entries) {
1454                         if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1455                             break;
1456                         reg_table->mc_reg_address[i].s1 =
1457                             (u16)(le16_to_cpu(format->usRegIndex));
1458                         reg_table->mc_reg_address[i].pre_reg_data =
1459                             (u8)(format->ucPreRegDataLength);
1460                         i++;
1461                         format = (ATOM_INIT_REG_INDEX_FORMAT *)
1462                             ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1463                     }
1464                     reg_table->last = i;
1465                     while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1466                            (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1467                         t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1468                                 >> MEM_ID_SHIFT);
1469                         if (module_index == t_mem_id) {
1470                             reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1471                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1472                                       >> CLOCK_RANGE_SHIFT);
1473                             for (i = 0, j = 1; i < reg_table->last; i++) {
1474                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1475                                     reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1476                                         (u32)le32_to_cpu(*((u32 *)reg_data + j));
1477                                     j++;
1478                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1479                                     reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1480                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1481                                 }
1482                             }
1483                             num_ranges++;
1484                         }
1485                         reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1486                             ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1487                     }
1488                     if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1489                         return -EINVAL;
1490                     reg_table->num_entries = num_ranges;
1491                 } else
1492                     return -EINVAL;
1493                 break;
1494             default:
1495                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1496                 return -EINVAL;
1497             }
1498             break;
1499         default:
1500             DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1501             return -EINVAL;
1502         }
1503         return 0;
1504     }
1505     return -EINVAL;
1506 }
1507 #endif
1508 
1509 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1510 {
1511     int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1512     u8 frev, crev;
1513     u16 data_offset, size;
1514 
1515     if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1516                       &frev, &crev, &data_offset))
1517         return true;
1518 
1519     return false;
1520 }
1521 
1522 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1523 {
1524     uint32_t bios_6_scratch;
1525 
1526     bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1527 
1528     if (lock) {
1529         bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1530         bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1531     } else {
1532         bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1533         bios_6_scratch |= ATOM_S6_ACC_MODE;
1534     }
1535 
1536     WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1537 }
1538 
1539 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1540 {
1541     uint32_t bios_2_scratch, bios_6_scratch;
1542 
1543     adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1544 
1545     bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1546     bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1547 
1548     /* let the bios control the backlight */
1549     bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1550 
1551     /* tell the bios not to handle mode switching */
1552     bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1553 
1554     /* clear the vbios dpms state */
1555     bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1556 
1557     WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1558     WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1559 }
1560 
1561 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1562                           bool hung)
1563 {
1564     u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1565 
1566     if (hung)
1567         tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1568     else
1569         tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1570 
1571     WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1572 }
1573 
1574 void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev,
1575                               u32 backlight_level)
1576 {
1577     u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
1578 
1579     tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
1580     tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
1581         ATOM_S2_CURRENT_BL_LEVEL_MASK;
1582 
1583     WREG32(adev->bios_scratch_reg_offset + 2, tmp);
1584 }
1585 
1586 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1587 {
1588     u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1589 
1590     if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1591         return false;
1592     else
1593         return true;
1594 }
1595 
1596 /* Atom needs data in little endian format so swap as appropriate when copying
1597  * data to or from atom. Note that atom operates on dw units.
1598  *
1599  * Use to_le=true when sending data to atom and provide at least
1600  * ALIGN(num_bytes,4) bytes in the dst buffer.
1601  *
1602  * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1603  * byes in the src buffer.
1604  */
1605 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1606 {
1607 #ifdef __BIG_ENDIAN
1608     u32 src_tmp[5], dst_tmp[5];
1609     int i;
1610     u8 align_num_bytes = ALIGN(num_bytes, 4);
1611 
1612     if (to_le) {
1613         memcpy(src_tmp, src, num_bytes);
1614         for (i = 0; i < align_num_bytes / 4; i++)
1615             dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1616         memcpy(dst, dst_tmp, align_num_bytes);
1617     } else {
1618         memcpy(src_tmp, src, align_num_bytes);
1619         for (i = 0; i < align_num_bytes / 4; i++)
1620             dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1621         memcpy(dst, dst_tmp, num_bytes);
1622     }
1623 #else
1624     memcpy(dst, src, num_bytes);
1625 #endif
1626 }
1627 
1628 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1629 {
1630     struct atom_context *ctx = adev->mode_info.atom_context;
1631     int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1632     uint16_t data_offset;
1633     int usage_bytes = 0;
1634     struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1635     u64 start_addr;
1636     u64 size;
1637 
1638     if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1639         firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1640 
1641         DRM_DEBUG("atom firmware requested %08x %dkb\n",
1642               le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1643               le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1644 
1645         start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
1646         size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
1647 
1648         if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
1649             (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
1650             ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
1651             /* Firmware request VRAM reservation for SR-IOV */
1652             adev->mman.fw_vram_usage_start_offset = (start_addr &
1653                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
1654             adev->mman.fw_vram_usage_size = size << 10;
1655             /* Use the default scratch size */
1656             usage_bytes = 0;
1657         } else {
1658             usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1659         }
1660     }
1661     ctx->scratch_size_bytes = 0;
1662     if (usage_bytes == 0)
1663         usage_bytes = 20 * 1024;
1664     /* allocate some scratch memory */
1665     ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1666     if (!ctx->scratch)
1667         return -ENOMEM;
1668     ctx->scratch_size_bytes = usage_bytes;
1669     return 0;
1670 }
1671 
1672 /* ATOM accessor methods */
1673 /*
1674  * ATOM is an interpreted byte code stored in tables in the vbios.  The
1675  * driver registers callbacks to access registers and the interpreter
1676  * in the driver parses the tables and executes then to program specific
1677  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
1678  * atombios.h, and atom.c
1679  */
1680 
1681 /**
1682  * cail_pll_read - read PLL register
1683  *
1684  * @info: atom card_info pointer
1685  * @reg: PLL register offset
1686  *
1687  * Provides a PLL register accessor for the atom interpreter (r4xx+).
1688  * Returns the value of the PLL register.
1689  */
1690 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
1691 {
1692     return 0;
1693 }
1694 
1695 /**
1696  * cail_pll_write - write PLL register
1697  *
1698  * @info: atom card_info pointer
1699  * @reg: PLL register offset
1700  * @val: value to write to the pll register
1701  *
1702  * Provides a PLL register accessor for the atom interpreter (r4xx+).
1703  */
1704 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
1705 {
1706 
1707 }
1708 
1709 /**
1710  * cail_mc_read - read MC (Memory Controller) register
1711  *
1712  * @info: atom card_info pointer
1713  * @reg: MC register offset
1714  *
1715  * Provides an MC register accessor for the atom interpreter (r4xx+).
1716  * Returns the value of the MC register.
1717  */
1718 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
1719 {
1720     return 0;
1721 }
1722 
1723 /**
1724  * cail_mc_write - write MC (Memory Controller) register
1725  *
1726  * @info: atom card_info pointer
1727  * @reg: MC register offset
1728  * @val: value to write to the pll register
1729  *
1730  * Provides a MC register accessor for the atom interpreter (r4xx+).
1731  */
1732 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
1733 {
1734 
1735 }
1736 
1737 /**
1738  * cail_reg_write - write MMIO register
1739  *
1740  * @info: atom card_info pointer
1741  * @reg: MMIO register offset
1742  * @val: value to write to the pll register
1743  *
1744  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
1745  */
1746 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
1747 {
1748     struct amdgpu_device *adev = drm_to_adev(info->dev);
1749 
1750     WREG32(reg, val);
1751 }
1752 
1753 /**
1754  * cail_reg_read - read MMIO register
1755  *
1756  * @info: atom card_info pointer
1757  * @reg: MMIO register offset
1758  *
1759  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
1760  * Returns the value of the MMIO register.
1761  */
1762 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1763 {
1764     struct amdgpu_device *adev = drm_to_adev(info->dev);
1765     uint32_t r;
1766 
1767     r = RREG32(reg);
1768     return r;
1769 }
1770 
1771 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1772                          struct device_attribute *attr,
1773                          char *buf)
1774 {
1775     struct drm_device *ddev = dev_get_drvdata(dev);
1776     struct amdgpu_device *adev = drm_to_adev(ddev);
1777     struct atom_context *ctx = adev->mode_info.atom_context;
1778 
1779     return sysfs_emit(buf, "%s\n", ctx->vbios_version);
1780 }
1781 
1782 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1783            NULL);
1784 
1785 static struct attribute *amdgpu_vbios_version_attrs[] = {
1786     &dev_attr_vbios_version.attr,
1787     NULL
1788 };
1789 
1790 const struct attribute_group amdgpu_vbios_version_attr_group = {
1791     .attrs = amdgpu_vbios_version_attrs
1792 };
1793 
1794 /**
1795  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1796  *
1797  * @adev: amdgpu_device pointer
1798  *
1799  * Frees the driver info and register access callbacks for the ATOM
1800  * interpreter (r4xx+).
1801  * Called at driver shutdown.
1802  */
1803 void amdgpu_atombios_fini(struct amdgpu_device *adev)
1804 {
1805     if (adev->mode_info.atom_context) {
1806         kfree(adev->mode_info.atom_context->scratch);
1807         kfree(adev->mode_info.atom_context->iio);
1808     }
1809     kfree(adev->mode_info.atom_context);
1810     adev->mode_info.atom_context = NULL;
1811     kfree(adev->mode_info.atom_card_info);
1812     adev->mode_info.atom_card_info = NULL;
1813 }
1814 
1815 /**
1816  * amdgpu_atombios_init - init the driver info and callbacks for atombios
1817  *
1818  * @adev: amdgpu_device pointer
1819  *
1820  * Initializes the driver info and register access callbacks for the
1821  * ATOM interpreter (r4xx+).
1822  * Returns 0 on sucess, -ENOMEM on failure.
1823  * Called at driver startup.
1824  */
1825 int amdgpu_atombios_init(struct amdgpu_device *adev)
1826 {
1827     struct card_info *atom_card_info =
1828         kzalloc(sizeof(struct card_info), GFP_KERNEL);
1829 
1830     if (!atom_card_info)
1831         return -ENOMEM;
1832 
1833     adev->mode_info.atom_card_info = atom_card_info;
1834     atom_card_info->dev = adev_to_drm(adev);
1835     atom_card_info->reg_read = cail_reg_read;
1836     atom_card_info->reg_write = cail_reg_write;
1837     atom_card_info->mc_read = cail_mc_read;
1838     atom_card_info->mc_write = cail_mc_write;
1839     atom_card_info->pll_read = cail_pll_read;
1840     atom_card_info->pll_write = cail_pll_write;
1841 
1842     adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1843     if (!adev->mode_info.atom_context) {
1844         amdgpu_atombios_fini(adev);
1845         return -ENOMEM;
1846     }
1847 
1848     mutex_init(&adev->mode_info.atom_context->mutex);
1849     if (adev->is_atom_fw) {
1850         amdgpu_atomfirmware_scratch_regs_init(adev);
1851         amdgpu_atomfirmware_allocate_fb_scratch(adev);
1852         /* cached firmware_flags for further usage */
1853         adev->mode_info.firmware_flags =
1854             amdgpu_atomfirmware_query_firmware_capability(adev);
1855     } else {
1856         amdgpu_atombios_scratch_regs_init(adev);
1857         amdgpu_atombios_allocate_fb_scratch(adev);
1858     }
1859 
1860     return 0;
1861 }
1862 
1863 int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
1864                    uint32_t table,
1865                    uint16_t *size,
1866                    uint8_t *frev,
1867                    uint8_t *crev,
1868                    uint8_t **addr)
1869 {
1870     uint16_t data_start;
1871 
1872     if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
1873                        size, frev, crev, &data_start))
1874         return -EINVAL;
1875 
1876     *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
1877 
1878     return 0;
1879 }
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