amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023
0024
0025 void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
0026         uint32_t sh_mem_config,
0027         uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
0028         uint32_t sh_mem_bases);
0029 int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
0030         unsigned int vmid);
0031 int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id);
0032 int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
0033             uint32_t queue_id, uint32_t __user *wptr,
0034             uint32_t wptr_shift, uint32_t wptr_mask,
0035             struct mm_struct *mm);
0036 int kgd_gfx_v9_hiq_mqd_load(struct amdgpu_device *adev, void *mqd,
0037                 uint32_t pipe_id, uint32_t queue_id,
0038                 uint32_t doorbell_off);
0039 int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev,
0040             uint32_t pipe_id, uint32_t queue_id,
0041             uint32_t (**dump)[2], uint32_t *n_regs);
0042 bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
0043             uint64_t queue_address, uint32_t pipe_id,
0044             uint32_t queue_id);
0045 int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
0046                 enum kfd_preempt_type reset_type,
0047                 unsigned int utimeout, uint32_t pipe_id,
0048                 uint32_t queue_id);
0049 int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
0050                     uint32_t gfx_index_val,
0051                     uint32_t sq_cmd);
0052 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
0053                     uint8_t vmid, uint16_t *p_pasid);
0054
0055 void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,
0056             uint32_t vmid, uint64_t page_table_base);
0057 void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
0058         int *pasid_wave_cnt, int *max_waves_per_cu);
0059 void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
0060         uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr);