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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  * Copyright 2008 Red Hat Inc.
0004  * Copyright 2009 Jerome Glisse.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0019  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0022  * OTHER DEALINGS IN THE SOFTWARE.
0023  *
0024  * Authors: Dave Airlie
0025  *          Alex Deucher
0026  *          Jerome Glisse
0027  */
0028 #ifndef __AMDGPU_H__
0029 #define __AMDGPU_H__
0030 
0031 #ifdef pr_fmt
0032 #undef pr_fmt
0033 #endif
0034 
0035 #define pr_fmt(fmt) "amdgpu: " fmt
0036 
0037 #ifdef dev_fmt
0038 #undef dev_fmt
0039 #endif
0040 
0041 #define dev_fmt(fmt) "amdgpu: " fmt
0042 
0043 #include "amdgpu_ctx.h"
0044 
0045 #include <linux/atomic.h>
0046 #include <linux/wait.h>
0047 #include <linux/list.h>
0048 #include <linux/kref.h>
0049 #include <linux/rbtree.h>
0050 #include <linux/hashtable.h>
0051 #include <linux/dma-fence.h>
0052 #include <linux/pci.h>
0053 #include <linux/aer.h>
0054 
0055 #include <drm/ttm/ttm_bo_api.h>
0056 #include <drm/ttm/ttm_bo_driver.h>
0057 #include <drm/ttm/ttm_placement.h>
0058 #include <drm/ttm/ttm_execbuf_util.h>
0059 
0060 #include <drm/amdgpu_drm.h>
0061 #include <drm/drm_gem.h>
0062 #include <drm/drm_ioctl.h>
0063 
0064 #include <kgd_kfd_interface.h>
0065 #include "dm_pp_interface.h"
0066 #include "kgd_pp_interface.h"
0067 
0068 #include "amd_shared.h"
0069 #include "amdgpu_mode.h"
0070 #include "amdgpu_ih.h"
0071 #include "amdgpu_irq.h"
0072 #include "amdgpu_ucode.h"
0073 #include "amdgpu_ttm.h"
0074 #include "amdgpu_psp.h"
0075 #include "amdgpu_gds.h"
0076 #include "amdgpu_sync.h"
0077 #include "amdgpu_ring.h"
0078 #include "amdgpu_vm.h"
0079 #include "amdgpu_dpm.h"
0080 #include "amdgpu_acp.h"
0081 #include "amdgpu_uvd.h"
0082 #include "amdgpu_vce.h"
0083 #include "amdgpu_vcn.h"
0084 #include "amdgpu_jpeg.h"
0085 #include "amdgpu_mn.h"
0086 #include "amdgpu_gmc.h"
0087 #include "amdgpu_gfx.h"
0088 #include "amdgpu_sdma.h"
0089 #include "amdgpu_lsdma.h"
0090 #include "amdgpu_nbio.h"
0091 #include "amdgpu_hdp.h"
0092 #include "amdgpu_dm.h"
0093 #include "amdgpu_virt.h"
0094 #include "amdgpu_csa.h"
0095 #include "amdgpu_mes_ctx.h"
0096 #include "amdgpu_gart.h"
0097 #include "amdgpu_debugfs.h"
0098 #include "amdgpu_job.h"
0099 #include "amdgpu_bo_list.h"
0100 #include "amdgpu_gem.h"
0101 #include "amdgpu_doorbell.h"
0102 #include "amdgpu_amdkfd.h"
0103 #include "amdgpu_discovery.h"
0104 #include "amdgpu_mes.h"
0105 #include "amdgpu_umc.h"
0106 #include "amdgpu_mmhub.h"
0107 #include "amdgpu_gfxhub.h"
0108 #include "amdgpu_df.h"
0109 #include "amdgpu_smuio.h"
0110 #include "amdgpu_fdinfo.h"
0111 #include "amdgpu_mca.h"
0112 #include "amdgpu_ras.h"
0113 
0114 #define MAX_GPU_INSTANCE        16
0115 
0116 struct amdgpu_gpu_instance
0117 {
0118     struct amdgpu_device        *adev;
0119     int             mgpu_fan_enabled;
0120 };
0121 
0122 struct amdgpu_mgpu_info
0123 {
0124     struct amdgpu_gpu_instance  gpu_ins[MAX_GPU_INSTANCE];
0125     struct mutex            mutex;
0126     uint32_t            num_gpu;
0127     uint32_t            num_dgpu;
0128     uint32_t            num_apu;
0129 
0130     /* delayed reset_func for XGMI configuration if necessary */
0131     struct delayed_work     delayed_reset_work;
0132     bool                pending_reset;
0133 };
0134 
0135 enum amdgpu_ss {
0136     AMDGPU_SS_DRV_LOAD,
0137     AMDGPU_SS_DEV_D0,
0138     AMDGPU_SS_DEV_D3,
0139     AMDGPU_SS_DRV_UNLOAD
0140 };
0141 
0142 struct amdgpu_watchdog_timer
0143 {
0144     bool timeout_fatal_disable;
0145     uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
0146 };
0147 
0148 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
0149 
0150 /*
0151  * Modules parameters.
0152  */
0153 extern int amdgpu_modeset;
0154 extern int amdgpu_vram_limit;
0155 extern int amdgpu_vis_vram_limit;
0156 extern int amdgpu_gart_size;
0157 extern int amdgpu_gtt_size;
0158 extern int amdgpu_moverate;
0159 extern int amdgpu_audio;
0160 extern int amdgpu_disp_priority;
0161 extern int amdgpu_hw_i2c;
0162 extern int amdgpu_pcie_gen2;
0163 extern int amdgpu_msi;
0164 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
0165 extern int amdgpu_dpm;
0166 extern int amdgpu_fw_load_type;
0167 extern int amdgpu_aspm;
0168 extern int amdgpu_runtime_pm;
0169 extern uint amdgpu_ip_block_mask;
0170 extern int amdgpu_bapm;
0171 extern int amdgpu_deep_color;
0172 extern int amdgpu_vm_size;
0173 extern int amdgpu_vm_block_size;
0174 extern int amdgpu_vm_fragment_size;
0175 extern int amdgpu_vm_fault_stop;
0176 extern int amdgpu_vm_debug;
0177 extern int amdgpu_vm_update_mode;
0178 extern int amdgpu_exp_hw_support;
0179 extern int amdgpu_dc;
0180 extern int amdgpu_sched_jobs;
0181 extern int amdgpu_sched_hw_submission;
0182 extern uint amdgpu_pcie_gen_cap;
0183 extern uint amdgpu_pcie_lane_cap;
0184 extern u64 amdgpu_cg_mask;
0185 extern uint amdgpu_pg_mask;
0186 extern uint amdgpu_sdma_phase_quantum;
0187 extern char *amdgpu_disable_cu;
0188 extern char *amdgpu_virtual_display;
0189 extern uint amdgpu_pp_feature_mask;
0190 extern uint amdgpu_force_long_training;
0191 extern int amdgpu_job_hang_limit;
0192 extern int amdgpu_lbpw;
0193 extern int amdgpu_compute_multipipe;
0194 extern int amdgpu_gpu_recovery;
0195 extern int amdgpu_emu_mode;
0196 extern uint amdgpu_smu_memory_pool_size;
0197 extern int amdgpu_smu_pptable_id;
0198 extern uint amdgpu_dc_feature_mask;
0199 extern uint amdgpu_dc_debug_mask;
0200 extern uint amdgpu_dc_visual_confirm;
0201 extern uint amdgpu_dm_abm_level;
0202 extern int amdgpu_backlight;
0203 extern struct amdgpu_mgpu_info mgpu_info;
0204 extern int amdgpu_ras_enable;
0205 extern uint amdgpu_ras_mask;
0206 extern int amdgpu_bad_page_threshold;
0207 extern bool amdgpu_ignore_bad_page_threshold;
0208 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
0209 extern int amdgpu_async_gfx_ring;
0210 extern int amdgpu_mcbp;
0211 extern int amdgpu_discovery;
0212 extern int amdgpu_mes;
0213 extern int amdgpu_mes_kiq;
0214 extern int amdgpu_noretry;
0215 extern int amdgpu_force_asic_type;
0216 extern int amdgpu_smartshift_bias;
0217 extern int amdgpu_use_xgmi_p2p;
0218 #ifdef CONFIG_HSA_AMD
0219 extern int sched_policy;
0220 extern bool debug_evictions;
0221 extern bool no_system_mem_limit;
0222 #else
0223 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
0224 static const bool __maybe_unused debug_evictions; /* = false */
0225 static const bool __maybe_unused no_system_mem_limit;
0226 #endif
0227 #ifdef CONFIG_HSA_AMD_P2P
0228 extern bool pcie_p2p;
0229 #endif
0230 
0231 extern int amdgpu_tmz;
0232 extern int amdgpu_reset_method;
0233 
0234 #ifdef CONFIG_DRM_AMDGPU_SI
0235 extern int amdgpu_si_support;
0236 #endif
0237 #ifdef CONFIG_DRM_AMDGPU_CIK
0238 extern int amdgpu_cik_support;
0239 #endif
0240 extern int amdgpu_num_kcq;
0241 
0242 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
0243 extern int amdgpu_vcnfw_log;
0244 
0245 #define AMDGPU_VM_MAX_NUM_CTX           4096
0246 #define AMDGPU_SG_THRESHOLD         (256*1024*1024)
0247 #define AMDGPU_DEFAULT_GTT_SIZE_MB      3072ULL /* 3GB by default */
0248 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS          3000
0249 #define AMDGPU_MAX_USEC_TIMEOUT         100000  /* 100 ms */
0250 #define AMDGPU_FENCE_JIFFIES_TIMEOUT        (HZ / 2)
0251 #define AMDGPU_DEBUGFS_MAX_COMPONENTS       32
0252 #define AMDGPUFB_CONN_LIMIT         4
0253 #define AMDGPU_BIOS_NUM_SCRATCH         16
0254 
0255 #define AMDGPU_VBIOS_VGA_ALLOCATION     (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
0256 
0257 /* hard reset data */
0258 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
0259 
0260 /* reset flags */
0261 #define AMDGPU_RESET_GFX            (1 << 0)
0262 #define AMDGPU_RESET_COMPUTE            (1 << 1)
0263 #define AMDGPU_RESET_DMA            (1 << 2)
0264 #define AMDGPU_RESET_CP             (1 << 3)
0265 #define AMDGPU_RESET_GRBM           (1 << 4)
0266 #define AMDGPU_RESET_DMA1           (1 << 5)
0267 #define AMDGPU_RESET_RLC            (1 << 6)
0268 #define AMDGPU_RESET_SEM            (1 << 7)
0269 #define AMDGPU_RESET_IH             (1 << 8)
0270 #define AMDGPU_RESET_VMC            (1 << 9)
0271 #define AMDGPU_RESET_MC             (1 << 10)
0272 #define AMDGPU_RESET_DISPLAY            (1 << 11)
0273 #define AMDGPU_RESET_UVD            (1 << 12)
0274 #define AMDGPU_RESET_VCE            (1 << 13)
0275 #define AMDGPU_RESET_VCE1           (1 << 14)
0276 
0277 /* max cursor sizes (in pixels) */
0278 #define CIK_CURSOR_WIDTH 128
0279 #define CIK_CURSOR_HEIGHT 128
0280 
0281 /* smart shift bias level limits */
0282 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
0283 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
0284 
0285 struct amdgpu_device;
0286 struct amdgpu_irq_src;
0287 struct amdgpu_fpriv;
0288 struct amdgpu_bo_va_mapping;
0289 struct kfd_vm_fault_info;
0290 struct amdgpu_hive_info;
0291 struct amdgpu_reset_context;
0292 struct amdgpu_reset_control;
0293 
0294 enum amdgpu_cp_irq {
0295     AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
0296     AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
0297     AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
0298     AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
0299     AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
0300     AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
0301     AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
0302     AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
0303     AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
0304     AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
0305 
0306     AMDGPU_CP_IRQ_LAST
0307 };
0308 
0309 enum amdgpu_thermal_irq {
0310     AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
0311     AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
0312 
0313     AMDGPU_THERMAL_IRQ_LAST
0314 };
0315 
0316 enum amdgpu_kiq_irq {
0317     AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
0318     AMDGPU_CP_KIQ_IRQ_LAST
0319 };
0320 #define SRIOV_USEC_TIMEOUT  1200000 /* wait 12 * 100ms for SRIOV */
0321 #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
0322 #define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
0323 #define MAX_KIQ_REG_TRY 1000
0324 
0325 int amdgpu_device_ip_set_clockgating_state(void *dev,
0326                        enum amd_ip_block_type block_type,
0327                        enum amd_clockgating_state state);
0328 int amdgpu_device_ip_set_powergating_state(void *dev,
0329                        enum amd_ip_block_type block_type,
0330                        enum amd_powergating_state state);
0331 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
0332                         u64 *flags);
0333 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
0334                    enum amd_ip_block_type block_type);
0335 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
0336                   enum amd_ip_block_type block_type);
0337 
0338 #define AMDGPU_MAX_IP_NUM 16
0339 
0340 struct amdgpu_ip_block_status {
0341     bool valid;
0342     bool sw;
0343     bool hw;
0344     bool late_initialized;
0345     bool hang;
0346 };
0347 
0348 struct amdgpu_ip_block_version {
0349     const enum amd_ip_block_type type;
0350     const u32 major;
0351     const u32 minor;
0352     const u32 rev;
0353     const struct amd_ip_funcs *funcs;
0354 };
0355 
0356 #define HW_REV(_Major, _Minor, _Rev) \
0357     ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
0358 
0359 struct amdgpu_ip_block {
0360     struct amdgpu_ip_block_status status;
0361     const struct amdgpu_ip_block_version *version;
0362 };
0363 
0364 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
0365                        enum amd_ip_block_type type,
0366                        u32 major, u32 minor);
0367 
0368 struct amdgpu_ip_block *
0369 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
0370                   enum amd_ip_block_type type);
0371 
0372 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
0373                    const struct amdgpu_ip_block_version *ip_block_version);
0374 
0375 /*
0376  * BIOS.
0377  */
0378 bool amdgpu_get_bios(struct amdgpu_device *adev);
0379 bool amdgpu_read_bios(struct amdgpu_device *adev);
0380 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
0381                      u8 *bios, u32 length_bytes);
0382 /*
0383  * Clocks
0384  */
0385 
0386 #define AMDGPU_MAX_PPLL 3
0387 
0388 struct amdgpu_clock {
0389     struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
0390     struct amdgpu_pll spll;
0391     struct amdgpu_pll mpll;
0392     /* 10 Khz units */
0393     uint32_t default_mclk;
0394     uint32_t default_sclk;
0395     uint32_t default_dispclk;
0396     uint32_t current_dispclk;
0397     uint32_t dp_extclk;
0398     uint32_t max_pixel_clock;
0399 };
0400 
0401 /* sub-allocation manager, it has to be protected by another lock.
0402  * By conception this is an helper for other part of the driver
0403  * like the indirect buffer or semaphore, which both have their
0404  * locking.
0405  *
0406  * Principe is simple, we keep a list of sub allocation in offset
0407  * order (first entry has offset == 0, last entry has the highest
0408  * offset).
0409  *
0410  * When allocating new object we first check if there is room at
0411  * the end total_size - (last_object_offset + last_object_size) >=
0412  * alloc_size. If so we allocate new object there.
0413  *
0414  * When there is not enough room at the end, we start waiting for
0415  * each sub object until we reach object_offset+object_size >=
0416  * alloc_size, this object then become the sub object we return.
0417  *
0418  * Alignment can't be bigger than page size.
0419  *
0420  * Hole are not considered for allocation to keep things simple.
0421  * Assumption is that there won't be hole (all object on same
0422  * alignment).
0423  */
0424 
0425 #define AMDGPU_SA_NUM_FENCE_LISTS   32
0426 
0427 struct amdgpu_sa_manager {
0428     wait_queue_head_t   wq;
0429     struct amdgpu_bo    *bo;
0430     struct list_head    *hole;
0431     struct list_head    flist[AMDGPU_SA_NUM_FENCE_LISTS];
0432     struct list_head    olist;
0433     unsigned        size;
0434     uint64_t        gpu_addr;
0435     void            *cpu_ptr;
0436     uint32_t        domain;
0437     uint32_t        align;
0438 };
0439 
0440 /* sub-allocation buffer */
0441 struct amdgpu_sa_bo {
0442     struct list_head        olist;
0443     struct list_head        flist;
0444     struct amdgpu_sa_manager    *manager;
0445     unsigned            soffset;
0446     unsigned            eoffset;
0447     struct dma_fence            *fence;
0448 };
0449 
0450 int amdgpu_fence_slab_init(void);
0451 void amdgpu_fence_slab_fini(void);
0452 
0453 /*
0454  * IRQS.
0455  */
0456 
0457 struct amdgpu_flip_work {
0458     struct delayed_work     flip_work;
0459     struct work_struct      unpin_work;
0460     struct amdgpu_device        *adev;
0461     int             crtc_id;
0462     u32             target_vblank;
0463     uint64_t            base;
0464     struct drm_pending_vblank_event *event;
0465     struct amdgpu_bo        *old_abo;
0466     unsigned            shared_count;
0467     struct dma_fence        **shared;
0468     struct dma_fence_cb     cb;
0469     bool                async;
0470 };
0471 
0472 
0473 /*
0474  * file private structure
0475  */
0476 
0477 struct amdgpu_fpriv {
0478     struct amdgpu_vm    vm;
0479     struct amdgpu_bo_va *prt_va;
0480     struct amdgpu_bo_va *csa_va;
0481     struct mutex        bo_list_lock;
0482     struct idr      bo_list_handles;
0483     struct amdgpu_ctx_mgr   ctx_mgr;
0484 };
0485 
0486 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
0487 
0488 /*
0489  * Writeback
0490  */
0491 #define AMDGPU_MAX_WB 256   /* Reserve at most 256 WB slots for amdgpu-owned rings. */
0492 
0493 struct amdgpu_wb {
0494     struct amdgpu_bo    *wb_obj;
0495     volatile uint32_t   *wb;
0496     uint64_t        gpu_addr;
0497     u32         num_wb; /* Number of wb slots actually reserved for amdgpu. */
0498     unsigned long       used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
0499 };
0500 
0501 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
0502 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
0503 
0504 /*
0505  * Benchmarking
0506  */
0507 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
0508 
0509 /*
0510  * ASIC specific register table accessible by UMD
0511  */
0512 struct amdgpu_allowed_register_entry {
0513     uint32_t reg_offset;
0514     bool grbm_indexed;
0515 };
0516 
0517 enum amd_reset_method {
0518     AMD_RESET_METHOD_NONE = -1,
0519     AMD_RESET_METHOD_LEGACY = 0,
0520     AMD_RESET_METHOD_MODE0,
0521     AMD_RESET_METHOD_MODE1,
0522     AMD_RESET_METHOD_MODE2,
0523     AMD_RESET_METHOD_BACO,
0524     AMD_RESET_METHOD_PCI,
0525 };
0526 
0527 struct amdgpu_video_codec_info {
0528     u32 codec_type;
0529     u32 max_width;
0530     u32 max_height;
0531     u32 max_pixels_per_frame;
0532     u32 max_level;
0533 };
0534 
0535 #define codec_info_build(type, width, height, level) \
0536              .codec_type = type,\
0537              .max_width = width,\
0538              .max_height = height,\
0539              .max_pixels_per_frame = height * width,\
0540              .max_level = level,
0541 
0542 struct amdgpu_video_codecs {
0543     const u32 codec_count;
0544     const struct amdgpu_video_codec_info *codec_array;
0545 };
0546 
0547 /*
0548  * ASIC specific functions.
0549  */
0550 struct amdgpu_asic_funcs {
0551     bool (*read_disabled_bios)(struct amdgpu_device *adev);
0552     bool (*read_bios_from_rom)(struct amdgpu_device *adev,
0553                    u8 *bios, u32 length_bytes);
0554     int (*read_register)(struct amdgpu_device *adev, u32 se_num,
0555                  u32 sh_num, u32 reg_offset, u32 *value);
0556     void (*set_vga_state)(struct amdgpu_device *adev, bool state);
0557     int (*reset)(struct amdgpu_device *adev);
0558     enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
0559     /* get the reference clock */
0560     u32 (*get_xclk)(struct amdgpu_device *adev);
0561     /* MM block clocks */
0562     int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
0563     int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
0564     /* static power management */
0565     int (*get_pcie_lanes)(struct amdgpu_device *adev);
0566     void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
0567     /* get config memsize register */
0568     u32 (*get_config_memsize)(struct amdgpu_device *adev);
0569     /* flush hdp write queue */
0570     void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
0571     /* invalidate hdp read cache */
0572     void (*invalidate_hdp)(struct amdgpu_device *adev,
0573                    struct amdgpu_ring *ring);
0574     /* check if the asic needs a full reset of if soft reset will work */
0575     bool (*need_full_reset)(struct amdgpu_device *adev);
0576     /* initialize doorbell layout for specific asic*/
0577     void (*init_doorbell_index)(struct amdgpu_device *adev);
0578     /* PCIe bandwidth usage */
0579     void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
0580                    uint64_t *count1);
0581     /* do we need to reset the asic at init time (e.g., kexec) */
0582     bool (*need_reset_on_init)(struct amdgpu_device *adev);
0583     /* PCIe replay counter */
0584     uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
0585     /* device supports BACO */
0586     bool (*supports_baco)(struct amdgpu_device *adev);
0587     /* pre asic_init quirks */
0588     void (*pre_asic_init)(struct amdgpu_device *adev);
0589     /* enter/exit umd stable pstate */
0590     int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
0591     /* query video codecs */
0592     int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
0593                   const struct amdgpu_video_codecs **codecs);
0594 };
0595 
0596 /*
0597  * IOCTL.
0598  */
0599 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
0600                 struct drm_file *filp);
0601 
0602 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
0603 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
0604                     struct drm_file *filp);
0605 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
0606 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
0607                 struct drm_file *filp);
0608 
0609 /* VRAM scratch page for HDP bug, default vram page */
0610 struct amdgpu_vram_scratch {
0611     struct amdgpu_bo        *robj;
0612     volatile uint32_t       *ptr;
0613     u64             gpu_addr;
0614 };
0615 
0616 /*
0617  * CGS
0618  */
0619 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
0620 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
0621 
0622 /*
0623  * Core structure, functions and helpers.
0624  */
0625 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
0626 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
0627 
0628 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
0629 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
0630 
0631 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
0632 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
0633 
0634 struct amdgpu_mmio_remap {
0635     u32 reg_offset;
0636     resource_size_t bus_addr;
0637 };
0638 
0639 /* Define the HW IP blocks will be used in driver , add more if necessary */
0640 enum amd_hw_ip_block_type {
0641     GC_HWIP = 1,
0642     HDP_HWIP,
0643     SDMA0_HWIP,
0644     SDMA1_HWIP,
0645     SDMA2_HWIP,
0646     SDMA3_HWIP,
0647     SDMA4_HWIP,
0648     SDMA5_HWIP,
0649     SDMA6_HWIP,
0650     SDMA7_HWIP,
0651     LSDMA_HWIP,
0652     MMHUB_HWIP,
0653     ATHUB_HWIP,
0654     NBIO_HWIP,
0655     MP0_HWIP,
0656     MP1_HWIP,
0657     UVD_HWIP,
0658     VCN_HWIP = UVD_HWIP,
0659     JPEG_HWIP = VCN_HWIP,
0660     VCN1_HWIP,
0661     VCE_HWIP,
0662     DF_HWIP,
0663     DCE_HWIP,
0664     OSSSYS_HWIP,
0665     SMUIO_HWIP,
0666     PWR_HWIP,
0667     NBIF_HWIP,
0668     THM_HWIP,
0669     CLK_HWIP,
0670     UMC_HWIP,
0671     RSMU_HWIP,
0672     XGMI_HWIP,
0673     DCI_HWIP,
0674     PCIE_HWIP,
0675     MAX_HWIP
0676 };
0677 
0678 #define HWIP_MAX_INSTANCE   11
0679 
0680 #define HW_ID_MAX       300
0681 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
0682 #define IP_VERSION_MAJ(ver) ((ver) >> 16)
0683 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
0684 #define IP_VERSION_REV(ver) ((ver) & 0xFF)
0685 
0686 struct amd_powerplay {
0687     void *pp_handle;
0688     const struct amd_pm_funcs *pp_funcs;
0689 };
0690 
0691 struct ip_discovery_top;
0692 
0693 /* polaris10 kickers */
0694 #define ASICID_IS_P20(did, rid)     (((did == 0x67DF) && \
0695                      ((rid == 0xE3) || \
0696                       (rid == 0xE4) || \
0697                       (rid == 0xE5) || \
0698                       (rid == 0xE7) || \
0699                       (rid == 0xEF))) || \
0700                      ((did == 0x6FDF) && \
0701                      ((rid == 0xE7) || \
0702                       (rid == 0xEF) || \
0703                       (rid == 0xFF))))
0704 
0705 #define ASICID_IS_P30(did, rid)     ((did == 0x67DF) && \
0706                     ((rid == 0xE1) || \
0707                      (rid == 0xF7)))
0708 
0709 /* polaris11 kickers */
0710 #define ASICID_IS_P21(did, rid)     (((did == 0x67EF) && \
0711                      ((rid == 0xE0) || \
0712                       (rid == 0xE5))) || \
0713                      ((did == 0x67FF) && \
0714                      ((rid == 0xCF) || \
0715                       (rid == 0xEF) || \
0716                       (rid == 0xFF))))
0717 
0718 #define ASICID_IS_P31(did, rid)     ((did == 0x67EF) && \
0719                     ((rid == 0xE2)))
0720 
0721 /* polaris12 kickers */
0722 #define ASICID_IS_P23(did, rid)     (((did == 0x6987) && \
0723                      ((rid == 0xC0) || \
0724                       (rid == 0xC1) || \
0725                       (rid == 0xC3) || \
0726                       (rid == 0xC7))) || \
0727                      ((did == 0x6981) && \
0728                      ((rid == 0x00) || \
0729                       (rid == 0x01) || \
0730                       (rid == 0x10))))
0731 
0732 struct amdgpu_mqd_prop {
0733     uint64_t mqd_gpu_addr;
0734     uint64_t hqd_base_gpu_addr;
0735     uint64_t rptr_gpu_addr;
0736     uint64_t wptr_gpu_addr;
0737     uint32_t queue_size;
0738     bool use_doorbell;
0739     uint32_t doorbell_index;
0740     uint64_t eop_gpu_addr;
0741     uint32_t hqd_pipe_priority;
0742     uint32_t hqd_queue_priority;
0743     bool hqd_active;
0744 };
0745 
0746 struct amdgpu_mqd {
0747     unsigned mqd_size;
0748     int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
0749             struct amdgpu_mqd_prop *p);
0750 };
0751 
0752 #define AMDGPU_RESET_MAGIC_NUM 64
0753 #define AMDGPU_MAX_DF_PERFMONS 4
0754 #define AMDGPU_PRODUCT_NAME_LEN 64
0755 struct amdgpu_reset_domain;
0756 
0757 struct amdgpu_device {
0758     struct device           *dev;
0759     struct pci_dev          *pdev;
0760     struct drm_device       ddev;
0761 
0762 #ifdef CONFIG_DRM_AMD_ACP
0763     struct amdgpu_acp       acp;
0764 #endif
0765     struct amdgpu_hive_info *hive;
0766     /* ASIC */
0767     enum amd_asic_type      asic_type;
0768     uint32_t            family;
0769     uint32_t            rev_id;
0770     uint32_t            external_rev_id;
0771     unsigned long           flags;
0772     unsigned long           apu_flags;
0773     int             usec_timeout;
0774     const struct amdgpu_asic_funcs  *asic_funcs;
0775     bool                shutdown;
0776     bool                need_swiotlb;
0777     bool                accel_working;
0778     struct notifier_block       acpi_nb;
0779     struct amdgpu_i2c_chan      *i2c_bus[AMDGPU_MAX_I2C_BUS];
0780     struct debugfs_blob_wrapper     debugfs_vbios_blob;
0781     struct debugfs_blob_wrapper     debugfs_discovery_blob;
0782     struct mutex            srbm_mutex;
0783     /* GRBM index mutex. Protects concurrent access to GRBM index */
0784     struct mutex                    grbm_idx_mutex;
0785     struct dev_pm_domain        vga_pm_domain;
0786     bool                have_disp_power_ref;
0787     bool                            have_atomics_support;
0788 
0789     /* BIOS */
0790     bool                is_atom_fw;
0791     uint8_t             *bios;
0792     uint32_t            bios_size;
0793     uint32_t            bios_scratch_reg_offset;
0794     uint32_t            bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
0795 
0796     /* Register/doorbell mmio */
0797     resource_size_t         rmmio_base;
0798     resource_size_t         rmmio_size;
0799     void __iomem            *rmmio;
0800     /* protects concurrent MM_INDEX/DATA based register access */
0801     spinlock_t mmio_idx_lock;
0802     struct amdgpu_mmio_remap        rmmio_remap;
0803     /* protects concurrent SMC based register access */
0804     spinlock_t smc_idx_lock;
0805     amdgpu_rreg_t           smc_rreg;
0806     amdgpu_wreg_t           smc_wreg;
0807     /* protects concurrent PCIE register access */
0808     spinlock_t pcie_idx_lock;
0809     amdgpu_rreg_t           pcie_rreg;
0810     amdgpu_wreg_t           pcie_wreg;
0811     amdgpu_rreg_t           pciep_rreg;
0812     amdgpu_wreg_t           pciep_wreg;
0813     amdgpu_rreg64_t         pcie_rreg64;
0814     amdgpu_wreg64_t         pcie_wreg64;
0815     /* protects concurrent UVD register access */
0816     spinlock_t uvd_ctx_idx_lock;
0817     amdgpu_rreg_t           uvd_ctx_rreg;
0818     amdgpu_wreg_t           uvd_ctx_wreg;
0819     /* protects concurrent DIDT register access */
0820     spinlock_t didt_idx_lock;
0821     amdgpu_rreg_t           didt_rreg;
0822     amdgpu_wreg_t           didt_wreg;
0823     /* protects concurrent gc_cac register access */
0824     spinlock_t gc_cac_idx_lock;
0825     amdgpu_rreg_t           gc_cac_rreg;
0826     amdgpu_wreg_t           gc_cac_wreg;
0827     /* protects concurrent se_cac register access */
0828     spinlock_t se_cac_idx_lock;
0829     amdgpu_rreg_t           se_cac_rreg;
0830     amdgpu_wreg_t           se_cac_wreg;
0831     /* protects concurrent ENDPOINT (audio) register access */
0832     spinlock_t audio_endpt_idx_lock;
0833     amdgpu_block_rreg_t     audio_endpt_rreg;
0834     amdgpu_block_wreg_t     audio_endpt_wreg;
0835     struct amdgpu_doorbell      doorbell;
0836 
0837     /* clock/pll info */
0838     struct amdgpu_clock            clock;
0839 
0840     /* MC */
0841     struct amdgpu_gmc       gmc;
0842     struct amdgpu_gart      gart;
0843     dma_addr_t          dummy_page_addr;
0844     struct amdgpu_vm_manager    vm_manager;
0845     struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
0846     unsigned            num_vmhubs;
0847 
0848     /* memory management */
0849     struct amdgpu_mman      mman;
0850     struct amdgpu_vram_scratch  vram_scratch;
0851     struct amdgpu_wb        wb;
0852     atomic64_t          num_bytes_moved;
0853     atomic64_t          num_evictions;
0854     atomic64_t          num_vram_cpu_page_faults;
0855     atomic_t            gpu_reset_counter;
0856     atomic_t            vram_lost_counter;
0857 
0858     /* data for buffer migration throttling */
0859     struct {
0860         spinlock_t      lock;
0861         s64         last_update_us;
0862         s64         accum_us; /* accumulated microseconds */
0863         s64         accum_us_vis; /* for visible VRAM */
0864         u32         log2_max_MBps;
0865     } mm_stats;
0866 
0867     /* display */
0868     bool                enable_virtual_display;
0869     struct amdgpu_vkms_output       *amdgpu_vkms_output;
0870     struct amdgpu_mode_info     mode_info;
0871     /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
0872     struct work_struct      hotplug_work;
0873     struct amdgpu_irq_src       crtc_irq;
0874     struct amdgpu_irq_src       vline0_irq;
0875     struct amdgpu_irq_src       vupdate_irq;
0876     struct amdgpu_irq_src       pageflip_irq;
0877     struct amdgpu_irq_src       hpd_irq;
0878     struct amdgpu_irq_src       dmub_trace_irq;
0879     struct amdgpu_irq_src       dmub_outbox_irq;
0880 
0881     /* rings */
0882     u64             fence_context;
0883     unsigned            num_rings;
0884     struct amdgpu_ring      *rings[AMDGPU_MAX_RINGS];
0885     bool                ib_pool_ready;
0886     struct amdgpu_sa_manager    ib_pools[AMDGPU_IB_POOL_MAX];
0887     struct amdgpu_sched     gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
0888 
0889     /* interrupts */
0890     struct amdgpu_irq       irq;
0891 
0892     /* powerplay */
0893     struct amd_powerplay        powerplay;
0894     struct amdgpu_pm        pm;
0895     u64             cg_flags;
0896     u32             pg_flags;
0897 
0898     /* nbio */
0899     struct amdgpu_nbio      nbio;
0900 
0901     /* hdp */
0902     struct amdgpu_hdp       hdp;
0903 
0904     /* smuio */
0905     struct amdgpu_smuio     smuio;
0906 
0907     /* mmhub */
0908     struct amdgpu_mmhub     mmhub;
0909 
0910     /* gfxhub */
0911     struct amdgpu_gfxhub        gfxhub;
0912 
0913     /* gfx */
0914     struct amdgpu_gfx       gfx;
0915 
0916     /* sdma */
0917     struct amdgpu_sdma      sdma;
0918 
0919     /* lsdma */
0920     struct amdgpu_lsdma     lsdma;
0921 
0922     /* uvd */
0923     struct amdgpu_uvd       uvd;
0924 
0925     /* vce */
0926     struct amdgpu_vce       vce;
0927 
0928     /* vcn */
0929     struct amdgpu_vcn       vcn;
0930 
0931     /* jpeg */
0932     struct amdgpu_jpeg      jpeg;
0933 
0934     /* firmwares */
0935     struct amdgpu_firmware      firmware;
0936 
0937     /* PSP */
0938     struct psp_context      psp;
0939 
0940     /* GDS */
0941     struct amdgpu_gds       gds;
0942 
0943     /* KFD */
0944     struct amdgpu_kfd_dev       kfd;
0945 
0946     /* UMC */
0947     struct amdgpu_umc       umc;
0948 
0949     /* display related functionality */
0950     struct amdgpu_display_manager dm;
0951 
0952     /* mes */
0953     bool                            enable_mes;
0954     bool                            enable_mes_kiq;
0955     struct amdgpu_mes               mes;
0956     struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];
0957 
0958     /* df */
0959     struct amdgpu_df                df;
0960 
0961     /* MCA */
0962     struct amdgpu_mca               mca;
0963 
0964     struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
0965     uint32_t                harvest_ip_mask;
0966     int             num_ip_blocks;
0967     struct mutex    mn_lock;
0968     DECLARE_HASHTABLE(mn_hash, 7);
0969 
0970     /* tracking pinned memory */
0971     atomic64_t vram_pin_size;
0972     atomic64_t visible_pin_size;
0973     atomic64_t gart_pin_size;
0974 
0975     /* soc15 register offset based on ip, instance and  segment */
0976     uint32_t        *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
0977 
0978     /* delayed work_func for deferring clockgating during resume */
0979     struct delayed_work     delayed_init_work;
0980 
0981     struct amdgpu_virt  virt;
0982 
0983     /* link all shadow bo */
0984     struct list_head                shadow_list;
0985     struct mutex                    shadow_list_lock;
0986 
0987     /* record hw reset is performed */
0988     bool has_hw_reset;
0989     u8              reset_magic[AMDGPU_RESET_MAGIC_NUM];
0990 
0991     /* s3/s4 mask */
0992     bool                            in_suspend;
0993     bool                in_s3;
0994     bool                in_s4;
0995     bool                in_s0ix;
0996 
0997     enum pp_mp1_state               mp1_state;
0998     struct amdgpu_doorbell_index doorbell_index;
0999 
1000     struct mutex            notifier_lock;
1001 
1002     int asic_reset_res;
1003     struct work_struct      xgmi_reset_work;
1004     struct list_head        reset_list;
1005 
1006     long                gfx_timeout;
1007     long                sdma_timeout;
1008     long                video_timeout;
1009     long                compute_timeout;
1010 
1011     uint64_t            unique_id;
1012     uint64_t    df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1013 
1014     /* enable runtime pm on the device */
1015     bool                            in_runpm;
1016     bool                            has_pr3;
1017 
1018     bool                            pm_sysfs_en;
1019     bool                            ucode_sysfs_en;
1020     bool                            psp_sysfs_en;
1021 
1022     /* Chip product information */
1023     char                product_number[20];
1024     char                product_name[AMDGPU_PRODUCT_NAME_LEN];
1025     char                serial[20];
1026 
1027     atomic_t            throttling_logging_enabled;
1028     struct ratelimit_state      throttling_logging_rs;
1029     uint32_t                        ras_hw_enabled;
1030     uint32_t                        ras_enabled;
1031 
1032     bool                            no_hw_access;
1033     struct pci_saved_state          *pci_state;
1034     pci_channel_state_t     pci_channel_state;
1035 
1036     struct amdgpu_reset_control     *reset_cntl;
1037     uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1038 
1039     bool                ram_is_direct_mapped;
1040 
1041     struct list_head                ras_list;
1042 
1043     struct ip_discovery_top         *ip_top;
1044 
1045     struct amdgpu_reset_domain  *reset_domain;
1046 
1047     struct mutex            benchmark_mutex;
1048 
1049     /* reset dump register */
1050     uint32_t                        *reset_dump_reg_list;
1051     uint32_t            *reset_dump_reg_value;
1052     int                             num_regs;
1053 #ifdef CONFIG_DEV_COREDUMP
1054     struct amdgpu_task_info         reset_task_info;
1055     bool                            reset_vram_lost;
1056     struct timespec64               reset_time;
1057 #endif
1058 
1059     bool                            scpm_enabled;
1060     uint32_t                        scpm_status;
1061 
1062     struct work_struct      reset_work;
1063 };
1064 
1065 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1066 {
1067     return container_of(ddev, struct amdgpu_device, ddev);
1068 }
1069 
1070 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1071 {
1072     return &adev->ddev;
1073 }
1074 
1075 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1076 {
1077     return container_of(bdev, struct amdgpu_device, mman.bdev);
1078 }
1079 
1080 int amdgpu_device_init(struct amdgpu_device *adev,
1081                uint32_t flags);
1082 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1083 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1084 
1085 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1086 
1087 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1088                  void *buf, size_t size, bool write);
1089 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1090                  void *buf, size_t size, bool write);
1091 
1092 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1093                    void *buf, size_t size, bool write);
1094 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1095                 uint32_t reg, uint32_t acc_flags);
1096 void amdgpu_device_wreg(struct amdgpu_device *adev,
1097             uint32_t reg, uint32_t v,
1098             uint32_t acc_flags);
1099 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1100                  uint32_t reg, uint32_t v);
1101 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1102 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1103 
1104 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1105                 u32 pcie_index, u32 pcie_data,
1106                 u32 reg_addr);
1107 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1108                   u32 pcie_index, u32 pcie_data,
1109                   u32 reg_addr);
1110 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1111                  u32 pcie_index, u32 pcie_data,
1112                  u32 reg_addr, u32 reg_data);
1113 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1114                    u32 pcie_index, u32 pcie_data,
1115                    u32 reg_addr, u64 reg_data);
1116 
1117 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1118 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1119 
1120 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1121                  struct amdgpu_reset_context *reset_context);
1122 
1123 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1124              struct amdgpu_reset_context *reset_context);
1125 
1126 int emu_soc_asic_init(struct amdgpu_device *adev);
1127 
1128 /*
1129  * Registers read & write functions.
1130  */
1131 #define AMDGPU_REGS_NO_KIQ    (1<<1)
1132 #define AMDGPU_REGS_RLC (1<<2)
1133 
1134 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1135 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1136 
1137 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1138 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1139 
1140 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1141 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1142 
1143 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1144 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1145 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1146 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1147 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1148 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1149 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1150 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1151 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1152 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1153 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1154 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1155 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1156 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1157 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1158 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1159 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1160 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1161 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1162 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1163 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1164 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1165 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1166 #define WREG32_P(reg, val, mask)                \
1167     do {                            \
1168         uint32_t tmp_ = RREG32(reg);            \
1169         tmp_ &= (mask);                 \
1170         tmp_ |= ((val) & ~(mask));          \
1171         WREG32(reg, tmp_);              \
1172     } while (0)
1173 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1174 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1175 #define WREG32_PLL_P(reg, val, mask)                \
1176     do {                            \
1177         uint32_t tmp_ = RREG32_PLL(reg);        \
1178         tmp_ &= (mask);                 \
1179         tmp_ |= ((val) & ~(mask));          \
1180         WREG32_PLL(reg, tmp_);              \
1181     } while (0)
1182 
1183 #define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
1184     do {                                                    \
1185         u32 tmp = RREG32_SMC(_Reg);                     \
1186         tmp &= (_Mask);                                 \
1187         tmp |= ((_Val) & ~(_Mask));                     \
1188         WREG32_SMC(_Reg, tmp);                          \
1189     } while (0)
1190 
1191 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1192 
1193 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1194 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1195 
1196 #define REG_SET_FIELD(orig_val, reg, field, field_val)          \
1197     (((orig_val) & ~REG_FIELD_MASK(reg, field)) |           \
1198      (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1199 
1200 #define REG_GET_FIELD(value, reg, field)                \
1201     (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1202 
1203 #define WREG32_FIELD(reg, field, val)   \
1204     WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1205 
1206 #define WREG32_FIELD_OFFSET(reg, offset, field, val)    \
1207     WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1208 
1209 /*
1210  * BIOS helpers.
1211  */
1212 #define RBIOS8(i) (adev->bios[i])
1213 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1214 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1215 
1216 /*
1217  * ASICs macro.
1218  */
1219 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1220 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1221 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1222 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1223 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1224 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1225 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1226 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1227 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1228 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1229 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1230 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1231 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1232 #define amdgpu_asic_flush_hdp(adev, r) \
1233     ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1234 #define amdgpu_asic_invalidate_hdp(adev, r) \
1235     ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1236      ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
1237 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1238 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1239 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1240 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1241 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1242 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1243 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1244 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1245     ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1246 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1247 
1248 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1249 
1250 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1251 
1252 /* Common functions */
1253 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1254 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1255 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1256                   struct amdgpu_job *job,
1257                   struct amdgpu_reset_context *reset_context);
1258 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1259 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1260 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1261 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1262 
1263 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1264                   u64 num_vis_bytes);
1265 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1266 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1267                          const u32 *registers,
1268                          const u32 array_size);
1269 
1270 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1271 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1272 bool amdgpu_device_supports_px(struct drm_device *dev);
1273 bool amdgpu_device_supports_boco(struct drm_device *dev);
1274 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1275 bool amdgpu_device_supports_baco(struct drm_device *dev);
1276 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1277                       struct amdgpu_device *peer_adev);
1278 int amdgpu_device_baco_enter(struct drm_device *dev);
1279 int amdgpu_device_baco_exit(struct drm_device *dev);
1280 
1281 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1282         struct amdgpu_ring *ring);
1283 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1284         struct amdgpu_ring *ring);
1285 
1286 void amdgpu_device_halt(struct amdgpu_device *adev);
1287 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1288                 u32 reg);
1289 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1290                 u32 reg, u32 v);
1291 
1292 /* atpx handler */
1293 #if defined(CONFIG_VGA_SWITCHEROO)
1294 void amdgpu_register_atpx_handler(void);
1295 void amdgpu_unregister_atpx_handler(void);
1296 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1297 bool amdgpu_is_atpx_hybrid(void);
1298 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1299 bool amdgpu_has_atpx(void);
1300 #else
1301 static inline void amdgpu_register_atpx_handler(void) {}
1302 static inline void amdgpu_unregister_atpx_handler(void) {}
1303 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1304 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1305 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1306 static inline bool amdgpu_has_atpx(void) { return false; }
1307 #endif
1308 
1309 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1310 void *amdgpu_atpx_get_dhandle(void);
1311 #else
1312 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1313 #endif
1314 
1315 /*
1316  * KMS
1317  */
1318 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1319 extern const int amdgpu_max_kms_ioctl;
1320 
1321 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1322 void amdgpu_driver_unload_kms(struct drm_device *dev);
1323 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1324 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1325 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1326                  struct drm_file *file_priv);
1327 void amdgpu_driver_release_kms(struct drm_device *dev);
1328 
1329 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1330 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1331 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1332 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1333 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1334 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1335 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1336               struct drm_file *filp);
1337 
1338 /*
1339  * functions used by amdgpu_encoder.c
1340  */
1341 struct amdgpu_afmt_acr {
1342     u32 clock;
1343 
1344     int n_32khz;
1345     int cts_32khz;
1346 
1347     int n_44_1khz;
1348     int cts_44_1khz;
1349 
1350     int n_48khz;
1351     int cts_48khz;
1352 
1353 };
1354 
1355 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1356 
1357 /* amdgpu_acpi.c */
1358 
1359 /* ATCS Device/Driver State */
1360 #define AMDGPU_ATCS_PSC_DEV_STATE_D0        0
1361 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT    3
1362 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR       0
1363 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR   1
1364 
1365 #if defined(CONFIG_ACPI)
1366 int amdgpu_acpi_init(struct amdgpu_device *adev);
1367 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1368 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1369 bool amdgpu_acpi_is_power_shift_control_supported(void);
1370 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1371                         u8 perf_req, bool advertise);
1372 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1373                     u8 dev_state, bool drv_state);
1374 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1375 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1376 
1377 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1378 void amdgpu_acpi_detect(void);
1379 #else
1380 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1381 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1382 static inline void amdgpu_acpi_detect(void) { }
1383 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1384 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1385                           u8 dev_state, bool drv_state) { return 0; }
1386 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1387                          enum amdgpu_ss ss_state) { return 0; }
1388 #endif
1389 
1390 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1391 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1392 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1393 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1394 #else
1395 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1396 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1397 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1398 #endif
1399 
1400 #if defined(CONFIG_DRM_AMD_DC)
1401 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1402 #else
1403 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1404 #endif
1405 
1406 
1407 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1408 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1409 
1410 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1411                        pci_channel_state_t state);
1412 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1413 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1414 void amdgpu_pci_resume(struct pci_dev *pdev);
1415 
1416 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1417 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1418 
1419 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1420 
1421 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1422                    enum amd_clockgating_state state);
1423 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1424                    enum amd_powergating_state state);
1425 
1426 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1427 {
1428     return amdgpu_gpu_recovery != 0 &&
1429         adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1430         adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1431         adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1432         adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1433 }
1434 
1435 #include "amdgpu_object.h"
1436 
1437 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1438 {
1439        return adev->gmc.tmz_enabled;
1440 }
1441 
1442 int amdgpu_in_reset(struct amdgpu_device *adev);
1443 
1444 #endif
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