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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Xilinx Zynq GPIO device driver
0004  *
0005  * Copyright (C) 2009 - 2014 Xilinx, Inc.
0006  */
0007 
0008 #include <linux/bitops.h>
0009 #include <linux/clk.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/io.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/of.h>
0019 
0020 #define DRIVER_NAME "zynq-gpio"
0021 
0022 /* Maximum banks */
0023 #define ZYNQ_GPIO_MAX_BANK  4
0024 #define ZYNQMP_GPIO_MAX_BANK    6
0025 #define VERSAL_GPIO_MAX_BANK    4
0026 #define PMC_GPIO_MAX_BANK   5
0027 #define VERSAL_UNUSED_BANKS 2
0028 
0029 #define ZYNQ_GPIO_BANK0_NGPIO   32
0030 #define ZYNQ_GPIO_BANK1_NGPIO   22
0031 #define ZYNQ_GPIO_BANK2_NGPIO   32
0032 #define ZYNQ_GPIO_BANK3_NGPIO   32
0033 
0034 #define ZYNQMP_GPIO_BANK0_NGPIO 26
0035 #define ZYNQMP_GPIO_BANK1_NGPIO 26
0036 #define ZYNQMP_GPIO_BANK2_NGPIO 26
0037 #define ZYNQMP_GPIO_BANK3_NGPIO 32
0038 #define ZYNQMP_GPIO_BANK4_NGPIO 32
0039 #define ZYNQMP_GPIO_BANK5_NGPIO 32
0040 
0041 #define ZYNQ_GPIO_NR_GPIOS  118
0042 #define ZYNQMP_GPIO_NR_GPIOS    174
0043 
0044 #define ZYNQ_GPIO_BANK0_PIN_MIN(str)    0
0045 #define ZYNQ_GPIO_BANK0_PIN_MAX(str)    (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
0046                     ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
0047 #define ZYNQ_GPIO_BANK1_PIN_MIN(str)    (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
0048 #define ZYNQ_GPIO_BANK1_PIN_MAX(str)    (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
0049                     ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
0050 #define ZYNQ_GPIO_BANK2_PIN_MIN(str)    (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
0051 #define ZYNQ_GPIO_BANK2_PIN_MAX(str)    (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
0052                     ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
0053 #define ZYNQ_GPIO_BANK3_PIN_MIN(str)    (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
0054 #define ZYNQ_GPIO_BANK3_PIN_MAX(str)    (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
0055                     ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
0056 #define ZYNQ_GPIO_BANK4_PIN_MIN(str)    (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
0057 #define ZYNQ_GPIO_BANK4_PIN_MAX(str)    (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
0058                     ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
0059 #define ZYNQ_GPIO_BANK5_PIN_MIN(str)    (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
0060 #define ZYNQ_GPIO_BANK5_PIN_MAX(str)    (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
0061                     ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
0062 
0063 /* Register offsets for the GPIO device */
0064 /* LSW Mask & Data -WO */
0065 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
0066 /* MSW Mask & Data -WO */
0067 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
0068 /* Data Register-RW */
0069 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
0070 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))
0071 /* Direction mode reg-RW */
0072 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
0073 /* Output enable reg-RW */
0074 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))
0075 /* Interrupt mask reg-RO */
0076 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))
0077 /* Interrupt enable reg-WO */
0078 #define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))
0079 /* Interrupt disable reg-WO */
0080 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))
0081 /* Interrupt status reg-RO */
0082 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))
0083 /* Interrupt type reg-RW */
0084 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))
0085 /* Interrupt polarity reg-RW */
0086 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))
0087 /* Interrupt on any, reg-RW */
0088 #define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))
0089 
0090 /* Disable all interrupts mask */
0091 #define ZYNQ_GPIO_IXR_DISABLE_ALL   0xFFFFFFFF
0092 
0093 /* Mid pin number of a bank */
0094 #define ZYNQ_GPIO_MID_PIN_NUM 16
0095 
0096 /* GPIO upper 16 bit mask */
0097 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
0098 
0099 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
0100 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
0101 #define GPIO_QUIRK_DATA_RO_BUG  BIT(1)
0102 #define GPIO_QUIRK_VERSAL   BIT(2)
0103 
0104 struct gpio_regs {
0105     u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
0106     u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
0107     u32 dirm[ZYNQMP_GPIO_MAX_BANK];
0108     u32 outen[ZYNQMP_GPIO_MAX_BANK];
0109     u32 int_en[ZYNQMP_GPIO_MAX_BANK];
0110     u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
0111     u32 int_type[ZYNQMP_GPIO_MAX_BANK];
0112     u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
0113     u32 int_any[ZYNQMP_GPIO_MAX_BANK];
0114 };
0115 
0116 /**
0117  * struct zynq_gpio - gpio device private data structure
0118  * @chip:   instance of the gpio_chip
0119  * @base_addr:  base address of the GPIO device
0120  * @clk:    clock resource for this controller
0121  * @irq:    interrupt for the GPIO device
0122  * @p_data: pointer to platform data
0123  * @context:    context registers
0124  * @dirlock:    lock used for direction in/out synchronization
0125  */
0126 struct zynq_gpio {
0127     struct gpio_chip chip;
0128     void __iomem *base_addr;
0129     struct clk *clk;
0130     int irq;
0131     const struct zynq_platform_data *p_data;
0132     struct gpio_regs context;
0133     spinlock_t dirlock; /* lock */
0134 };
0135 
0136 /**
0137  * struct zynq_platform_data -  zynq gpio platform data structure
0138  * @label:  string to store in gpio->label
0139  * @quirks: Flags is used to identify the platform
0140  * @ngpio:  max number of gpio pins
0141  * @max_bank:   maximum number of gpio banks
0142  * @bank_min:   this array represents bank's min pin
0143  * @bank_max:   this array represents bank's max pin
0144  */
0145 struct zynq_platform_data {
0146     const char *label;
0147     u32 quirks;
0148     u16 ngpio;
0149     int max_bank;
0150     int bank_min[ZYNQMP_GPIO_MAX_BANK];
0151     int bank_max[ZYNQMP_GPIO_MAX_BANK];
0152 };
0153 
0154 static struct irq_chip zynq_gpio_level_irqchip;
0155 static struct irq_chip zynq_gpio_edge_irqchip;
0156 
0157 /**
0158  * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
0159  * @gpio:   Pointer to driver data struct
0160  *
0161  * Return: 0 if zynqmp, 1 if zynq.
0162  */
0163 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
0164 {
0165     return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
0166 }
0167 
0168 /**
0169  * gpio_data_ro_bug - test if HW bug exists or not
0170  * @gpio:       Pointer to driver data struct
0171  *
0172  * Return: 0 if bug doesnot exist, 1 if bug exists.
0173  */
0174 static int gpio_data_ro_bug(struct zynq_gpio *gpio)
0175 {
0176     return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
0177 }
0178 
0179 /**
0180  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
0181  * for a given pin in the GPIO device
0182  * @pin_num:    gpio pin number within the device
0183  * @bank_num:   an output parameter used to return the bank number of the gpio
0184  *      pin
0185  * @bank_pin_num: an output parameter used to return pin number within a bank
0186  *        for the given gpio pin
0187  * @gpio:   gpio device data structure
0188  *
0189  * Returns the bank number and pin offset within the bank.
0190  */
0191 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
0192                       unsigned int *bank_num,
0193                       unsigned int *bank_pin_num,
0194                       struct zynq_gpio *gpio)
0195 {
0196     int bank;
0197 
0198     for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
0199         if ((pin_num >= gpio->p_data->bank_min[bank]) &&
0200             (pin_num <= gpio->p_data->bank_max[bank])) {
0201             *bank_num = bank;
0202             *bank_pin_num = pin_num -
0203                     gpio->p_data->bank_min[bank];
0204             return;
0205         }
0206         if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
0207             bank = bank + VERSAL_UNUSED_BANKS;
0208     }
0209 
0210     /* default */
0211     WARN(true, "invalid GPIO pin number: %u", pin_num);
0212     *bank_num = 0;
0213     *bank_pin_num = 0;
0214 }
0215 
0216 /**
0217  * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
0218  * @chip:   gpio_chip instance to be worked on
0219  * @pin:    gpio pin number within the device
0220  *
0221  * This function reads the state of the specified pin of the GPIO device.
0222  *
0223  * Return: 0 if the pin is low, 1 if pin is high.
0224  */
0225 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
0226 {
0227     u32 data;
0228     unsigned int bank_num, bank_pin_num;
0229     struct zynq_gpio *gpio = gpiochip_get_data(chip);
0230 
0231     zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
0232 
0233     if (gpio_data_ro_bug(gpio)) {
0234         if (zynq_gpio_is_zynq(gpio)) {
0235             if (bank_num <= 1) {
0236                 data = readl_relaxed(gpio->base_addr +
0237                     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
0238             } else {
0239                 data = readl_relaxed(gpio->base_addr +
0240                     ZYNQ_GPIO_DATA_OFFSET(bank_num));
0241             }
0242         } else {
0243             if (bank_num <= 2) {
0244                 data = readl_relaxed(gpio->base_addr +
0245                     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
0246             } else {
0247                 data = readl_relaxed(gpio->base_addr +
0248                     ZYNQ_GPIO_DATA_OFFSET(bank_num));
0249             }
0250         }
0251     } else {
0252         data = readl_relaxed(gpio->base_addr +
0253             ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
0254     }
0255     return (data >> bank_pin_num) & 1;
0256 }
0257 
0258 /**
0259  * zynq_gpio_set_value - Modify the state of the pin with specified value
0260  * @chip:   gpio_chip instance to be worked on
0261  * @pin:    gpio pin number within the device
0262  * @state:  value used to modify the state of the specified pin
0263  *
0264  * This function calculates the register offset (i.e to lower 16 bits or
0265  * upper 16 bits) based on the given pin number and sets the state of a
0266  * gpio pin to the specified value. The state is either 0 or non-zero.
0267  */
0268 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
0269                 int state)
0270 {
0271     unsigned int reg_offset, bank_num, bank_pin_num;
0272     struct zynq_gpio *gpio = gpiochip_get_data(chip);
0273 
0274     zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
0275 
0276     if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
0277         /* only 16 data bits in bit maskable reg */
0278         bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
0279         reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
0280     } else {
0281         reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
0282     }
0283 
0284     /*
0285      * get the 32 bit value to be written to the mask/data register where
0286      * the upper 16 bits is the mask and lower 16 bits is the data
0287      */
0288     state = !!state;
0289     state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
0290         ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
0291 
0292     writel_relaxed(state, gpio->base_addr + reg_offset);
0293 }
0294 
0295 /**
0296  * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
0297  * @chip:   gpio_chip instance to be worked on
0298  * @pin:    gpio pin number within the device
0299  *
0300  * This function uses the read-modify-write sequence to set the direction of
0301  * the gpio pin as input.
0302  *
0303  * Return: 0 always
0304  */
0305 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
0306 {
0307     u32 reg;
0308     unsigned int bank_num, bank_pin_num;
0309     unsigned long flags;
0310     struct zynq_gpio *gpio = gpiochip_get_data(chip);
0311 
0312     zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
0313 
0314     /*
0315      * On zynq bank 0 pins 7 and 8 are special and cannot be used
0316      * as inputs.
0317      */
0318     if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
0319         (bank_pin_num == 7 || bank_pin_num == 8))
0320         return -EINVAL;
0321 
0322     /* clear the bit in direction mode reg to set the pin as input */
0323     spin_lock_irqsave(&gpio->dirlock, flags);
0324     reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0325     reg &= ~BIT(bank_pin_num);
0326     writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0327     spin_unlock_irqrestore(&gpio->dirlock, flags);
0328 
0329     return 0;
0330 }
0331 
0332 /**
0333  * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
0334  * @chip:   gpio_chip instance to be worked on
0335  * @pin:    gpio pin number within the device
0336  * @state:  value to be written to specified pin
0337  *
0338  * This function sets the direction of specified GPIO pin as output, configures
0339  * the Output Enable register for the pin and uses zynq_gpio_set to set
0340  * the state of the pin to the value specified.
0341  *
0342  * Return: 0 always
0343  */
0344 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
0345                  int state)
0346 {
0347     u32 reg;
0348     unsigned int bank_num, bank_pin_num;
0349     unsigned long flags;
0350     struct zynq_gpio *gpio = gpiochip_get_data(chip);
0351 
0352     zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
0353 
0354     /* set the GPIO pin as output */
0355     spin_lock_irqsave(&gpio->dirlock, flags);
0356     reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0357     reg |= BIT(bank_pin_num);
0358     writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0359 
0360     /* configure the output enable reg for the pin */
0361     reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
0362     reg |= BIT(bank_pin_num);
0363     writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
0364     spin_unlock_irqrestore(&gpio->dirlock, flags);
0365 
0366     /* set the state of the pin */
0367     zynq_gpio_set_value(chip, pin, state);
0368     return 0;
0369 }
0370 
0371 /**
0372  * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
0373  * @chip:   gpio_chip instance to be worked on
0374  * @pin:    gpio pin number within the device
0375  *
0376  * This function returns the direction of the specified GPIO.
0377  *
0378  * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
0379  */
0380 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
0381 {
0382     u32 reg;
0383     unsigned int bank_num, bank_pin_num;
0384     struct zynq_gpio *gpio = gpiochip_get_data(chip);
0385 
0386     zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
0387 
0388     reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0389 
0390     if (reg & BIT(bank_pin_num))
0391         return GPIO_LINE_DIRECTION_OUT;
0392 
0393     return GPIO_LINE_DIRECTION_IN;
0394 }
0395 
0396 /**
0397  * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
0398  * @irq_data:   per irq and chip data passed down to chip functions
0399  *
0400  * This function calculates gpio pin number from irq number and sets the
0401  * bit in the Interrupt Disable register of the corresponding bank to disable
0402  * interrupts for that pin.
0403  */
0404 static void zynq_gpio_irq_mask(struct irq_data *irq_data)
0405 {
0406     unsigned int device_pin_num, bank_num, bank_pin_num;
0407     struct zynq_gpio *gpio =
0408         gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
0409 
0410     device_pin_num = irq_data->hwirq;
0411     zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
0412     writel_relaxed(BIT(bank_pin_num),
0413                gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
0414 }
0415 
0416 /**
0417  * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
0418  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
0419  *      to enable
0420  *
0421  * This function calculates the gpio pin number from irq number and sets the
0422  * bit in the Interrupt Enable register of the corresponding bank to enable
0423  * interrupts for that pin.
0424  */
0425 static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
0426 {
0427     unsigned int device_pin_num, bank_num, bank_pin_num;
0428     struct zynq_gpio *gpio =
0429         gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
0430 
0431     device_pin_num = irq_data->hwirq;
0432     zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
0433     writel_relaxed(BIT(bank_pin_num),
0434                gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
0435 }
0436 
0437 /**
0438  * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
0439  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
0440  *      to ack
0441  *
0442  * This function calculates gpio pin number from irq number and sets the bit
0443  * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
0444  */
0445 static void zynq_gpio_irq_ack(struct irq_data *irq_data)
0446 {
0447     unsigned int device_pin_num, bank_num, bank_pin_num;
0448     struct zynq_gpio *gpio =
0449         gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
0450 
0451     device_pin_num = irq_data->hwirq;
0452     zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
0453     writel_relaxed(BIT(bank_pin_num),
0454                gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
0455 }
0456 
0457 /**
0458  * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
0459  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
0460  *      to enable
0461  *
0462  * Clears the INTSTS bit and unmasks the given interrupt.
0463  */
0464 static void zynq_gpio_irq_enable(struct irq_data *irq_data)
0465 {
0466     /*
0467      * The Zynq GPIO controller does not disable interrupt detection when
0468      * the interrupt is masked and only disables the propagation of the
0469      * interrupt. This means when the controller detects an interrupt
0470      * condition while the interrupt is logically disabled it will propagate
0471      * that interrupt event once the interrupt is enabled. This will cause
0472      * the interrupt consumer to see spurious interrupts to prevent this
0473      * first make sure that the interrupt is not asserted and then enable
0474      * it.
0475      */
0476     zynq_gpio_irq_ack(irq_data);
0477     zynq_gpio_irq_unmask(irq_data);
0478 }
0479 
0480 /**
0481  * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
0482  * @irq_data:   irq data containing irq number of gpio pin
0483  * @type:   interrupt type that is to be set for the gpio pin
0484  *
0485  * This function gets the gpio pin number and its bank from the gpio pin number
0486  * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
0487  *
0488  * Return: 0, negative error otherwise.
0489  * TYPE-EDGE_RISING,  INT_TYPE - 1, INT_POLARITY - 1,  INT_ANY - 0;
0490  * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0,  INT_ANY - 0;
0491  * TYPE-EDGE_BOTH,    INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
0492  * TYPE-LEVEL_HIGH,   INT_TYPE - 0, INT_POLARITY - 1,  INT_ANY - NA;
0493  * TYPE-LEVEL_LOW,    INT_TYPE - 0, INT_POLARITY - 0,  INT_ANY - NA
0494  */
0495 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
0496 {
0497     u32 int_type, int_pol, int_any;
0498     unsigned int device_pin_num, bank_num, bank_pin_num;
0499     struct zynq_gpio *gpio =
0500         gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
0501 
0502     device_pin_num = irq_data->hwirq;
0503     zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
0504 
0505     int_type = readl_relaxed(gpio->base_addr +
0506                  ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
0507     int_pol = readl_relaxed(gpio->base_addr +
0508                 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
0509     int_any = readl_relaxed(gpio->base_addr +
0510                 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
0511 
0512     /*
0513      * based on the type requested, configure the INT_TYPE, INT_POLARITY
0514      * and INT_ANY registers
0515      */
0516     switch (type) {
0517     case IRQ_TYPE_EDGE_RISING:
0518         int_type |= BIT(bank_pin_num);
0519         int_pol |= BIT(bank_pin_num);
0520         int_any &= ~BIT(bank_pin_num);
0521         break;
0522     case IRQ_TYPE_EDGE_FALLING:
0523         int_type |= BIT(bank_pin_num);
0524         int_pol &= ~BIT(bank_pin_num);
0525         int_any &= ~BIT(bank_pin_num);
0526         break;
0527     case IRQ_TYPE_EDGE_BOTH:
0528         int_type |= BIT(bank_pin_num);
0529         int_any |= BIT(bank_pin_num);
0530         break;
0531     case IRQ_TYPE_LEVEL_HIGH:
0532         int_type &= ~BIT(bank_pin_num);
0533         int_pol |= BIT(bank_pin_num);
0534         break;
0535     case IRQ_TYPE_LEVEL_LOW:
0536         int_type &= ~BIT(bank_pin_num);
0537         int_pol &= ~BIT(bank_pin_num);
0538         break;
0539     default:
0540         return -EINVAL;
0541     }
0542 
0543     writel_relaxed(int_type,
0544                gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
0545     writel_relaxed(int_pol,
0546                gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
0547     writel_relaxed(int_any,
0548                gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
0549 
0550     if (type & IRQ_TYPE_LEVEL_MASK)
0551         irq_set_chip_handler_name_locked(irq_data,
0552                          &zynq_gpio_level_irqchip,
0553                          handle_fasteoi_irq, NULL);
0554     else
0555         irq_set_chip_handler_name_locked(irq_data,
0556                          &zynq_gpio_edge_irqchip,
0557                          handle_level_irq, NULL);
0558 
0559     return 0;
0560 }
0561 
0562 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
0563 {
0564     struct zynq_gpio *gpio =
0565         gpiochip_get_data(irq_data_get_irq_chip_data(data));
0566 
0567     irq_set_irq_wake(gpio->irq, on);
0568 
0569     return 0;
0570 }
0571 
0572 static int zynq_gpio_irq_reqres(struct irq_data *d)
0573 {
0574     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0575     int ret;
0576 
0577     ret = pm_runtime_resume_and_get(chip->parent);
0578     if (ret < 0)
0579         return ret;
0580 
0581     return gpiochip_reqres_irq(chip, d->hwirq);
0582 }
0583 
0584 static void zynq_gpio_irq_relres(struct irq_data *d)
0585 {
0586     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0587 
0588     gpiochip_relres_irq(chip, d->hwirq);
0589     pm_runtime_put(chip->parent);
0590 }
0591 
0592 /* irq chip descriptor */
0593 static struct irq_chip zynq_gpio_level_irqchip = {
0594     .name       = DRIVER_NAME,
0595     .irq_enable = zynq_gpio_irq_enable,
0596     .irq_eoi    = zynq_gpio_irq_ack,
0597     .irq_mask   = zynq_gpio_irq_mask,
0598     .irq_unmask = zynq_gpio_irq_unmask,
0599     .irq_set_type   = zynq_gpio_set_irq_type,
0600     .irq_set_wake   = zynq_gpio_set_wake,
0601     .irq_request_resources = zynq_gpio_irq_reqres,
0602     .irq_release_resources = zynq_gpio_irq_relres,
0603     .flags      = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
0604               IRQCHIP_MASK_ON_SUSPEND,
0605 };
0606 
0607 static struct irq_chip zynq_gpio_edge_irqchip = {
0608     .name       = DRIVER_NAME,
0609     .irq_enable = zynq_gpio_irq_enable,
0610     .irq_ack    = zynq_gpio_irq_ack,
0611     .irq_mask   = zynq_gpio_irq_mask,
0612     .irq_unmask = zynq_gpio_irq_unmask,
0613     .irq_set_type   = zynq_gpio_set_irq_type,
0614     .irq_set_wake   = zynq_gpio_set_wake,
0615     .irq_request_resources = zynq_gpio_irq_reqres,
0616     .irq_release_resources = zynq_gpio_irq_relres,
0617     .flags      = IRQCHIP_MASK_ON_SUSPEND,
0618 };
0619 
0620 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
0621                       unsigned int bank_num,
0622                       unsigned long pending)
0623 {
0624     unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
0625     struct irq_domain *irqdomain = gpio->chip.irq.domain;
0626     int offset;
0627 
0628     if (!pending)
0629         return;
0630 
0631     for_each_set_bit(offset, &pending, 32)
0632         generic_handle_domain_irq(irqdomain, offset + bank_offset);
0633 }
0634 
0635 /**
0636  * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
0637  * @desc:   irq descriptor instance of the 'irq'
0638  *
0639  * This function reads the Interrupt Status Register of each bank to get the
0640  * gpio pin number which has triggered an interrupt. It then acks the triggered
0641  * interrupt and calls the pin specific handler set by the higher layer
0642  * application for that pin.
0643  * Note: A bug is reported if no handler is set for the gpio pin.
0644  */
0645 static void zynq_gpio_irqhandler(struct irq_desc *desc)
0646 {
0647     u32 int_sts, int_enb;
0648     unsigned int bank_num;
0649     struct zynq_gpio *gpio =
0650         gpiochip_get_data(irq_desc_get_handler_data(desc));
0651     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0652 
0653     chained_irq_enter(irqchip, desc);
0654 
0655     for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
0656         int_sts = readl_relaxed(gpio->base_addr +
0657                     ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
0658         int_enb = readl_relaxed(gpio->base_addr +
0659                     ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
0660         zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
0661         if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
0662             bank_num = bank_num + VERSAL_UNUSED_BANKS;
0663     }
0664 
0665     chained_irq_exit(irqchip, desc);
0666 }
0667 
0668 static void zynq_gpio_save_context(struct zynq_gpio *gpio)
0669 {
0670     unsigned int bank_num;
0671 
0672     for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
0673         gpio->context.datalsw[bank_num] =
0674                 readl_relaxed(gpio->base_addr +
0675                 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
0676         gpio->context.datamsw[bank_num] =
0677                 readl_relaxed(gpio->base_addr +
0678                 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
0679         gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
0680                 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0681         gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
0682                 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
0683         gpio->context.int_type[bank_num] =
0684                 readl_relaxed(gpio->base_addr +
0685                 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
0686         gpio->context.int_polarity[bank_num] =
0687                 readl_relaxed(gpio->base_addr +
0688                 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
0689         gpio->context.int_any[bank_num] =
0690                 readl_relaxed(gpio->base_addr +
0691                 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
0692         if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
0693             bank_num = bank_num + VERSAL_UNUSED_BANKS;
0694     }
0695 }
0696 
0697 static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
0698 {
0699     unsigned int bank_num;
0700 
0701     for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
0702         writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
0703                 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
0704         writel_relaxed(gpio->context.datalsw[bank_num],
0705                    gpio->base_addr +
0706                    ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
0707         writel_relaxed(gpio->context.datamsw[bank_num],
0708                    gpio->base_addr +
0709                    ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
0710         writel_relaxed(gpio->context.dirm[bank_num],
0711                    gpio->base_addr +
0712                    ZYNQ_GPIO_DIRM_OFFSET(bank_num));
0713         writel_relaxed(gpio->context.int_type[bank_num],
0714                    gpio->base_addr +
0715                    ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
0716         writel_relaxed(gpio->context.int_polarity[bank_num],
0717                    gpio->base_addr +
0718                    ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
0719         writel_relaxed(gpio->context.int_any[bank_num],
0720                    gpio->base_addr +
0721                    ZYNQ_GPIO_INTANY_OFFSET(bank_num));
0722         writel_relaxed(~(gpio->context.int_en[bank_num]),
0723                    gpio->base_addr +
0724                    ZYNQ_GPIO_INTEN_OFFSET(bank_num));
0725         if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
0726             bank_num = bank_num + VERSAL_UNUSED_BANKS;
0727     }
0728 }
0729 
0730 static int __maybe_unused zynq_gpio_suspend(struct device *dev)
0731 {
0732     struct zynq_gpio *gpio = dev_get_drvdata(dev);
0733     struct irq_data *data = irq_get_irq_data(gpio->irq);
0734 
0735     if (!data) {
0736         dev_err(dev, "irq_get_irq_data() failed\n");
0737         return -EINVAL;
0738     }
0739 
0740     if (!device_may_wakeup(dev))
0741         disable_irq(gpio->irq);
0742 
0743     if (!irqd_is_wakeup_set(data)) {
0744         zynq_gpio_save_context(gpio);
0745         return pm_runtime_force_suspend(dev);
0746     }
0747 
0748     return 0;
0749 }
0750 
0751 static int __maybe_unused zynq_gpio_resume(struct device *dev)
0752 {
0753     struct zynq_gpio *gpio = dev_get_drvdata(dev);
0754     struct irq_data *data = irq_get_irq_data(gpio->irq);
0755     int ret;
0756 
0757     if (!data) {
0758         dev_err(dev, "irq_get_irq_data() failed\n");
0759         return -EINVAL;
0760     }
0761 
0762     if (!device_may_wakeup(dev))
0763         enable_irq(gpio->irq);
0764 
0765     if (!irqd_is_wakeup_set(data)) {
0766         ret = pm_runtime_force_resume(dev);
0767         zynq_gpio_restore_context(gpio);
0768         return ret;
0769     }
0770 
0771     return 0;
0772 }
0773 
0774 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
0775 {
0776     struct zynq_gpio *gpio = dev_get_drvdata(dev);
0777 
0778     clk_disable_unprepare(gpio->clk);
0779 
0780     return 0;
0781 }
0782 
0783 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
0784 {
0785     struct zynq_gpio *gpio = dev_get_drvdata(dev);
0786 
0787     return clk_prepare_enable(gpio->clk);
0788 }
0789 
0790 static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
0791 {
0792     int ret;
0793 
0794     ret = pm_runtime_get_sync(chip->parent);
0795 
0796     /*
0797      * If the device is already active pm_runtime_get() will return 1 on
0798      * success, but gpio_request still needs to return 0.
0799      */
0800     return ret < 0 ? ret : 0;
0801 }
0802 
0803 static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
0804 {
0805     pm_runtime_put(chip->parent);
0806 }
0807 
0808 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
0809     SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
0810     SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
0811                zynq_gpio_runtime_resume, NULL)
0812 };
0813 
0814 static const struct zynq_platform_data versal_gpio_def = {
0815     .label = "versal_gpio",
0816     .quirks = GPIO_QUIRK_VERSAL,
0817     .ngpio = 58,
0818     .max_bank = VERSAL_GPIO_MAX_BANK,
0819     .bank_min[0] = 0,
0820     .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
0821     .bank_min[3] = 26,
0822     .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
0823 };
0824 
0825 static const struct zynq_platform_data pmc_gpio_def = {
0826     .label = "pmc_gpio",
0827     .ngpio = 116,
0828     .max_bank = PMC_GPIO_MAX_BANK,
0829     .bank_min[0] = 0,
0830     .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
0831     .bank_min[1] = 26,
0832     .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
0833     .bank_min[3] = 52,
0834     .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
0835     .bank_min[4] = 84,
0836     .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
0837 };
0838 
0839 static const struct zynq_platform_data zynqmp_gpio_def = {
0840     .label = "zynqmp_gpio",
0841     .quirks = GPIO_QUIRK_DATA_RO_BUG,
0842     .ngpio = ZYNQMP_GPIO_NR_GPIOS,
0843     .max_bank = ZYNQMP_GPIO_MAX_BANK,
0844     .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
0845     .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
0846     .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
0847     .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
0848     .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
0849     .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
0850     .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
0851     .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
0852     .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
0853     .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
0854     .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
0855     .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
0856 };
0857 
0858 static const struct zynq_platform_data zynq_gpio_def = {
0859     .label = "zynq_gpio",
0860     .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
0861     .ngpio = ZYNQ_GPIO_NR_GPIOS,
0862     .max_bank = ZYNQ_GPIO_MAX_BANK,
0863     .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
0864     .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
0865     .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
0866     .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
0867     .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
0868     .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
0869     .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
0870     .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
0871 };
0872 
0873 static const struct of_device_id zynq_gpio_of_match[] = {
0874     { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
0875     { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
0876     { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
0877     { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
0878     { /* end of table */ }
0879 };
0880 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
0881 
0882 /**
0883  * zynq_gpio_probe - Initialization method for a zynq_gpio device
0884  * @pdev:   platform device instance
0885  *
0886  * This function allocates memory resources for the gpio device and registers
0887  * all the banks of the device. It will also set up interrupts for the gpio
0888  * pins.
0889  * Note: Interrupts are disabled for all the banks during initialization.
0890  *
0891  * Return: 0 on success, negative error otherwise.
0892  */
0893 static int zynq_gpio_probe(struct platform_device *pdev)
0894 {
0895     int ret, bank_num;
0896     struct zynq_gpio *gpio;
0897     struct gpio_chip *chip;
0898     struct gpio_irq_chip *girq;
0899     const struct of_device_id *match;
0900 
0901     gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
0902     if (!gpio)
0903         return -ENOMEM;
0904 
0905     match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
0906     if (!match) {
0907         dev_err(&pdev->dev, "of_match_node() failed\n");
0908         return -EINVAL;
0909     }
0910     gpio->p_data = match->data;
0911     platform_set_drvdata(pdev, gpio);
0912 
0913     gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
0914     if (IS_ERR(gpio->base_addr))
0915         return PTR_ERR(gpio->base_addr);
0916 
0917     gpio->irq = platform_get_irq(pdev, 0);
0918     if (gpio->irq < 0)
0919         return gpio->irq;
0920 
0921     /* configure the gpio chip */
0922     chip = &gpio->chip;
0923     chip->label = gpio->p_data->label;
0924     chip->owner = THIS_MODULE;
0925     chip->parent = &pdev->dev;
0926     chip->get = zynq_gpio_get_value;
0927     chip->set = zynq_gpio_set_value;
0928     chip->request = zynq_gpio_request;
0929     chip->free = zynq_gpio_free;
0930     chip->direction_input = zynq_gpio_dir_in;
0931     chip->direction_output = zynq_gpio_dir_out;
0932     chip->get_direction = zynq_gpio_get_direction;
0933     chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
0934     chip->ngpio = gpio->p_data->ngpio;
0935 
0936     /* Retrieve GPIO clock */
0937     gpio->clk = devm_clk_get(&pdev->dev, NULL);
0938     if (IS_ERR(gpio->clk))
0939         return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
0940 
0941     ret = clk_prepare_enable(gpio->clk);
0942     if (ret) {
0943         dev_err(&pdev->dev, "Unable to enable clock.\n");
0944         return ret;
0945     }
0946 
0947     spin_lock_init(&gpio->dirlock);
0948 
0949     pm_runtime_set_active(&pdev->dev);
0950     pm_runtime_enable(&pdev->dev);
0951     ret = pm_runtime_resume_and_get(&pdev->dev);
0952     if (ret < 0)
0953         goto err_pm_dis;
0954 
0955     /* disable interrupts for all banks */
0956     for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
0957         writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
0958                    ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
0959         if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
0960             bank_num = bank_num + VERSAL_UNUSED_BANKS;
0961     }
0962 
0963     /* Set up the GPIO irqchip */
0964     girq = &chip->irq;
0965     girq->chip = &zynq_gpio_edge_irqchip;
0966     girq->parent_handler = zynq_gpio_irqhandler;
0967     girq->num_parents = 1;
0968     girq->parents = devm_kcalloc(&pdev->dev, 1,
0969                      sizeof(*girq->parents),
0970                      GFP_KERNEL);
0971     if (!girq->parents) {
0972         ret = -ENOMEM;
0973         goto err_pm_put;
0974     }
0975     girq->parents[0] = gpio->irq;
0976     girq->default_type = IRQ_TYPE_NONE;
0977     girq->handler = handle_level_irq;
0978 
0979     /* report a bug if gpio chip registration fails */
0980     ret = gpiochip_add_data(chip, gpio);
0981     if (ret) {
0982         dev_err(&pdev->dev, "Failed to add gpio chip\n");
0983         goto err_pm_put;
0984     }
0985 
0986     irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
0987     device_init_wakeup(&pdev->dev, 1);
0988     pm_runtime_put(&pdev->dev);
0989 
0990     return 0;
0991 
0992 err_pm_put:
0993     pm_runtime_put(&pdev->dev);
0994 err_pm_dis:
0995     pm_runtime_disable(&pdev->dev);
0996     clk_disable_unprepare(gpio->clk);
0997 
0998     return ret;
0999 }
1000 
1001 /**
1002  * zynq_gpio_remove - Driver removal function
1003  * @pdev:   platform device instance
1004  *
1005  * Return: 0 always
1006  */
1007 static int zynq_gpio_remove(struct platform_device *pdev)
1008 {
1009     struct zynq_gpio *gpio = platform_get_drvdata(pdev);
1010     int ret;
1011 
1012     ret = pm_runtime_get_sync(&pdev->dev);
1013     if (ret < 0)
1014         dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");
1015     gpiochip_remove(&gpio->chip);
1016     clk_disable_unprepare(gpio->clk);
1017     device_set_wakeup_capable(&pdev->dev, 0);
1018     pm_runtime_disable(&pdev->dev);
1019     return 0;
1020 }
1021 
1022 static struct platform_driver zynq_gpio_driver = {
1023     .driver = {
1024         .name = DRIVER_NAME,
1025         .pm = &zynq_gpio_dev_pm_ops,
1026         .of_match_table = zynq_gpio_of_match,
1027     },
1028     .probe = zynq_gpio_probe,
1029     .remove = zynq_gpio_remove,
1030 };
1031 
1032 module_platform_driver(zynq_gpio_driver);
1033 
1034 MODULE_AUTHOR("Xilinx Inc.");
1035 MODULE_DESCRIPTION("Zynq GPIO driver");
1036 MODULE_LICENSE("GPL");
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