drivers/gpio/gpio-xlp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2003-2015 Broadcom Corporation
0004  * All Rights Reserved
0005  */
0006
0007 #include <linux/gpio/driver.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/module.h>
0010 #include <linux/irq.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/irqchip/chained_irq.h>
0013 #include <linux/acpi.h>
0014
0015 /*
0016  * XLP GPIO has multiple 32 bit registers for each feature where each register
0017  * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
0018  * require 3 32-bit registers for each feature.
0019  * Here we only define offset of the first register for each feature. Offset of
0020  * the registers for pins greater than 32 can be calculated as following(Use
0021  * GPIO_INT_STAT as example):
0022  *
0023  * offset = (gpio / XLP_GPIO_REGSZ) * 4;
0024  * reg_addr = addr + offset;
0025  *
0026  * where addr is base address of the that feature register and gpio is the pin.
0027  */
0028 #define GPIO_9XX_BYTESWAP   0X00
0029 #define GPIO_9XX_CTRL       0X04
0030 #define GPIO_9XX_OUTPUT_EN  0x14
0031 #define GPIO_9XX_PADDRV     0x24
0032 /*
0033  * Only for 4 interrupt enable reg are defined for now,
0034  * total reg available are 12.
0035  */
0036 #define GPIO_9XX_INT_EN00   0x44
0037 #define GPIO_9XX_INT_EN10   0x54
0038 #define GPIO_9XX_INT_EN20   0x64
0039 #define GPIO_9XX_INT_EN30   0x74
0040 #define GPIO_9XX_INT_POL    0x104
0041 #define GPIO_9XX_INT_TYPE   0x114
0042 #define GPIO_9XX_INT_STAT   0x124
0043
0044 /* Interrupt type register mask */
0045 #define XLP_GPIO_IRQ_TYPE_LVL   0x0
0046 #define XLP_GPIO_IRQ_TYPE_EDGE  0x1
0047
0048 /* Interrupt polarity register mask */
0049 #define XLP_GPIO_IRQ_POL_HIGH   0x0
0050 #define XLP_GPIO_IRQ_POL_LOW    0x1
0051
0052 #define XLP_GPIO_REGSZ      32
0053 #define XLP_GPIO_IRQ_BASE   768
0054 #define XLP_MAX_NR_GPIO     96
0055
0056 struct xlp_gpio_priv {
0057     struct gpio_chip chip;
0058     DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
0059     void __iomem *gpio_intr_en; /* pointer to first intr enable reg */
0060     void __iomem *gpio_intr_stat;   /* pointer to first intr status reg */
0061     void __iomem *gpio_intr_type;   /* pointer to first intr type reg */
0062     void __iomem *gpio_intr_pol;    /* pointer to first intr polarity reg */
0063     void __iomem *gpio_out_en;  /* pointer to first output enable reg */
0064     void __iomem *gpio_paddrv;  /* pointer to first pad drive reg */
0065     spinlock_t lock;
0066 };
0067
0068 static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
0069 {
0070     u32 pos, regset;
0071
0072     pos = gpio % XLP_GPIO_REGSZ;
0073     regset = (gpio / XLP_GPIO_REGSZ) * 4;
0074     return !!(readl(addr + regset) & BIT(pos));
0075 }
0076
0077 static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
0078 {
0079     u32 value, pos, regset;
0080
0081     pos = gpio % XLP_GPIO_REGSZ;
0082     regset = (gpio / XLP_GPIO_REGSZ) * 4;
0083     value = readl(addr + regset);
0084
0085     if (state)
0086         value |= BIT(pos);
0087     else
0088         value &= ~BIT(pos);
0089
0090     writel(value, addr + regset);
0091 }
0092
0093 static void xlp_gpio_irq_disable(struct irq_data *d)
0094 {
0095     struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
0096     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0097     unsigned long flags;
0098
0099     spin_lock_irqsave(&priv->lock, flags);
0100     xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
0101     __clear_bit(d->hwirq, priv->gpio_enabled_mask);
0102     spin_unlock_irqrestore(&priv->lock, flags);
0103 }
0104
0105 static void xlp_gpio_irq_mask_ack(struct irq_data *d)
0106 {
0107     struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
0108     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0109     unsigned long flags;
0110
0111     spin_lock_irqsave(&priv->lock, flags);
0112     xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
0113     xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
0114     __clear_bit(d->hwirq, priv->gpio_enabled_mask);
0115     spin_unlock_irqrestore(&priv->lock, flags);
0116 }
0117
0118 static void xlp_gpio_irq_unmask(struct irq_data *d)
0119 {
0120     struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
0121     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0122     unsigned long flags;
0123
0124     spin_lock_irqsave(&priv->lock, flags);
0125     xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
0126     __set_bit(d->hwirq, priv->gpio_enabled_mask);
0127     spin_unlock_irqrestore(&priv->lock, flags);
0128 }
0129
0130 static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
0131 {
0132     struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
0133     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0134     int pol, irq_type;
0135
0136     switch (type) {
0137     case IRQ_TYPE_EDGE_RISING:
0138         irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
0139         pol = XLP_GPIO_IRQ_POL_HIGH;
0140         break;
0141     case IRQ_TYPE_EDGE_FALLING:
0142         irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
0143         pol = XLP_GPIO_IRQ_POL_LOW;
0144         break;
0145     case IRQ_TYPE_LEVEL_HIGH:
0146         irq_type = XLP_GPIO_IRQ_TYPE_LVL;
0147         pol = XLP_GPIO_IRQ_POL_HIGH;
0148         break;
0149     case IRQ_TYPE_LEVEL_LOW:
0150         irq_type = XLP_GPIO_IRQ_TYPE_LVL;
0151         pol = XLP_GPIO_IRQ_POL_LOW;
0152         break;
0153     default:
0154         return -EINVAL;
0155     }
0156
0157     xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
0158     xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
0159
0160     return 0;
0161 }
0162
0163 static struct irq_chip xlp_gpio_irq_chip = {
0164     .name       = "XLP-GPIO",
0165     .irq_mask_ack   = xlp_gpio_irq_mask_ack,
0166     .irq_disable    = xlp_gpio_irq_disable,
0167     .irq_set_type   = xlp_gpio_set_irq_type,
0168     .irq_unmask = xlp_gpio_irq_unmask,
0169     .flags      = IRQCHIP_ONESHOT_SAFE,
0170 };
0171
0172 static void xlp_gpio_generic_handler(struct irq_desc *desc)
0173 {
0174     struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
0175     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0176     int gpio, regoff;
0177     u32 gpio_stat;
0178
0179     regoff = -1;
0180     gpio_stat = 0;
0181
0182     chained_irq_enter(irqchip, desc);
0183     for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
0184         if (regoff != gpio / XLP_GPIO_REGSZ) {
0185             regoff = gpio / XLP_GPIO_REGSZ;
0186             gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
0187         }
0188
0189         if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
0190             generic_handle_domain_irq(priv->chip.irq.domain, gpio);
0191     }
0192     chained_irq_exit(irqchip, desc);
0193 }
0194
0195 static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
0196 {
0197     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0198
0199     BUG_ON(gpio >= gc->ngpio);
0200     xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
0201
0202     return 0;
0203 }
0204
0205 static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
0206 {
0207     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0208
0209     BUG_ON(gpio >= gc->ngpio);
0210     xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
0211
0212     return 0;
0213 }
0214
0215 static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
0216 {
0217     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0218
0219     BUG_ON(gpio >= gc->ngpio);
0220     return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
0221 }
0222
0223 static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
0224 {
0225     struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
0226
0227     BUG_ON(gpio >= gc->ngpio);
0228     xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
0229 }
0230
0231 static int xlp_gpio_probe(struct platform_device *pdev)
0232 {
0233     struct gpio_chip *gc;
0234     struct gpio_irq_chip *girq;
0235     struct xlp_gpio_priv *priv;
0236     void __iomem *gpio_base;
0237     int irq, err;
0238
0239     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0240     if (!priv)
0241         return -ENOMEM;
0242
0243     gpio_base = devm_platform_ioremap_resource(pdev, 0);
0244     if (IS_ERR(gpio_base))
0245         return PTR_ERR(gpio_base);
0246
0247     irq = platform_get_irq(pdev, 0);
0248     if (irq < 0)
0249         return irq;
0250
0251     priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
0252     priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
0253     priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
0254     priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
0255     priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
0256     priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
0257
0258     bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
0259
0260     gc = &priv->chip;
0261
0262     gc->owner = THIS_MODULE;
0263     gc->label = dev_name(&pdev->dev);
0264     gc->base = 0;
0265     gc->parent = &pdev->dev;
0266     gc->ngpio = 70;
0267     gc->direction_output = xlp_gpio_dir_output;
0268     gc->direction_input = xlp_gpio_dir_input;
0269     gc->set = xlp_gpio_set;
0270     gc->get = xlp_gpio_get;
0271
0272     spin_lock_init(&priv->lock);
0273
0274     girq = &gc->irq;
0275     girq->chip = &xlp_gpio_irq_chip;
0276     girq->parent_handler = xlp_gpio_generic_handler;
0277     girq->num_parents = 1;
0278     girq->parents = devm_kcalloc(&pdev->dev, 1,
0279                      sizeof(*girq->parents),
0280                      GFP_KERNEL);
0281     if (!girq->parents)
0282         return -ENOMEM;
0283     girq->parents[0] = irq;
0284     girq->first = 0;
0285     girq->default_type = IRQ_TYPE_NONE;
0286     girq->handler = handle_level_irq;
0287
0288     err = gpiochip_add_data(gc, priv);
0289     if (err < 0)
0290         return err;
0291
0292     dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
0293
0294     return 0;
0295 }
0296
0297 #ifdef CONFIG_ACPI
0298 static const struct acpi_device_id xlp_gpio_acpi_match[] = {
0299     { "BRCM9006" },
0300     { "CAV9006" },
0301     {},
0302 };
0303 MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
0304 #endif
0305
0306 static struct platform_driver xlp_gpio_driver = {
0307     .driver     = {
0308         .name   = "xlp-gpio",
0309         .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
0310     },
0311     .probe      = xlp_gpio_probe,
0312 };
0313 module_platform_driver(xlp_gpio_driver);
0314
0315 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
0316 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
0317 MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
0318 MODULE_LICENSE("GPL v2");