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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2017 Broadcom
0004  */
0005 
0006 #include <linux/gpio/driver.h>
0007 #include <linux/init.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/io.h>
0010 #include <linux/irq.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spinlock.h>
0015 
0016 #define IPROC_CCA_INT_F_GPIOINT     BIT(0)
0017 #define IPROC_CCA_INT_STS       0x20
0018 #define IPROC_CCA_INT_MASK      0x24
0019 
0020 #define IPROC_GPIO_CCA_DIN      0x0
0021 #define IPROC_GPIO_CCA_DOUT     0x4
0022 #define IPROC_GPIO_CCA_OUT_EN       0x8
0023 #define IPROC_GPIO_CCA_INT_LEVEL    0x10
0024 #define IPROC_GPIO_CCA_INT_LEVEL_MASK   0x14
0025 #define IPROC_GPIO_CCA_INT_EVENT    0x18
0026 #define IPROC_GPIO_CCA_INT_EVENT_MASK   0x1C
0027 #define IPROC_GPIO_CCA_INT_EDGE     0x24
0028 
0029 struct iproc_gpio_chip {
0030     struct irq_chip irqchip;
0031     struct gpio_chip gc;
0032     spinlock_t lock;
0033     struct device *dev;
0034     void __iomem *base;
0035     void __iomem *intr;
0036 };
0037 
0038 static inline struct iproc_gpio_chip *
0039 to_iproc_gpio(struct gpio_chip *gc)
0040 {
0041     return container_of(gc, struct iproc_gpio_chip, gc);
0042 }
0043 
0044 static void iproc_gpio_irq_ack(struct irq_data *d)
0045 {
0046     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0047     struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
0048     int pin = d->hwirq;
0049     unsigned long flags;
0050     u32 irq = d->irq;
0051     u32 irq_type, event_status = 0;
0052 
0053     spin_lock_irqsave(&chip->lock, flags);
0054     irq_type = irq_get_trigger_type(irq);
0055     if (irq_type & IRQ_TYPE_EDGE_BOTH) {
0056         event_status |= BIT(pin);
0057         writel_relaxed(event_status,
0058                    chip->base + IPROC_GPIO_CCA_INT_EVENT);
0059     }
0060     spin_unlock_irqrestore(&chip->lock, flags);
0061 }
0062 
0063 static void iproc_gpio_irq_unmask(struct irq_data *d)
0064 {
0065     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0066     struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
0067     int pin = d->hwirq;
0068     unsigned long flags;
0069     u32 irq = d->irq;
0070     u32 int_mask, irq_type, event_mask;
0071 
0072     spin_lock_irqsave(&chip->lock, flags);
0073     irq_type = irq_get_trigger_type(irq);
0074     event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
0075     int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
0076 
0077     if (irq_type & IRQ_TYPE_EDGE_BOTH) {
0078         event_mask |= 1 << pin;
0079         writel_relaxed(event_mask,
0080                    chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
0081     } else {
0082         int_mask |= 1 << pin;
0083         writel_relaxed(int_mask,
0084                    chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
0085     }
0086     spin_unlock_irqrestore(&chip->lock, flags);
0087 }
0088 
0089 static void iproc_gpio_irq_mask(struct irq_data *d)
0090 {
0091     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0092     struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
0093     int pin = d->hwirq;
0094     unsigned long flags;
0095     u32 irq = d->irq;
0096     u32 irq_type, int_mask, event_mask;
0097 
0098     spin_lock_irqsave(&chip->lock, flags);
0099     irq_type = irq_get_trigger_type(irq);
0100     event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
0101     int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
0102 
0103     if (irq_type & IRQ_TYPE_EDGE_BOTH) {
0104         event_mask &= ~BIT(pin);
0105         writel_relaxed(event_mask,
0106                    chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
0107     } else {
0108         int_mask &= ~BIT(pin);
0109         writel_relaxed(int_mask,
0110                    chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
0111     }
0112     spin_unlock_irqrestore(&chip->lock, flags);
0113 }
0114 
0115 static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type)
0116 {
0117     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0118     struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
0119     int pin = d->hwirq;
0120     unsigned long flags;
0121     u32 irq = d->irq;
0122     u32 event_pol, int_pol;
0123     int ret = 0;
0124 
0125     spin_lock_irqsave(&chip->lock, flags);
0126     switch (type & IRQ_TYPE_SENSE_MASK) {
0127     case IRQ_TYPE_EDGE_RISING:
0128         event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
0129         event_pol &= ~BIT(pin);
0130         writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
0131         break;
0132     case IRQ_TYPE_EDGE_FALLING:
0133         event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
0134         event_pol |= BIT(pin);
0135         writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
0136         break;
0137     case IRQ_TYPE_LEVEL_HIGH:
0138         int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
0139         int_pol &= ~BIT(pin);
0140         writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
0141         break;
0142     case IRQ_TYPE_LEVEL_LOW:
0143         int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
0144         int_pol |= BIT(pin);
0145         writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
0146         break;
0147     default:
0148         /* should not come here */
0149         ret = -EINVAL;
0150         goto out_unlock;
0151     }
0152 
0153     if (type & IRQ_TYPE_LEVEL_MASK)
0154         irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq);
0155     else if (type & IRQ_TYPE_EDGE_BOTH)
0156         irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq);
0157 
0158 out_unlock:
0159     spin_unlock_irqrestore(&chip->lock, flags);
0160 
0161     return ret;
0162 }
0163 
0164 static irqreturn_t iproc_gpio_irq_handler(int irq, void *data)
0165 {
0166     struct gpio_chip *gc = (struct gpio_chip *)data;
0167     struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
0168     int bit;
0169     unsigned long int_bits = 0;
0170     u32 int_status;
0171 
0172     /* go through the entire GPIOs and handle all interrupts */
0173     int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS);
0174     if (int_status & IPROC_CCA_INT_F_GPIOINT) {
0175         u32 event, level;
0176 
0177         /* Get level and edge interrupts */
0178         event =
0179             readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
0180         event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT);
0181         level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN);
0182         level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
0183         level &=
0184             readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
0185         int_bits = level | event;
0186 
0187         for_each_set_bit(bit, &int_bits, gc->ngpio)
0188             generic_handle_domain_irq(gc->irq.domain, bit);
0189     }
0190 
0191     return int_bits ? IRQ_HANDLED : IRQ_NONE;
0192 }
0193 
0194 static int iproc_gpio_probe(struct platform_device *pdev)
0195 {
0196     struct device *dev = &pdev->dev;
0197     struct device_node *dn = pdev->dev.of_node;
0198     struct iproc_gpio_chip *chip;
0199     u32 num_gpios;
0200     int irq, ret;
0201 
0202     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0203     if (!chip)
0204         return -ENOMEM;
0205 
0206     chip->dev = dev;
0207     platform_set_drvdata(pdev, chip);
0208     spin_lock_init(&chip->lock);
0209 
0210     chip->base = devm_platform_ioremap_resource(pdev, 0);
0211     if (IS_ERR(chip->base))
0212         return PTR_ERR(chip->base);
0213 
0214     ret = bgpio_init(&chip->gc, dev, 4,
0215              chip->base + IPROC_GPIO_CCA_DIN,
0216              chip->base + IPROC_GPIO_CCA_DOUT,
0217              NULL,
0218              chip->base + IPROC_GPIO_CCA_OUT_EN,
0219              NULL,
0220              0);
0221     if (ret) {
0222         dev_err(dev, "unable to init GPIO chip\n");
0223         return ret;
0224     }
0225 
0226     chip->gc.label = dev_name(dev);
0227     if (!of_property_read_u32(dn, "ngpios", &num_gpios))
0228         chip->gc.ngpio = num_gpios;
0229 
0230     irq = platform_get_irq(pdev, 0);
0231     if (irq > 0) {
0232         struct gpio_irq_chip *girq;
0233         struct irq_chip *irqc;
0234         u32 val;
0235 
0236         irqc = &chip->irqchip;
0237         irqc->name = dev_name(dev);
0238         irqc->irq_ack = iproc_gpio_irq_ack;
0239         irqc->irq_mask = iproc_gpio_irq_mask;
0240         irqc->irq_unmask = iproc_gpio_irq_unmask;
0241         irqc->irq_set_type = iproc_gpio_irq_set_type;
0242 
0243         chip->intr = devm_platform_ioremap_resource(pdev, 1);
0244         if (IS_ERR(chip->intr))
0245             return PTR_ERR(chip->intr);
0246 
0247         /* Enable GPIO interrupts for CCA GPIO */
0248         val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
0249         val |= IPROC_CCA_INT_F_GPIOINT;
0250         writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
0251 
0252         /*
0253          * Directly request the irq here instead of passing
0254          * a flow-handler because the irq is shared.
0255          */
0256         ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
0257                        IRQF_SHARED, chip->gc.label, &chip->gc);
0258         if (ret) {
0259             dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret);
0260             return ret;
0261         }
0262 
0263         girq = &chip->gc.irq;
0264         girq->chip = irqc;
0265         /* This will let us handle the parent IRQ in the driver */
0266         girq->parent_handler = NULL;
0267         girq->num_parents = 0;
0268         girq->parents = NULL;
0269         girq->default_type = IRQ_TYPE_NONE;
0270         girq->handler = handle_simple_irq;
0271     }
0272 
0273     ret = devm_gpiochip_add_data(dev, &chip->gc, chip);
0274     if (ret) {
0275         dev_err(dev, "unable to add GPIO chip\n");
0276         return ret;
0277     }
0278 
0279     return 0;
0280 }
0281 
0282 static int iproc_gpio_remove(struct platform_device *pdev)
0283 {
0284     struct iproc_gpio_chip *chip = platform_get_drvdata(pdev);
0285 
0286     if (chip->intr) {
0287         u32 val;
0288 
0289         val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
0290         val &= ~IPROC_CCA_INT_F_GPIOINT;
0291         writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
0292     }
0293 
0294     return 0;
0295 }
0296 
0297 static const struct of_device_id bcm_iproc_gpio_of_match[] = {
0298     { .compatible = "brcm,iproc-gpio-cca" },
0299     {}
0300 };
0301 MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match);
0302 
0303 static struct platform_driver bcm_iproc_gpio_driver = {
0304     .driver = {
0305         .name = "iproc-xgs-gpio",
0306         .of_match_table = bcm_iproc_gpio_of_match,
0307     },
0308     .probe = iproc_gpio_probe,
0309     .remove = iproc_gpio_remove,
0310 };
0311 
0312 module_platform_driver(bcm_iproc_gpio_driver);
0313 
0314 MODULE_DESCRIPTION("XGS IPROC GPIO driver");
0315 MODULE_LICENSE("GPL v2");
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