drivers/gpio/gpio-xgene-sb.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * AppliedMicro X-Gene SoC GPIO-Standby Driver
0004  *
0005  * Copyright (c) 2014, Applied Micro Circuits Corporation
0006  * Author:  Tin Huynh <tnhuynh@apm.com>.
0007  *      Y Vo <yvo@apm.com>.
0008  *      Quan Nguyen <qnguyen@apm.com>.
0009  */
0010
0011 #include <linux/module.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/acpi.h>
0017
0018 #include "gpiolib.h"
0019 #include "gpiolib-acpi.h"
0020
0021 /* Common property names */
0022 #define XGENE_NIRQ_PROPERTY     "apm,nr-irqs"
0023 #define XGENE_NGPIO_PROPERTY        "apm,nr-gpios"
0024 #define XGENE_IRQ_START_PROPERTY    "apm,irq-start"
0025
0026 #define XGENE_DFLT_MAX_NGPIO        22
0027 #define XGENE_DFLT_MAX_NIRQ     6
0028 #define XGENE_DFLT_IRQ_START_PIN    8
0029 #define GPIO_MASK(x)            (1U << ((x) % 32))
0030
0031 #define MPA_GPIO_INT_LVL        0x0290
0032 #define MPA_GPIO_OE_ADDR        0x029c
0033 #define MPA_GPIO_OUT_ADDR       0x02a0
0034 #define MPA_GPIO_IN_ADDR        0x02a4
0035 #define MPA_GPIO_SEL_LO         0x0294
0036
0037 #define GPIO_INT_LEVEL_H    0x000001
0038 #define GPIO_INT_LEVEL_L    0x000000
0039
0040 /**
0041  * struct xgene_gpio_sb - GPIO-Standby private data structure.
0042  * @gc:             memory-mapped GPIO controllers.
0043  * @regs:           GPIO register base offset
0044  * @irq_domain:         GPIO interrupt domain
0045  * @irq_start:          GPIO pin that start support interrupt
0046  * @nirq:           Number of GPIO pins that supports interrupt
0047  * @parent_irq_base:        Start parent HWIRQ
0048  */
0049 struct xgene_gpio_sb {
0050     struct gpio_chip    gc;
0051     void __iomem        *regs;
0052     struct irq_domain   *irq_domain;
0053     u16         irq_start;
0054     u16         nirq;
0055     u16         parent_irq_base;
0056 };
0057
0058 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
0059 #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
0060
0061 static void xgene_gpio_set_bit(struct gpio_chip *gc,
0062                 void __iomem *reg, u32 gpio, int val)
0063 {
0064     u32 data;
0065
0066     data = gc->read_reg(reg);
0067     if (val)
0068         data |= GPIO_MASK(gpio);
0069     else
0070         data &= ~GPIO_MASK(gpio);
0071     gc->write_reg(reg, data);
0072 }
0073
0074 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
0075 {
0076     struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
0077     int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
0078     int lvl_type = GPIO_INT_LEVEL_H;
0079
0080     switch (type & IRQ_TYPE_SENSE_MASK) {
0081     case IRQ_TYPE_EDGE_RISING:
0082     case IRQ_TYPE_LEVEL_HIGH:
0083         lvl_type = GPIO_INT_LEVEL_H;
0084         break;
0085     case IRQ_TYPE_EDGE_FALLING:
0086     case IRQ_TYPE_LEVEL_LOW:
0087         lvl_type = GPIO_INT_LEVEL_L;
0088         break;
0089     default:
0090         break;
0091     }
0092
0093     xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
0094             gpio * 2, 1);
0095     xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
0096             d->hwirq, lvl_type);
0097
0098     /* Propagate IRQ type setting to parent */
0099     if (type & IRQ_TYPE_EDGE_BOTH)
0100         return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
0101     else
0102         return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
0103 }
0104
0105 static struct irq_chip xgene_gpio_sb_irq_chip = {
0106     .name           = "sbgpio",
0107     .irq_eoi    = irq_chip_eoi_parent,
0108     .irq_mask       = irq_chip_mask_parent,
0109     .irq_unmask     = irq_chip_unmask_parent,
0110     .irq_set_type   = xgene_gpio_sb_irq_set_type,
0111 };
0112
0113 static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
0114 {
0115     struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
0116     struct irq_fwspec fwspec;
0117
0118     if ((gpio < priv->irq_start) ||
0119             (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
0120         return -ENXIO;
0121
0122     fwspec.fwnode = gc->parent->fwnode;
0123     fwspec.param_count = 2;
0124     fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
0125     fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
0126     return irq_create_fwspec_mapping(&fwspec);
0127 }
0128
0129 static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
0130                      struct irq_data *irq_data,
0131                      bool reserve)
0132 {
0133     struct xgene_gpio_sb *priv = d->host_data;
0134     u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
0135     int ret;
0136
0137     ret = gpiochip_lock_as_irq(&priv->gc, gpio);
0138     if (ret) {
0139         dev_err(priv->gc.parent,
0140         "Unable to configure XGene GPIO standby pin %d as IRQ\n",
0141                 gpio);
0142         return ret;
0143     }
0144
0145     xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
0146             gpio * 2, 1);
0147     return 0;
0148 }
0149
0150 static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
0151         struct irq_data *irq_data)
0152 {
0153     struct xgene_gpio_sb *priv = d->host_data;
0154     u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
0155
0156     gpiochip_unlock_as_irq(&priv->gc, gpio);
0157     xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
0158             gpio * 2, 0);
0159 }
0160
0161 static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
0162         struct irq_fwspec *fwspec,
0163         unsigned long *hwirq,
0164         unsigned int *type)
0165 {
0166     struct xgene_gpio_sb *priv = d->host_data;
0167
0168     if ((fwspec->param_count != 2) ||
0169         (fwspec->param[0] >= priv->nirq))
0170         return -EINVAL;
0171     *hwirq = fwspec->param[0];
0172     *type = fwspec->param[1];
0173     return 0;
0174 }
0175
0176 static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
0177                     unsigned int virq,
0178                     unsigned int nr_irqs, void *data)
0179 {
0180     struct irq_fwspec *fwspec = data;
0181     struct irq_fwspec parent_fwspec;
0182     struct xgene_gpio_sb *priv = domain->host_data;
0183     irq_hw_number_t hwirq;
0184     unsigned int i;
0185
0186     hwirq = fwspec->param[0];
0187     for (i = 0; i < nr_irqs; i++)
0188         irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
0189                 &xgene_gpio_sb_irq_chip, priv);
0190
0191     parent_fwspec.fwnode = domain->parent->fwnode;
0192     if (is_of_node(parent_fwspec.fwnode)) {
0193         parent_fwspec.param_count = 3;
0194         parent_fwspec.param[0] = 0;/* SPI */
0195         /* Skip SGIs and PPIs*/
0196         parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
0197         parent_fwspec.param[2] = fwspec->param[1];
0198     } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
0199         parent_fwspec.param_count = 2;
0200         parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
0201         parent_fwspec.param[1] = fwspec->param[1];
0202     } else
0203         return -EINVAL;
0204
0205     return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
0206             &parent_fwspec);
0207 }
0208
0209 static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
0210     .translate      = xgene_gpio_sb_domain_translate,
0211     .alloc          = xgene_gpio_sb_domain_alloc,
0212     .free           = irq_domain_free_irqs_common,
0213     .activate   = xgene_gpio_sb_domain_activate,
0214     .deactivate = xgene_gpio_sb_domain_deactivate,
0215 };
0216
0217 static int xgene_gpio_sb_probe(struct platform_device *pdev)
0218 {
0219     struct xgene_gpio_sb *priv;
0220     int ret;
0221     void __iomem *regs;
0222     struct irq_domain *parent_domain = NULL;
0223     u32 val32;
0224
0225     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0226     if (!priv)
0227         return -ENOMEM;
0228
0229     regs = devm_platform_ioremap_resource(pdev, 0);
0230     if (IS_ERR(regs))
0231         return PTR_ERR(regs);
0232
0233     priv->regs = regs;
0234
0235     ret = platform_get_irq(pdev, 0);
0236     if (ret > 0) {
0237         priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
0238         parent_domain = irq_get_irq_data(ret)->domain;
0239     }
0240     if (!parent_domain) {
0241         dev_err(&pdev->dev, "unable to obtain parent domain\n");
0242         return -ENODEV;
0243     }
0244
0245     ret = bgpio_init(&priv->gc, &pdev->dev, 4,
0246             regs + MPA_GPIO_IN_ADDR,
0247             regs + MPA_GPIO_OUT_ADDR, NULL,
0248             regs + MPA_GPIO_OE_ADDR, NULL, 0);
0249         if (ret)
0250                 return ret;
0251
0252     priv->gc.to_irq = xgene_gpio_sb_to_irq;
0253
0254     /* Retrieve start irq pin, use default if property not found */
0255     priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
0256     if (!device_property_read_u32(&pdev->dev,
0257                     XGENE_IRQ_START_PROPERTY, &val32))
0258         priv->irq_start = val32;
0259
0260     /* Retrieve number irqs, use default if property not found */
0261     priv->nirq = XGENE_DFLT_MAX_NIRQ;
0262     if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
0263         priv->nirq = val32;
0264
0265     /* Retrieve number gpio, use default if property not found */
0266     priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
0267     if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
0268         priv->gc.ngpio = val32;
0269
0270     dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
0271             priv->gc.ngpio, priv->nirq, priv->irq_start);
0272
0273     platform_set_drvdata(pdev, priv);
0274
0275     priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
0276                     0, priv->nirq, pdev->dev.fwnode,
0277                     &xgene_gpio_sb_domain_ops, priv);
0278     if (!priv->irq_domain)
0279         return -ENODEV;
0280
0281     priv->gc.irq.domain = priv->irq_domain;
0282
0283     ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
0284     if (ret) {
0285         dev_err(&pdev->dev,
0286             "failed to register X-Gene GPIO Standby driver\n");
0287         irq_domain_remove(priv->irq_domain);
0288         return ret;
0289     }
0290
0291     dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
0292
0293     /* Register interrupt handlers for GPIO signaled ACPI Events */
0294     acpi_gpiochip_request_interrupts(&priv->gc);
0295
0296     return ret;
0297 }
0298
0299 static int xgene_gpio_sb_remove(struct platform_device *pdev)
0300 {
0301     struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
0302
0303     acpi_gpiochip_free_interrupts(&priv->gc);
0304
0305     irq_domain_remove(priv->irq_domain);
0306
0307     return 0;
0308 }
0309
0310 static const struct of_device_id xgene_gpio_sb_of_match[] = {
0311     {.compatible = "apm,xgene-gpio-sb", },
0312     {},
0313 };
0314 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
0315
0316 #ifdef CONFIG_ACPI
0317 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
0318     {"APMC0D15", 0},
0319     {},
0320 };
0321 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
0322 #endif
0323
0324 static struct platform_driver xgene_gpio_sb_driver = {
0325     .driver = {
0326            .name = "xgene-gpio-sb",
0327            .of_match_table = xgene_gpio_sb_of_match,
0328            .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
0329            },
0330     .probe = xgene_gpio_sb_probe,
0331     .remove = xgene_gpio_sb_remove,
0332 };
0333 module_platform_driver(xgene_gpio_sb_driver);
0334
0335 MODULE_AUTHOR("AppliedMicro");
0336 MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
0337 MODULE_LICENSE("GPL");