0001
0002
0003
0004
0005
0006
0007
0008
0009 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0010
0011 #include <linux/gpio/driver.h>
0012 #include <linux/ioport.h>
0013 #include <linux/isa.h>
0014 #include <linux/module.h>
0015
0016 #define WB_GPIO_DRIVER_NAME KBUILD_MODNAME
0017
0018 #define WB_SIO_BASE 0x2e
0019 #define WB_SIO_BASE_HIGH 0x4e
0020
0021 #define WB_SIO_EXT_ENTER_KEY 0x87
0022 #define WB_SIO_EXT_EXIT_KEY 0xaa
0023
0024
0025
0026 #define WB_SIO_REG_LOGICAL 0x07
0027
0028 #define WB_SIO_REG_CHIP_MSB 0x20
0029 #define WB_SIO_REG_CHIP_LSB 0x21
0030
0031 #define WB_SIO_CHIP_ID_W83627UHG 0xa230
0032 #define WB_SIO_CHIP_ID_W83627UHG_MASK GENMASK(15, 4)
0033
0034 #define WB_SIO_REG_DPD 0x22
0035 #define WB_SIO_REG_DPD_UARTA 4
0036 #define WB_SIO_REG_DPD_UARTB 5
0037
0038 #define WB_SIO_REG_IDPD 0x23
0039 #define WB_SIO_REG_IDPD_UARTC 4
0040 #define WB_SIO_REG_IDPD_UARTD 5
0041 #define WB_SIO_REG_IDPD_UARTE 6
0042 #define WB_SIO_REG_IDPD_UARTF 7
0043
0044 #define WB_SIO_REG_GLOBAL_OPT 0x24
0045 #define WB_SIO_REG_GO_ENFDC 1
0046
0047 #define WB_SIO_REG_OVTGPIO3456 0x29
0048 #define WB_SIO_REG_OG3456_G3PP 3
0049 #define WB_SIO_REG_OG3456_G4PP 4
0050 #define WB_SIO_REG_OG3456_G5PP 5
0051 #define WB_SIO_REG_OG3456_G6PP 7
0052
0053 #define WB_SIO_REG_I2C_PS 0x2a
0054 #define WB_SIO_REG_I2CPS_I2CFS 1
0055
0056 #define WB_SIO_REG_GPIO1_MF 0x2c
0057 #define WB_SIO_REG_G1MF_G1PP 6
0058 #define WB_SIO_REG_G1MF_G2PP 7
0059 #define WB_SIO_REG_G1MF_FS_MASK GENMASK(1, 0)
0060 #define WB_SIO_REG_G1MF_FS_IR_OFF 0
0061 #define WB_SIO_REG_G1MF_FS_IR 1
0062 #define WB_SIO_REG_G1MF_FS_GPIO1 2
0063 #define WB_SIO_REG_G1MF_FS_UARTB 3
0064
0065
0066 #define WB_SIO_DEV_NONE 0xff
0067
0068
0069
0070
0071 #define WB_SIO_DEV_UARTB 0x03
0072 #define WB_SIO_UARTB_REG_ENABLE 0x30
0073 #define WB_SIO_UARTB_ENABLE_ON 0
0074
0075
0076 #define WB_SIO_DEV_UARTC 0x06
0077 #define WB_SIO_UARTC_REG_ENABLE 0x30
0078 #define WB_SIO_UARTC_ENABLE_ON 0
0079
0080
0081 #define WB_SIO_DEV_GPIO34 0x07
0082 #define WB_SIO_GPIO34_REG_ENABLE 0x30
0083 #define WB_SIO_GPIO34_ENABLE_3 0
0084 #define WB_SIO_GPIO34_ENABLE_4 1
0085 #define WB_SIO_GPIO34_REG_IO3 0xe0
0086 #define WB_SIO_GPIO34_REG_DATA3 0xe1
0087 #define WB_SIO_GPIO34_REG_INV3 0xe2
0088 #define WB_SIO_GPIO34_REG_IO4 0xe4
0089 #define WB_SIO_GPIO34_REG_DATA4 0xe5
0090 #define WB_SIO_GPIO34_REG_INV4 0xe6
0091
0092
0093 #define WB_SIO_DEV_WDGPIO56 0x08
0094 #define WB_SIO_WDGPIO56_REG_ENABLE 0x30
0095 #define WB_SIO_WDGPIO56_ENABLE_5 1
0096 #define WB_SIO_WDGPIO56_ENABLE_6 2
0097 #define WB_SIO_WDGPIO56_REG_IO5 0xe0
0098 #define WB_SIO_WDGPIO56_REG_DATA5 0xe1
0099 #define WB_SIO_WDGPIO56_REG_INV5 0xe2
0100 #define WB_SIO_WDGPIO56_REG_IO6 0xe4
0101 #define WB_SIO_WDGPIO56_REG_DATA6 0xe5
0102 #define WB_SIO_WDGPIO56_REG_INV6 0xe6
0103
0104
0105 #define WB_SIO_DEV_GPIO12 0x09
0106 #define WB_SIO_GPIO12_REG_ENABLE 0x30
0107 #define WB_SIO_GPIO12_ENABLE_1 0
0108 #define WB_SIO_GPIO12_ENABLE_2 1
0109 #define WB_SIO_GPIO12_REG_IO1 0xe0
0110 #define WB_SIO_GPIO12_REG_DATA1 0xe1
0111 #define WB_SIO_GPIO12_REG_INV1 0xe2
0112 #define WB_SIO_GPIO12_REG_IO2 0xe4
0113 #define WB_SIO_GPIO12_REG_DATA2 0xe5
0114 #define WB_SIO_GPIO12_REG_INV2 0xe6
0115
0116
0117 #define WB_SIO_DEV_UARTD 0x0d
0118 #define WB_SIO_UARTD_REG_ENABLE 0x30
0119 #define WB_SIO_UARTD_ENABLE_ON 0
0120
0121
0122 #define WB_SIO_DEV_UARTE 0x0e
0123 #define WB_SIO_UARTE_REG_ENABLE 0x30
0124 #define WB_SIO_UARTE_ENABLE_ON 0
0125
0126
0127
0128
0129
0130 struct winbond_gpio_params {
0131 unsigned long base;
0132 unsigned long gpios;
0133 unsigned long ppgpios;
0134 unsigned long odgpios;
0135 bool pledgpio;
0136 bool beepgpio;
0137 bool i2cgpio;
0138 };
0139
0140 static struct winbond_gpio_params params;
0141
0142 static int winbond_sio_enter(unsigned long base)
0143 {
0144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME))
0145 return -EBUSY;
0146
0147
0148
0149
0150
0151 outb(WB_SIO_EXT_ENTER_KEY, base);
0152 outb(WB_SIO_EXT_ENTER_KEY, base);
0153
0154 return 0;
0155 }
0156
0157 static void winbond_sio_select_logical(unsigned long base, u8 dev)
0158 {
0159 outb(WB_SIO_REG_LOGICAL, base);
0160 outb(dev, base + 1);
0161 }
0162
0163 static void winbond_sio_leave(unsigned long base)
0164 {
0165 outb(WB_SIO_EXT_EXIT_KEY, base);
0166
0167 release_region(base, 2);
0168 }
0169
0170 static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data)
0171 {
0172 outb(reg, base);
0173 outb(data, base + 1);
0174 }
0175
0176 static u8 winbond_sio_reg_read(unsigned long base, u8 reg)
0177 {
0178 outb(reg, base);
0179 return inb(base + 1);
0180 }
0181
0182 static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit)
0183 {
0184 u8 val;
0185
0186 val = winbond_sio_reg_read(base, reg);
0187 val |= BIT(bit);
0188 winbond_sio_reg_write(base, reg, val);
0189 }
0190
0191 static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit)
0192 {
0193 u8 val;
0194
0195 val = winbond_sio_reg_read(base, reg);
0196 val &= ~BIT(bit);
0197 winbond_sio_reg_write(base, reg, val);
0198 }
0199
0200 static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit)
0201 {
0202 return winbond_sio_reg_read(base, reg) & BIT(bit);
0203 }
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217 struct winbond_gpio_port_conflict {
0218 const char *name;
0219 u8 dev;
0220 u8 testreg;
0221 u8 testbit;
0222 bool warnonly;
0223 };
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239 struct winbond_gpio_info {
0240 u8 dev;
0241 u8 enablereg;
0242 u8 enablebit;
0243 u8 outputreg;
0244 u8 outputppbit;
0245 u8 ioreg;
0246 u8 invreg;
0247 u8 datareg;
0248 struct winbond_gpio_port_conflict conflict;
0249 };
0250
0251 static const struct winbond_gpio_info winbond_gpio_infos[6] = {
0252 {
0253 .dev = WB_SIO_DEV_GPIO12,
0254 .enablereg = WB_SIO_GPIO12_REG_ENABLE,
0255 .enablebit = WB_SIO_GPIO12_ENABLE_1,
0256 .outputreg = WB_SIO_REG_GPIO1_MF,
0257 .outputppbit = WB_SIO_REG_G1MF_G1PP,
0258 .ioreg = WB_SIO_GPIO12_REG_IO1,
0259 .invreg = WB_SIO_GPIO12_REG_INV1,
0260 .datareg = WB_SIO_GPIO12_REG_DATA1,
0261 .conflict = {
0262 .name = "UARTB",
0263 .dev = WB_SIO_DEV_UARTB,
0264 .testreg = WB_SIO_UARTB_REG_ENABLE,
0265 .testbit = WB_SIO_UARTB_ENABLE_ON,
0266 .warnonly = true
0267 }
0268 },
0269 {
0270 .dev = WB_SIO_DEV_GPIO12,
0271 .enablereg = WB_SIO_GPIO12_REG_ENABLE,
0272 .enablebit = WB_SIO_GPIO12_ENABLE_2,
0273 .outputreg = WB_SIO_REG_GPIO1_MF,
0274 .outputppbit = WB_SIO_REG_G1MF_G2PP,
0275 .ioreg = WB_SIO_GPIO12_REG_IO2,
0276 .invreg = WB_SIO_GPIO12_REG_INV2,
0277 .datareg = WB_SIO_GPIO12_REG_DATA2
0278
0279 },
0280 {
0281 .dev = WB_SIO_DEV_GPIO34,
0282 .enablereg = WB_SIO_GPIO34_REG_ENABLE,
0283 .enablebit = WB_SIO_GPIO34_ENABLE_3,
0284 .outputreg = WB_SIO_REG_OVTGPIO3456,
0285 .outputppbit = WB_SIO_REG_OG3456_G3PP,
0286 .ioreg = WB_SIO_GPIO34_REG_IO3,
0287 .invreg = WB_SIO_GPIO34_REG_INV3,
0288 .datareg = WB_SIO_GPIO34_REG_DATA3,
0289 .conflict = {
0290 .name = "UARTC",
0291 .dev = WB_SIO_DEV_UARTC,
0292 .testreg = WB_SIO_UARTC_REG_ENABLE,
0293 .testbit = WB_SIO_UARTC_ENABLE_ON,
0294 .warnonly = true
0295 }
0296 },
0297 {
0298 .dev = WB_SIO_DEV_GPIO34,
0299 .enablereg = WB_SIO_GPIO34_REG_ENABLE,
0300 .enablebit = WB_SIO_GPIO34_ENABLE_4,
0301 .outputreg = WB_SIO_REG_OVTGPIO3456,
0302 .outputppbit = WB_SIO_REG_OG3456_G4PP,
0303 .ioreg = WB_SIO_GPIO34_REG_IO4,
0304 .invreg = WB_SIO_GPIO34_REG_INV4,
0305 .datareg = WB_SIO_GPIO34_REG_DATA4,
0306 .conflict = {
0307 .name = "UARTD",
0308 .dev = WB_SIO_DEV_UARTD,
0309 .testreg = WB_SIO_UARTD_REG_ENABLE,
0310 .testbit = WB_SIO_UARTD_ENABLE_ON,
0311 .warnonly = true
0312 }
0313 },
0314 {
0315 .dev = WB_SIO_DEV_WDGPIO56,
0316 .enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
0317 .enablebit = WB_SIO_WDGPIO56_ENABLE_5,
0318 .outputreg = WB_SIO_REG_OVTGPIO3456,
0319 .outputppbit = WB_SIO_REG_OG3456_G5PP,
0320 .ioreg = WB_SIO_WDGPIO56_REG_IO5,
0321 .invreg = WB_SIO_WDGPIO56_REG_INV5,
0322 .datareg = WB_SIO_WDGPIO56_REG_DATA5,
0323 .conflict = {
0324 .name = "UARTE",
0325 .dev = WB_SIO_DEV_UARTE,
0326 .testreg = WB_SIO_UARTE_REG_ENABLE,
0327 .testbit = WB_SIO_UARTE_ENABLE_ON,
0328 .warnonly = true
0329 }
0330 },
0331 {
0332 .dev = WB_SIO_DEV_WDGPIO56,
0333 .enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
0334 .enablebit = WB_SIO_WDGPIO56_ENABLE_6,
0335 .outputreg = WB_SIO_REG_OVTGPIO3456,
0336 .outputppbit = WB_SIO_REG_OG3456_G6PP,
0337 .ioreg = WB_SIO_WDGPIO56_REG_IO6,
0338 .invreg = WB_SIO_WDGPIO56_REG_INV6,
0339 .datareg = WB_SIO_WDGPIO56_REG_DATA6,
0340 .conflict = {
0341 .name = "FDC",
0342 .dev = WB_SIO_DEV_NONE,
0343 .testreg = WB_SIO_REG_GLOBAL_OPT,
0344 .testbit = WB_SIO_REG_GO_ENFDC,
0345 .warnonly = false
0346 }
0347 }
0348 };
0349
0350
0351 static bool winbond_gpio_get_info(unsigned int *gpio_num,
0352 const struct winbond_gpio_info **info)
0353 {
0354 bool allow_changing = true;
0355 unsigned long i;
0356
0357 for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG) {
0358 if (*gpio_num < 8)
0359 break;
0360
0361 *gpio_num -= 8;
0362 }
0363
0364 *info = &winbond_gpio_infos[i];
0365
0366
0367
0368
0369
0370
0371 if (i == 1) {
0372 if (*gpio_num == 0 && !params.pledgpio)
0373 allow_changing = false;
0374 else if (*gpio_num == 1 && !params.beepgpio)
0375 allow_changing = false;
0376 else if ((*gpio_num == 5 || *gpio_num == 6) && !params.i2cgpio)
0377 allow_changing = false;
0378 }
0379
0380 return allow_changing;
0381 }
0382
0383 static int winbond_gpio_get(struct gpio_chip *gc, unsigned int offset)
0384 {
0385 unsigned long *base = gpiochip_get_data(gc);
0386 const struct winbond_gpio_info *info;
0387 bool val;
0388 int ret;
0389
0390 winbond_gpio_get_info(&offset, &info);
0391
0392 ret = winbond_sio_enter(*base);
0393 if (ret)
0394 return ret;
0395
0396 winbond_sio_select_logical(*base, info->dev);
0397
0398 val = winbond_sio_reg_btest(*base, info->datareg, offset);
0399 if (winbond_sio_reg_btest(*base, info->invreg, offset))
0400 val = !val;
0401
0402 winbond_sio_leave(*base);
0403
0404 return val;
0405 }
0406
0407 static int winbond_gpio_direction_in(struct gpio_chip *gc, unsigned int offset)
0408 {
0409 unsigned long *base = gpiochip_get_data(gc);
0410 const struct winbond_gpio_info *info;
0411 int ret;
0412
0413 if (!winbond_gpio_get_info(&offset, &info))
0414 return -EACCES;
0415
0416 ret = winbond_sio_enter(*base);
0417 if (ret)
0418 return ret;
0419
0420 winbond_sio_select_logical(*base, info->dev);
0421
0422 winbond_sio_reg_bset(*base, info->ioreg, offset);
0423
0424 winbond_sio_leave(*base);
0425
0426 return 0;
0427 }
0428
0429 static int winbond_gpio_direction_out(struct gpio_chip *gc,
0430 unsigned int offset,
0431 int val)
0432 {
0433 unsigned long *base = gpiochip_get_data(gc);
0434 const struct winbond_gpio_info *info;
0435 int ret;
0436
0437 if (!winbond_gpio_get_info(&offset, &info))
0438 return -EACCES;
0439
0440 ret = winbond_sio_enter(*base);
0441 if (ret)
0442 return ret;
0443
0444 winbond_sio_select_logical(*base, info->dev);
0445
0446 winbond_sio_reg_bclear(*base, info->ioreg, offset);
0447
0448 if (winbond_sio_reg_btest(*base, info->invreg, offset))
0449 val = !val;
0450
0451 if (val)
0452 winbond_sio_reg_bset(*base, info->datareg, offset);
0453 else
0454 winbond_sio_reg_bclear(*base, info->datareg, offset);
0455
0456 winbond_sio_leave(*base);
0457
0458 return 0;
0459 }
0460
0461 static void winbond_gpio_set(struct gpio_chip *gc, unsigned int offset,
0462 int val)
0463 {
0464 unsigned long *base = gpiochip_get_data(gc);
0465 const struct winbond_gpio_info *info;
0466
0467 if (!winbond_gpio_get_info(&offset, &info))
0468 return;
0469
0470 if (winbond_sio_enter(*base) != 0)
0471 return;
0472
0473 winbond_sio_select_logical(*base, info->dev);
0474
0475 if (winbond_sio_reg_btest(*base, info->invreg, offset))
0476 val = !val;
0477
0478 if (val)
0479 winbond_sio_reg_bset(*base, info->datareg, offset);
0480 else
0481 winbond_sio_reg_bclear(*base, info->datareg, offset);
0482
0483 winbond_sio_leave(*base);
0484 }
0485
0486 static struct gpio_chip winbond_gpio_chip = {
0487 .base = -1,
0488 .label = WB_GPIO_DRIVER_NAME,
0489 .owner = THIS_MODULE,
0490 .can_sleep = true,
0491 .get = winbond_gpio_get,
0492 .direction_input = winbond_gpio_direction_in,
0493 .set = winbond_gpio_set,
0494 .direction_output = winbond_gpio_direction_out,
0495 };
0496
0497 static void winbond_gpio_configure_port0_pins(unsigned long base)
0498 {
0499 unsigned int val;
0500
0501 val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF);
0502 if ((val & WB_SIO_REG_G1MF_FS_MASK) == WB_SIO_REG_G1MF_FS_GPIO1)
0503 return;
0504
0505 pr_warn("GPIO1 pins were connected to something else (%.2x), fixing\n",
0506 val);
0507
0508 val &= ~WB_SIO_REG_G1MF_FS_MASK;
0509 val |= WB_SIO_REG_G1MF_FS_GPIO1;
0510
0511 winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val);
0512 }
0513
0514 static void winbond_gpio_configure_port1_check_i2c(unsigned long base)
0515 {
0516 params.i2cgpio = !winbond_sio_reg_btest(base, WB_SIO_REG_I2C_PS,
0517 WB_SIO_REG_I2CPS_I2CFS);
0518 if (!params.i2cgpio)
0519 pr_warn("disabling GPIO2.5 and GPIO2.6 as I2C is enabled\n");
0520 }
0521
0522 static bool winbond_gpio_configure_port(unsigned long base, unsigned int idx)
0523 {
0524 const struct winbond_gpio_info *info = &winbond_gpio_infos[idx];
0525 const struct winbond_gpio_port_conflict *conflict = &info->conflict;
0526
0527
0528 if (conflict->name != NULL) {
0529 if (conflict->dev != WB_SIO_DEV_NONE)
0530 winbond_sio_select_logical(base, conflict->dev);
0531
0532 if (winbond_sio_reg_btest(base, conflict->testreg,
0533 conflict->testbit)) {
0534 if (conflict->warnonly)
0535 pr_warn("enabled GPIO%u share pins with active %s\n",
0536 idx + 1, conflict->name);
0537 else {
0538 pr_warn("disabling GPIO%u as %s is enabled\n",
0539 idx + 1, conflict->name);
0540 return false;
0541 }
0542 }
0543 }
0544
0545
0546 if (idx == 0)
0547 winbond_gpio_configure_port0_pins(base);
0548 else if (idx == 1)
0549 winbond_gpio_configure_port1_check_i2c(base);
0550
0551 winbond_sio_select_logical(base, info->dev);
0552
0553 winbond_sio_reg_bset(base, info->enablereg, info->enablebit);
0554
0555 if (params.ppgpios & BIT(idx))
0556 winbond_sio_reg_bset(base, info->outputreg,
0557 info->outputppbit);
0558 else if (params.odgpios & BIT(idx))
0559 winbond_sio_reg_bclear(base, info->outputreg,
0560 info->outputppbit);
0561 else
0562 pr_notice("GPIO%u pins are %s\n", idx + 1,
0563 winbond_sio_reg_btest(base, info->outputreg,
0564 info->outputppbit) ?
0565 "push-pull" :
0566 "open drain");
0567
0568 return true;
0569 }
0570
0571 static int winbond_gpio_configure(unsigned long base)
0572 {
0573 unsigned long i;
0574
0575 for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG)
0576 if (!winbond_gpio_configure_port(base, i))
0577 __clear_bit(i, ¶ms.gpios);
0578
0579 if (!params.gpios) {
0580 pr_err("please use 'gpios' module parameter to select some active GPIO ports to enable\n");
0581 return -EINVAL;
0582 }
0583
0584 return 0;
0585 }
0586
0587 static int winbond_gpio_check_chip(unsigned long base)
0588 {
0589 int ret;
0590 unsigned int chip;
0591
0592 ret = winbond_sio_enter(base);
0593 if (ret)
0594 return ret;
0595
0596 chip = winbond_sio_reg_read(base, WB_SIO_REG_CHIP_MSB) << 8;
0597 chip |= winbond_sio_reg_read(base, WB_SIO_REG_CHIP_LSB);
0598
0599 pr_notice("chip ID at %lx is %.4x\n", base, chip);
0600
0601 if ((chip & WB_SIO_CHIP_ID_W83627UHG_MASK) !=
0602 WB_SIO_CHIP_ID_W83627UHG) {
0603 pr_err("not an our chip\n");
0604 ret = -ENODEV;
0605 }
0606
0607 winbond_sio_leave(base);
0608
0609 return ret;
0610 }
0611
0612 static int winbond_gpio_imatch(struct device *dev, unsigned int id)
0613 {
0614 unsigned long gpios_rem;
0615 int ret;
0616
0617 gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1,
0618 0);
0619 if (gpios_rem) {
0620 pr_warn("unknown ports (%lx) enabled in GPIO ports bitmask\n",
0621 gpios_rem);
0622 params.gpios &= ~gpios_rem;
0623 }
0624
0625 if (params.ppgpios & params.odgpios) {
0626 pr_err("some GPIO ports are set both to push-pull and open drain mode at the same time\n");
0627 return 0;
0628 }
0629
0630 if (params.base != 0)
0631 return winbond_gpio_check_chip(params.base) == 0;
0632
0633
0634
0635
0636
0637 params.base = WB_SIO_BASE;
0638 ret = winbond_gpio_check_chip(params.base);
0639 if (ret == 0)
0640 return 1;
0641 if (ret != -ENODEV && ret != -EBUSY)
0642 return 0;
0643
0644 params.base = WB_SIO_BASE_HIGH;
0645 return winbond_gpio_check_chip(params.base) == 0;
0646 }
0647
0648 static int winbond_gpio_iprobe(struct device *dev, unsigned int id)
0649 {
0650 int ret;
0651
0652 if (params.base == 0)
0653 return -EINVAL;
0654
0655 ret = winbond_sio_enter(params.base);
0656 if (ret)
0657 return ret;
0658
0659 ret = winbond_gpio_configure(params.base);
0660
0661 winbond_sio_leave(params.base);
0662
0663 if (ret)
0664 return ret;
0665
0666
0667
0668
0669
0670
0671 winbond_gpio_chip.ngpio = hweight_long(params.gpios) * 8;
0672
0673
0674
0675
0676
0677 if (params.gpios & BIT(5))
0678 winbond_gpio_chip.ngpio -= (8 - 5);
0679
0680 winbond_gpio_chip.parent = dev;
0681
0682 return devm_gpiochip_add_data(dev, &winbond_gpio_chip, ¶ms.base);
0683 }
0684
0685 static struct isa_driver winbond_gpio_idriver = {
0686 .driver = {
0687 .name = WB_GPIO_DRIVER_NAME,
0688 },
0689 .match = winbond_gpio_imatch,
0690 .probe = winbond_gpio_iprobe,
0691 };
0692
0693 module_isa_driver(winbond_gpio_idriver, 1);
0694
0695 module_param_named(base, params.base, ulong, 0444);
0696 MODULE_PARM_DESC(base,
0697 "I/O port base (when unset - probe chip default ones)");
0698
0699
0700 module_param_named(gpios, params.gpios, ulong, 0444);
0701 MODULE_PARM_DESC(gpios,
0702 "bitmask of GPIO ports to enable (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
0703
0704
0705
0706
0707
0708
0709 module_param_named(ppgpios, params.ppgpios, ulong, 0444);
0710 MODULE_PARM_DESC(ppgpios,
0711 "bitmask of GPIO ports to set to push-pull mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
0712
0713 module_param_named(odgpios, params.odgpios, ulong, 0444);
0714 MODULE_PARM_DESC(odgpios,
0715 "bitmask of GPIO ports to set to open drain mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
0716
0717
0718
0719
0720
0721
0722
0723 module_param_named(pledgpio, params.pledgpio, bool, 0644);
0724 MODULE_PARM_DESC(pledgpio,
0725 "enable changing value of GPIO2.0 bit (Power LED), default no.");
0726
0727 module_param_named(beepgpio, params.beepgpio, bool, 0644);
0728 MODULE_PARM_DESC(beepgpio,
0729 "enable changing value of GPIO2.1 bit (BEEP), default no.");
0730
0731 MODULE_AUTHOR("Maciej S. Szmigiero <mail@maciej.szmigiero.name>");
0732 MODULE_DESCRIPTION("GPIO interface for Winbond Super I/O chips");
0733 MODULE_LICENSE("GPL");