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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Whiskey Cove PMIC GPIO Driver
0004  *
0005  * This driver is written based on gpio-crystalcove.c
0006  *
0007  * Copyright (C) 2016 Intel Corporation. All rights reserved.
0008  */
0009 
0010 #include <linux/bitops.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/mfd/intel_soc_pmic.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/seq_file.h>
0018 
0019 /*
0020  * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
0021  * Bank 0: Pin  0 - 6
0022  * Bank 1: Pin  7 - 10
0023  * Bank 2: Pin 11 - 12
0024  * Each pin has one output control register and one input control register.
0025  */
0026 #define BANK0_NR_PINS       7
0027 #define BANK1_NR_PINS       4
0028 #define BANK2_NR_PINS       2
0029 #define WCOVE_GPIO_NUM      (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
0030 #define WCOVE_VGPIO_NUM     94
0031 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
0032 #define GPIO_OUT_CTRL_BASE  0x4e44
0033 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
0034 #define GPIO_IN_CTRL_BASE   0x4e51
0035 
0036 /*
0037  * GPIO interrupts are organized in two groups:
0038  * Group 0: Bank 0 pins (Pin 0 - 6)
0039  * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
0040  * Each group has two registers (one bit per pin): status and mask.
0041  */
0042 #define GROUP0_NR_IRQS      7
0043 #define GROUP1_NR_IRQS      6
0044 #define IRQ_MASK_BASE       0x4e19
0045 #define IRQ_STATUS_BASE     0x4e0b
0046 #define GPIO_IRQ0_MASK      GENMASK(6, 0)
0047 #define GPIO_IRQ1_MASK      GENMASK(5, 0)
0048 #define UPDATE_IRQ_TYPE     BIT(0)
0049 #define UPDATE_IRQ_MASK     BIT(1)
0050 
0051 #define CTLI_INTCNT_DIS     (0 << 1)
0052 #define CTLI_INTCNT_NE      (1 << 1)
0053 #define CTLI_INTCNT_PE      (2 << 1)
0054 #define CTLI_INTCNT_BE      (3 << 1)
0055 
0056 #define CTLO_DIR_IN     (0 << 5)
0057 #define CTLO_DIR_OUT        (1 << 5)
0058 
0059 #define CTLO_DRV_MASK       (1 << 4)
0060 #define CTLO_DRV_OD     (0 << 4)
0061 #define CTLO_DRV_CMOS       (1 << 4)
0062 
0063 #define CTLO_DRV_REN        (1 << 3)
0064 
0065 #define CTLO_RVAL_2KDOWN    (0 << 1)
0066 #define CTLO_RVAL_2KUP      (1 << 1)
0067 #define CTLO_RVAL_50KDOWN   (2 << 1)
0068 #define CTLO_RVAL_50KUP     (3 << 1)
0069 
0070 #define CTLO_INPUT_SET      (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
0071 #define CTLO_OUTPUT_SET     (CTLO_DIR_OUT | CTLO_INPUT_SET)
0072 
0073 enum ctrl_register {
0074     CTRL_IN,
0075     CTRL_OUT,
0076     IRQ_STATUS,
0077     IRQ_MASK,
0078 };
0079 
0080 /*
0081  * struct wcove_gpio - Whiskey Cove GPIO controller
0082  * @buslock: for bus lock/sync and unlock.
0083  * @chip: the abstract gpio_chip structure.
0084  * @dev: the gpio device
0085  * @regmap: the regmap from the parent device.
0086  * @regmap_irq_chip: the regmap of the gpio irq chip.
0087  * @update: pending IRQ setting update, to be written to the chip upon unlock.
0088  * @intcnt: the Interrupt Detect value to be written.
0089  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
0090  */
0091 struct wcove_gpio {
0092     struct mutex buslock;
0093     struct gpio_chip chip;
0094     struct device *dev;
0095     struct regmap *regmap;
0096     struct regmap_irq_chip_data *regmap_irq_chip;
0097     int update;
0098     int intcnt;
0099     bool set_irq_mask;
0100 };
0101 
0102 static inline int to_reg(int gpio, enum ctrl_register type)
0103 {
0104     unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE;
0105 
0106     if (gpio >= WCOVE_GPIO_NUM)
0107         return -EOPNOTSUPP;
0108 
0109     return reg + gpio;
0110 }
0111 
0112 static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask)
0113 {
0114     unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE;
0115 
0116     if (gpio < GROUP0_NR_IRQS) {
0117         reg += 0;
0118         *mask = BIT(gpio);
0119     } else {
0120         reg += 1;
0121         *mask = BIT(gpio - GROUP0_NR_IRQS);
0122     }
0123 
0124     return reg;
0125 }
0126 
0127 static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio)
0128 {
0129     unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask);
0130 
0131     if (wg->set_irq_mask)
0132         regmap_set_bits(wg->regmap, reg, mask);
0133     else
0134         regmap_clear_bits(wg->regmap, reg, mask);
0135 }
0136 
0137 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio)
0138 {
0139     int reg = to_reg(gpio, CTRL_IN);
0140 
0141     regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
0142 }
0143 
0144 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
0145 {
0146     struct wcove_gpio *wg = gpiochip_get_data(chip);
0147     int reg = to_reg(gpio, CTRL_OUT);
0148 
0149     if (reg < 0)
0150         return 0;
0151 
0152     return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
0153 }
0154 
0155 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
0156                     int value)
0157 {
0158     struct wcove_gpio *wg = gpiochip_get_data(chip);
0159     int reg = to_reg(gpio, CTRL_OUT);
0160 
0161     if (reg < 0)
0162         return 0;
0163 
0164     return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
0165 }
0166 
0167 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
0168 {
0169     struct wcove_gpio *wg = gpiochip_get_data(chip);
0170     unsigned int val;
0171     int ret, reg = to_reg(gpio, CTRL_OUT);
0172 
0173     if (reg < 0)
0174         return GPIO_LINE_DIRECTION_OUT;
0175 
0176     ret = regmap_read(wg->regmap, reg, &val);
0177     if (ret)
0178         return ret;
0179 
0180     if (val & CTLO_DIR_OUT)
0181         return GPIO_LINE_DIRECTION_OUT;
0182 
0183     return GPIO_LINE_DIRECTION_IN;
0184 }
0185 
0186 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
0187 {
0188     struct wcove_gpio *wg = gpiochip_get_data(chip);
0189     unsigned int val;
0190     int ret, reg = to_reg(gpio, CTRL_IN);
0191 
0192     if (reg < 0)
0193         return 0;
0194 
0195     ret = regmap_read(wg->regmap, reg, &val);
0196     if (ret)
0197         return ret;
0198 
0199     return val & 0x1;
0200 }
0201 
0202 static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
0203 {
0204     struct wcove_gpio *wg = gpiochip_get_data(chip);
0205     int reg = to_reg(gpio, CTRL_OUT);
0206 
0207     if (reg < 0)
0208         return;
0209 
0210     if (value)
0211         regmap_set_bits(wg->regmap, reg, 1);
0212     else
0213         regmap_clear_bits(wg->regmap, reg, 1);
0214 }
0215 
0216 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
0217                  unsigned long config)
0218 {
0219     struct wcove_gpio *wg = gpiochip_get_data(chip);
0220     int reg = to_reg(gpio, CTRL_OUT);
0221 
0222     if (reg < 0)
0223         return 0;
0224 
0225     switch (pinconf_to_config_param(config)) {
0226     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0227         return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
0228                       CTLO_DRV_OD);
0229     case PIN_CONFIG_DRIVE_PUSH_PULL:
0230         return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
0231                       CTLO_DRV_CMOS);
0232     default:
0233         break;
0234     }
0235 
0236     return -ENOTSUPP;
0237 }
0238 
0239 static int wcove_irq_type(struct irq_data *data, unsigned int type)
0240 {
0241     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0242     struct wcove_gpio *wg = gpiochip_get_data(chip);
0243     irq_hw_number_t gpio = irqd_to_hwirq(data);
0244 
0245     if (gpio >= WCOVE_GPIO_NUM)
0246         return 0;
0247 
0248     switch (type) {
0249     case IRQ_TYPE_NONE:
0250         wg->intcnt = CTLI_INTCNT_DIS;
0251         break;
0252     case IRQ_TYPE_EDGE_BOTH:
0253         wg->intcnt = CTLI_INTCNT_BE;
0254         break;
0255     case IRQ_TYPE_EDGE_RISING:
0256         wg->intcnt = CTLI_INTCNT_PE;
0257         break;
0258     case IRQ_TYPE_EDGE_FALLING:
0259         wg->intcnt = CTLI_INTCNT_NE;
0260         break;
0261     default:
0262         return -EINVAL;
0263     }
0264 
0265     wg->update |= UPDATE_IRQ_TYPE;
0266 
0267     return 0;
0268 }
0269 
0270 static void wcove_bus_lock(struct irq_data *data)
0271 {
0272     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0273     struct wcove_gpio *wg = gpiochip_get_data(chip);
0274 
0275     mutex_lock(&wg->buslock);
0276 }
0277 
0278 static void wcove_bus_sync_unlock(struct irq_data *data)
0279 {
0280     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0281     struct wcove_gpio *wg = gpiochip_get_data(chip);
0282     irq_hw_number_t gpio = irqd_to_hwirq(data);
0283 
0284     if (wg->update & UPDATE_IRQ_TYPE)
0285         wcove_update_irq_ctrl(wg, gpio);
0286     if (wg->update & UPDATE_IRQ_MASK)
0287         wcove_update_irq_mask(wg, gpio);
0288     wg->update = 0;
0289 
0290     mutex_unlock(&wg->buslock);
0291 }
0292 
0293 static void wcove_irq_unmask(struct irq_data *data)
0294 {
0295     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0296     struct wcove_gpio *wg = gpiochip_get_data(chip);
0297     irq_hw_number_t gpio = irqd_to_hwirq(data);
0298 
0299     if (gpio >= WCOVE_GPIO_NUM)
0300         return;
0301 
0302     gpiochip_enable_irq(chip, gpio);
0303 
0304     wg->set_irq_mask = false;
0305     wg->update |= UPDATE_IRQ_MASK;
0306 }
0307 
0308 static void wcove_irq_mask(struct irq_data *data)
0309 {
0310     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0311     struct wcove_gpio *wg = gpiochip_get_data(chip);
0312     irq_hw_number_t gpio = irqd_to_hwirq(data);
0313 
0314     if (gpio >= WCOVE_GPIO_NUM)
0315         return;
0316 
0317     wg->set_irq_mask = true;
0318     wg->update |= UPDATE_IRQ_MASK;
0319 
0320     gpiochip_disable_irq(chip, gpio);
0321 }
0322 
0323 static const struct irq_chip wcove_irqchip = {
0324     .name           = "Whiskey Cove",
0325     .irq_mask       = wcove_irq_mask,
0326     .irq_unmask     = wcove_irq_unmask,
0327     .irq_set_type       = wcove_irq_type,
0328     .irq_bus_lock       = wcove_bus_lock,
0329     .irq_bus_sync_unlock    = wcove_bus_sync_unlock,
0330     .flags          = IRQCHIP_IMMUTABLE,
0331     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0332 };
0333 
0334 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
0335 {
0336     struct wcove_gpio *wg = (struct wcove_gpio *)data;
0337     unsigned int virq, gpio;
0338     unsigned long pending;
0339     u8 p[2];
0340 
0341     if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
0342         dev_err(wg->dev, "Failed to read irq status register\n");
0343         return IRQ_NONE;
0344     }
0345 
0346     pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
0347     if (!pending)
0348         return IRQ_NONE;
0349 
0350     /* Iterate until no interrupt is pending */
0351     while (pending) {
0352         /* One iteration is for all pending bits */
0353         for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) {
0354             unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask);
0355 
0356             virq = irq_find_mapping(wg->chip.irq.domain, gpio);
0357             handle_nested_irq(virq);
0358             regmap_set_bits(wg->regmap, reg, mask);
0359         }
0360 
0361         /* Next iteration */
0362         if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
0363             dev_err(wg->dev, "Failed to read irq status\n");
0364             break;
0365         }
0366 
0367         pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
0368     }
0369 
0370     return IRQ_HANDLED;
0371 }
0372 
0373 static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0374 {
0375     unsigned int ctlo, ctli, irq_mask, irq_status;
0376     struct wcove_gpio *wg = gpiochip_get_data(chip);
0377     int gpio, mask, ret = 0;
0378 
0379     for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
0380         ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
0381         ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
0382         if (ret) {
0383             dev_err(wg->dev, "Failed to read registers: CTRL out/in\n");
0384             break;
0385         }
0386 
0387         ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
0388         ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
0389         if (ret) {
0390             dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n");
0391             break;
0392         }
0393 
0394         seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
0395                gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
0396                ctli & 0x1 ? "hi" : "lo",
0397                ctli & CTLI_INTCNT_NE ? "fall" : "    ",
0398                ctli & CTLI_INTCNT_PE ? "rise" : "    ",
0399                ctlo,
0400                irq_mask & mask ? "mask  " : "unmask",
0401                irq_status & mask ? "pending" : "       ");
0402     }
0403 }
0404 
0405 static int wcove_gpio_probe(struct platform_device *pdev)
0406 {
0407     struct intel_soc_pmic *pmic;
0408     struct wcove_gpio *wg;
0409     int virq, ret, irq;
0410     struct device *dev;
0411     struct gpio_irq_chip *girq;
0412 
0413     /*
0414      * This gpio platform device is created by a mfd device (see
0415      * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
0416      * shared by all sub-devices created by the mfd device, the regmap
0417      * pointer for instance, is stored as driver data of the mfd device
0418      * driver.
0419      */
0420     pmic = dev_get_drvdata(pdev->dev.parent);
0421     if (!pmic)
0422         return -ENODEV;
0423 
0424     irq = platform_get_irq(pdev, 0);
0425     if (irq < 0)
0426         return irq;
0427 
0428     dev = &pdev->dev;
0429 
0430     wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
0431     if (!wg)
0432         return -ENOMEM;
0433 
0434     wg->regmap_irq_chip = pmic->irq_chip_data;
0435 
0436     platform_set_drvdata(pdev, wg);
0437 
0438     mutex_init(&wg->buslock);
0439     wg->chip.label = KBUILD_MODNAME;
0440     wg->chip.direction_input = wcove_gpio_dir_in;
0441     wg->chip.direction_output = wcove_gpio_dir_out;
0442     wg->chip.get_direction = wcove_gpio_get_direction;
0443     wg->chip.get = wcove_gpio_get;
0444     wg->chip.set = wcove_gpio_set;
0445     wg->chip.set_config = wcove_gpio_set_config;
0446     wg->chip.base = -1;
0447     wg->chip.ngpio = WCOVE_VGPIO_NUM;
0448     wg->chip.can_sleep = true;
0449     wg->chip.parent = pdev->dev.parent;
0450     wg->chip.dbg_show = wcove_gpio_dbg_show;
0451     wg->dev = dev;
0452     wg->regmap = pmic->regmap;
0453 
0454     virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
0455     if (virq < 0) {
0456         dev_err(dev, "Failed to get virq by irq %d\n", irq);
0457         return virq;
0458     }
0459 
0460     girq = &wg->chip.irq;
0461     gpio_irq_chip_set_chip(girq, &wcove_irqchip);
0462     /* This will let us handle the parent IRQ in the driver */
0463     girq->parent_handler = NULL;
0464     girq->num_parents = 0;
0465     girq->parents = NULL;
0466     girq->default_type = IRQ_TYPE_NONE;
0467     girq->handler = handle_simple_irq;
0468     girq->threaded = true;
0469 
0470     ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
0471                     IRQF_ONESHOT, pdev->name, wg);
0472     if (ret) {
0473         dev_err(dev, "Failed to request irq %d\n", virq);
0474         return ret;
0475     }
0476 
0477     ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
0478     if (ret) {
0479         dev_err(dev, "Failed to add gpiochip: %d\n", ret);
0480         return ret;
0481     }
0482 
0483     /* Enable GPIO0 interrupts */
0484     ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
0485     if (ret)
0486         return ret;
0487 
0488     /* Enable GPIO1 interrupts */
0489     ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);
0490     if (ret)
0491         return ret;
0492 
0493     return 0;
0494 }
0495 
0496 /*
0497  * Whiskey Cove PMIC itself is a analog device(but with digital control
0498  * interface) providing power management support for other devices in
0499  * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
0500  */
0501 static struct platform_driver wcove_gpio_driver = {
0502     .driver = {
0503         .name = "bxt_wcove_gpio",
0504     },
0505     .probe = wcove_gpio_probe,
0506 };
0507 
0508 module_platform_driver(wcove_gpio_driver);
0509 
0510 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
0511 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
0512 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
0513 MODULE_LICENSE("GPL v2");
0514 MODULE_ALIAS("platform:bxt_wcove_gpio");
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