drivers/gpio/gpio-uniphier.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2017 Socionext Inc.
0004 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0005
0006 #include <linux/bits.h>
0007 #include <linux/gpio/driver.h>
0008 #include <linux/irq.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/spinlock.h>
0016 #include <dt-bindings/gpio/uniphier-gpio.h>
0017
0018 #define UNIPHIER_GPIO_IRQ_MAX_NUM   24
0019
0020 #define UNIPHIER_GPIO_PORT_DATA     0x0 /* data */
0021 #define UNIPHIER_GPIO_PORT_DIR      0x4 /* direction (1:in, 0:out) */
0022 #define UNIPHIER_GPIO_IRQ_EN        0x90    /* irq enable */
0023 #define UNIPHIER_GPIO_IRQ_MODE      0x94    /* irq mode (1: both edge) */
0024 #define UNIPHIER_GPIO_IRQ_FLT_EN    0x98    /* noise filter enable */
0025 #define UNIPHIER_GPIO_IRQ_FLT_CYC   0x9c    /* noise filter clock cycle */
0026
0027 struct uniphier_gpio_priv {
0028     struct gpio_chip chip;
0029     struct irq_chip irq_chip;
0030     struct irq_domain *domain;
0031     void __iomem *regs;
0032     spinlock_t lock;
0033     u32 saved_vals[];
0034 };
0035
0036 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
0037 {
0038     unsigned int reg;
0039
0040     reg = (bank + 1) * 8;
0041
0042     /*
0043      * Unfortunately, the GPIO port registers are not contiguous because
0044      * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
0045      */
0046     if (reg >= UNIPHIER_GPIO_IRQ_EN)
0047         reg += 0x10;
0048
0049     return reg;
0050 }
0051
0052 static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
0053                         unsigned int *bank, u32 *mask)
0054 {
0055     *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
0056     *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
0057 }
0058
0059 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
0060                      unsigned int reg, u32 mask, u32 val)
0061 {
0062     unsigned long flags;
0063     u32 tmp;
0064
0065     spin_lock_irqsave(&priv->lock, flags);
0066     tmp = readl(priv->regs + reg);
0067     tmp &= ~mask;
0068     tmp |= mask & val;
0069     writel(tmp, priv->regs + reg);
0070     spin_unlock_irqrestore(&priv->lock, flags);
0071 }
0072
0073 static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
0074                      unsigned int reg, u32 mask, u32 val)
0075 {
0076     struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
0077
0078     if (!mask)
0079         return;
0080
0081     uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
0082                  mask, val);
0083 }
0084
0085 static void uniphier_gpio_offset_write(struct gpio_chip *chip,
0086                        unsigned int offset, unsigned int reg,
0087                        int val)
0088 {
0089     unsigned int bank;
0090     u32 mask;
0091
0092     uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
0093
0094     uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
0095 }
0096
0097 static int uniphier_gpio_offset_read(struct gpio_chip *chip,
0098                      unsigned int offset, unsigned int reg)
0099 {
0100     struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
0101     unsigned int bank, reg_offset;
0102     u32 mask;
0103
0104     uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
0105     reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
0106
0107     return !!(readl(priv->regs + reg_offset) & mask);
0108 }
0109
0110 static int uniphier_gpio_get_direction(struct gpio_chip *chip,
0111                        unsigned int offset)
0112 {
0113     if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR))
0114         return GPIO_LINE_DIRECTION_IN;
0115
0116     return GPIO_LINE_DIRECTION_OUT;
0117 }
0118
0119 static int uniphier_gpio_direction_input(struct gpio_chip *chip,
0120                      unsigned int offset)
0121 {
0122     uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
0123
0124     return 0;
0125 }
0126
0127 static int uniphier_gpio_direction_output(struct gpio_chip *chip,
0128                       unsigned int offset, int val)
0129 {
0130     uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
0131     uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
0132
0133     return 0;
0134 }
0135
0136 static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
0137 {
0138     return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
0139 }
0140
0141 static void uniphier_gpio_set(struct gpio_chip *chip,
0142                   unsigned int offset, int val)
0143 {
0144     uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
0145 }
0146
0147 static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
0148                        unsigned long *mask, unsigned long *bits)
0149 {
0150     unsigned long i, bank, bank_mask, bank_bits;
0151
0152     for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
0153         bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
0154         bank_bits = bitmap_get_value8(bits, i);
0155
0156         uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
0157                      bank_mask, bank_bits);
0158     }
0159 }
0160
0161 static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
0162 {
0163     struct irq_fwspec fwspec;
0164
0165     if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
0166         return -ENXIO;
0167
0168     fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
0169     fwspec.param_count = 2;
0170     fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
0171     /*
0172      * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
0173      * temporarily. Anyway, ->irq_set_type() will override it later.
0174      */
0175     fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
0176
0177     return irq_create_fwspec_mapping(&fwspec);
0178 }
0179
0180 static void uniphier_gpio_irq_mask(struct irq_data *data)
0181 {
0182     struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
0183     u32 mask = BIT(irqd_to_hwirq(data));
0184
0185     uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
0186
0187     irq_chip_mask_parent(data);
0188 }
0189
0190 static void uniphier_gpio_irq_unmask(struct irq_data *data)
0191 {
0192     struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
0193     u32 mask = BIT(irqd_to_hwirq(data));
0194
0195     uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
0196
0197     irq_chip_unmask_parent(data);
0198 }
0199
0200 static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
0201 {
0202     struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
0203     u32 mask = BIT(irqd_to_hwirq(data));
0204     u32 val = 0;
0205
0206     if (type == IRQ_TYPE_EDGE_BOTH) {
0207         val = mask;
0208         type = IRQ_TYPE_EDGE_FALLING;
0209     }
0210
0211     uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
0212     /* To enable both edge detection, the noise filter must be enabled. */
0213     uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
0214
0215     return irq_chip_set_type_parent(data, type);
0216 }
0217
0218 static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
0219                           unsigned int hwirq)
0220 {
0221     struct device_node *np = priv->chip.parent->of_node;
0222     const __be32 *range;
0223     u32 base, parent_base, size;
0224     int len;
0225
0226     range = of_get_property(np, "socionext,interrupt-ranges", &len);
0227     if (!range)
0228         return -EINVAL;
0229
0230     len /= sizeof(*range);
0231
0232     for (; len >= 3; len -= 3) {
0233         base = be32_to_cpu(*range++);
0234         parent_base = be32_to_cpu(*range++);
0235         size = be32_to_cpu(*range++);
0236
0237         if (base <= hwirq && hwirq < base + size)
0238             return hwirq - base + parent_base;
0239     }
0240
0241     return -ENOENT;
0242 }
0243
0244 static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
0245                           struct irq_fwspec *fwspec,
0246                           unsigned long *out_hwirq,
0247                           unsigned int *out_type)
0248 {
0249     if (WARN_ON(fwspec->param_count < 2))
0250         return -EINVAL;
0251
0252     *out_hwirq = fwspec->param[0];
0253     *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
0254
0255     return 0;
0256 }
0257
0258 static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
0259                       unsigned int virq,
0260                       unsigned int nr_irqs, void *arg)
0261 {
0262     struct uniphier_gpio_priv *priv = domain->host_data;
0263     struct irq_fwspec parent_fwspec;
0264     irq_hw_number_t hwirq;
0265     unsigned int type;
0266     int ret;
0267
0268     if (WARN_ON(nr_irqs != 1))
0269         return -EINVAL;
0270
0271     ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
0272     if (ret)
0273         return ret;
0274
0275     ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
0276     if (ret < 0)
0277         return ret;
0278
0279     /* parent is UniPhier AIDET */
0280     parent_fwspec.fwnode = domain->parent->fwnode;
0281     parent_fwspec.param_count = 2;
0282     parent_fwspec.param[0] = ret;
0283     parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
0284                         IRQ_TYPE_EDGE_FALLING : type;
0285
0286     ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
0287                         &priv->irq_chip, priv);
0288     if (ret)
0289         return ret;
0290
0291     return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
0292 }
0293
0294 static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
0295                          struct irq_data *data, bool early)
0296 {
0297     struct uniphier_gpio_priv *priv = domain->host_data;
0298     struct gpio_chip *chip = &priv->chip;
0299
0300     return gpiochip_lock_as_irq(chip,
0301             irqd_to_hwirq(data) + UNIPHIER_GPIO_IRQ_OFFSET);
0302 }
0303
0304 static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
0305                         struct irq_data *data)
0306 {
0307     struct uniphier_gpio_priv *priv = domain->host_data;
0308     struct gpio_chip *chip = &priv->chip;
0309
0310     gpiochip_unlock_as_irq(chip,
0311             irqd_to_hwirq(data) + UNIPHIER_GPIO_IRQ_OFFSET);
0312 }
0313
0314 static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
0315     .alloc = uniphier_gpio_irq_domain_alloc,
0316     .free = irq_domain_free_irqs_common,
0317     .activate = uniphier_gpio_irq_domain_activate,
0318     .deactivate = uniphier_gpio_irq_domain_deactivate,
0319     .translate = uniphier_gpio_irq_domain_translate,
0320 };
0321
0322 static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
0323 {
0324     /*
0325      * Due to the hardware design, the noise filter must be enabled to
0326      * detect both edge interrupts.  This filter is intended to remove the
0327      * noise from the irq lines.  It does not work for GPIO input, so GPIO
0328      * debounce is not supported.  Unfortunately, the filter period is
0329      * shared among all irq lines.  Just choose a sensible period here.
0330      */
0331     writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
0332 }
0333
0334 static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
0335 {
0336     return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
0337 }
0338
0339 static int uniphier_gpio_probe(struct platform_device *pdev)
0340 {
0341     struct device *dev = &pdev->dev;
0342     struct device_node *parent_np;
0343     struct irq_domain *parent_domain;
0344     struct uniphier_gpio_priv *priv;
0345     struct gpio_chip *chip;
0346     struct irq_chip *irq_chip;
0347     unsigned int nregs;
0348     u32 ngpios;
0349     int ret;
0350
0351     parent_np = of_irq_find_parent(dev->of_node);
0352     if (!parent_np)
0353         return -ENXIO;
0354
0355     parent_domain = irq_find_host(parent_np);
0356     of_node_put(parent_np);
0357     if (!parent_domain)
0358         return -EPROBE_DEFER;
0359
0360     ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
0361     if (ret)
0362         return ret;
0363
0364     nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
0365     priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
0366                 GFP_KERNEL);
0367     if (!priv)
0368         return -ENOMEM;
0369
0370     priv->regs = devm_platform_ioremap_resource(pdev, 0);
0371     if (IS_ERR(priv->regs))
0372         return PTR_ERR(priv->regs);
0373
0374     spin_lock_init(&priv->lock);
0375
0376     chip = &priv->chip;
0377     chip->label = dev_name(dev);
0378     chip->parent = dev;
0379     chip->request = gpiochip_generic_request;
0380     chip->free = gpiochip_generic_free;
0381     chip->get_direction = uniphier_gpio_get_direction;
0382     chip->direction_input = uniphier_gpio_direction_input;
0383     chip->direction_output = uniphier_gpio_direction_output;
0384     chip->get = uniphier_gpio_get;
0385     chip->set = uniphier_gpio_set;
0386     chip->set_multiple = uniphier_gpio_set_multiple;
0387     chip->to_irq = uniphier_gpio_to_irq;
0388     chip->base = -1;
0389     chip->ngpio = ngpios;
0390
0391     irq_chip = &priv->irq_chip;
0392     irq_chip->name = dev_name(dev);
0393     irq_chip->irq_mask = uniphier_gpio_irq_mask;
0394     irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
0395     irq_chip->irq_eoi = irq_chip_eoi_parent;
0396     irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
0397     irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
0398
0399     uniphier_gpio_hw_init(priv);
0400
0401     ret = devm_gpiochip_add_data(dev, chip, priv);
0402     if (ret)
0403         return ret;
0404
0405     priv->domain = irq_domain_create_hierarchy(
0406                     parent_domain, 0,
0407                     UNIPHIER_GPIO_IRQ_MAX_NUM,
0408                     of_node_to_fwnode(dev->of_node),
0409                     &uniphier_gpio_irq_domain_ops, priv);
0410     if (!priv->domain)
0411         return -ENOMEM;
0412
0413     platform_set_drvdata(pdev, priv);
0414
0415     return 0;
0416 }
0417
0418 static int uniphier_gpio_remove(struct platform_device *pdev)
0419 {
0420     struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
0421
0422     irq_domain_remove(priv->domain);
0423
0424     return 0;
0425 }
0426
0427 static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
0428 {
0429     struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
0430     unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
0431     u32 *val = priv->saved_vals;
0432     unsigned int reg;
0433     int i;
0434
0435     for (i = 0; i < nbanks; i++) {
0436         reg = uniphier_gpio_bank_to_reg(i);
0437
0438         *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
0439         *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
0440     }
0441
0442     *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
0443     *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
0444     *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
0445
0446     return 0;
0447 }
0448
0449 static int __maybe_unused uniphier_gpio_resume(struct device *dev)
0450 {
0451     struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
0452     unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
0453     const u32 *val = priv->saved_vals;
0454     unsigned int reg;
0455     int i;
0456
0457     for (i = 0; i < nbanks; i++) {
0458         reg = uniphier_gpio_bank_to_reg(i);
0459
0460         writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
0461         writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
0462     }
0463
0464     writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
0465     writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
0466     writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
0467
0468     uniphier_gpio_hw_init(priv);
0469
0470     return 0;
0471 }
0472
0473 static const struct dev_pm_ops uniphier_gpio_pm_ops = {
0474     SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
0475                      uniphier_gpio_resume)
0476 };
0477
0478 static const struct of_device_id uniphier_gpio_match[] = {
0479     { .compatible = "socionext,uniphier-gpio" },
0480     { /* sentinel */ }
0481 };
0482 MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
0483
0484 static struct platform_driver uniphier_gpio_driver = {
0485     .probe = uniphier_gpio_probe,
0486     .remove = uniphier_gpio_remove,
0487     .driver = {
0488         .name = "uniphier-gpio",
0489         .of_match_table = uniphier_gpio_match,
0490         .pm = &uniphier_gpio_pm_ops,
0491     },
0492 };
0493 module_platform_driver(uniphier_gpio_driver);
0494
0495 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
0496 MODULE_DESCRIPTION("UniPhier GPIO driver");
0497 MODULE_LICENSE("GPL v2");