drivers/gpio/gpio-tqmx86.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * TQ-Systems TQMx86 PLD GPIO driver
0004  *
0005  * Based on vendor driver by:
0006  *   Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/errno.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/slab.h>
0019
0020 #define TQMX86_NGPIO    8
0021 #define TQMX86_NGPO 4   /* 0-3 - output */
0022 #define TQMX86_NGPI 4   /* 4-7 - input */
0023 #define TQMX86_DIR_INPUT_MASK   0xf0    /* 0-3 - output, 4-7 - input */
0024
0025 #define TQMX86_GPIODD   0   /* GPIO Data Direction Register */
0026 #define TQMX86_GPIOD    1   /* GPIO Data Register */
0027 #define TQMX86_GPIIC    3   /* GPI Interrupt Configuration Register */
0028 #define TQMX86_GPIIS    4   /* GPI Interrupt Status Register */
0029
0030 #define TQMX86_GPII_FALLING BIT(0)
0031 #define TQMX86_GPII_RISING  BIT(1)
0032 #define TQMX86_GPII_MASK    (BIT(0) | BIT(1))
0033 #define TQMX86_GPII_BITS    2
0034
0035 struct tqmx86_gpio_data {
0036     struct gpio_chip    chip;
0037     struct irq_chip     irq_chip;
0038     void __iomem        *io_base;
0039     int         irq;
0040     raw_spinlock_t      spinlock;
0041     u8          irq_type[TQMX86_NGPI];
0042 };
0043
0044 static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg)
0045 {
0046     return ioread8(gd->io_base + reg);
0047 }
0048
0049 static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
0050                   unsigned int reg)
0051 {
0052     iowrite8(val, gd->io_base + reg);
0053 }
0054
0055 static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset)
0056 {
0057     struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
0058
0059     return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset));
0060 }
0061
0062 static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
0063                 int value)
0064 {
0065     struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
0066     unsigned long flags;
0067     u8 val;
0068
0069     raw_spin_lock_irqsave(&gpio->spinlock, flags);
0070     val = tqmx86_gpio_read(gpio, TQMX86_GPIOD);
0071     if (value)
0072         val |= BIT(offset);
0073     else
0074         val &= ~BIT(offset);
0075     tqmx86_gpio_write(gpio, val, TQMX86_GPIOD);
0076     raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
0077 }
0078
0079 static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
0080                        unsigned int offset)
0081 {
0082     /* Direction cannot be changed. Validate is an input. */
0083     if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
0084         return 0;
0085     else
0086         return -EINVAL;
0087 }
0088
0089 static int tqmx86_gpio_direction_output(struct gpio_chip *chip,
0090                     unsigned int offset,
0091                     int value)
0092 {
0093     /* Direction cannot be changed, validate is an output */
0094     if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
0095         return -EINVAL;
0096
0097     tqmx86_gpio_set(chip, offset, value);
0098     return 0;
0099 }
0100
0101 static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
0102                      unsigned int offset)
0103 {
0104     if (TQMX86_DIR_INPUT_MASK & BIT(offset))
0105         return GPIO_LINE_DIRECTION_IN;
0106
0107     return GPIO_LINE_DIRECTION_OUT;
0108 }
0109
0110 static void tqmx86_gpio_irq_mask(struct irq_data *data)
0111 {
0112     unsigned int offset = (data->hwirq - TQMX86_NGPO);
0113     struct tqmx86_gpio_data *gpio = gpiochip_get_data(
0114         irq_data_get_irq_chip_data(data));
0115     unsigned long flags;
0116     u8 gpiic, mask;
0117
0118     mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
0119
0120     raw_spin_lock_irqsave(&gpio->spinlock, flags);
0121     gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
0122     gpiic &= ~mask;
0123     tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
0124     raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
0125 }
0126
0127 static void tqmx86_gpio_irq_unmask(struct irq_data *data)
0128 {
0129     unsigned int offset = (data->hwirq - TQMX86_NGPO);
0130     struct tqmx86_gpio_data *gpio = gpiochip_get_data(
0131         irq_data_get_irq_chip_data(data));
0132     unsigned long flags;
0133     u8 gpiic, mask;
0134
0135     mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
0136
0137     raw_spin_lock_irqsave(&gpio->spinlock, flags);
0138     gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
0139     gpiic &= ~mask;
0140     gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS);
0141     tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
0142     raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
0143 }
0144
0145 static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
0146 {
0147     struct tqmx86_gpio_data *gpio = gpiochip_get_data(
0148         irq_data_get_irq_chip_data(data));
0149     unsigned int offset = (data->hwirq - TQMX86_NGPO);
0150     unsigned int edge_type = type & IRQF_TRIGGER_MASK;
0151     unsigned long flags;
0152     u8 new_type, gpiic;
0153
0154     switch (edge_type) {
0155     case IRQ_TYPE_EDGE_RISING:
0156         new_type = TQMX86_GPII_RISING;
0157         break;
0158     case IRQ_TYPE_EDGE_FALLING:
0159         new_type = TQMX86_GPII_FALLING;
0160         break;
0161     case IRQ_TYPE_EDGE_BOTH:
0162         new_type = TQMX86_GPII_FALLING | TQMX86_GPII_RISING;
0163         break;
0164     default:
0165         return -EINVAL; /* not supported */
0166     }
0167
0168     gpio->irq_type[offset] = new_type;
0169
0170     raw_spin_lock_irqsave(&gpio->spinlock, flags);
0171     gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
0172     gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS));
0173     gpiic |= new_type << (offset * TQMX86_GPII_BITS);
0174     tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
0175     raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
0176
0177     return 0;
0178 }
0179
0180 static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
0181 {
0182     struct gpio_chip *chip = irq_desc_get_handler_data(desc);
0183     struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
0184     struct irq_chip *irq_chip = irq_desc_get_chip(desc);
0185     unsigned long irq_bits;
0186     int i = 0;
0187     u8 irq_status;
0188
0189     chained_irq_enter(irq_chip, desc);
0190
0191     irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
0192     tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
0193
0194     irq_bits = irq_status;
0195     for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
0196         generic_handle_domain_irq(gpio->chip.irq.domain,
0197                       i + TQMX86_NGPO);
0198
0199     chained_irq_exit(irq_chip, desc);
0200 }
0201
0202 /* Minimal runtime PM is needed by the IRQ subsystem */
0203 static int __maybe_unused tqmx86_gpio_runtime_suspend(struct device *dev)
0204 {
0205     return 0;
0206 }
0207
0208 static int __maybe_unused tqmx86_gpio_runtime_resume(struct device *dev)
0209 {
0210     return 0;
0211 }
0212
0213 static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = {
0214     SET_RUNTIME_PM_OPS(tqmx86_gpio_runtime_suspend,
0215                tqmx86_gpio_runtime_resume, NULL)
0216 };
0217
0218 static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip,
0219                        unsigned long *valid_mask,
0220                        unsigned int ngpios)
0221 {
0222     /* Only GPIOs 4-7 are valid for interrupts. Clear the others */
0223     clear_bit(0, valid_mask);
0224     clear_bit(1, valid_mask);
0225     clear_bit(2, valid_mask);
0226     clear_bit(3, valid_mask);
0227 }
0228
0229 static int tqmx86_gpio_probe(struct platform_device *pdev)
0230 {
0231     struct device *dev = &pdev->dev;
0232     struct tqmx86_gpio_data *gpio;
0233     struct gpio_chip *chip;
0234     struct gpio_irq_chip *girq;
0235     void __iomem *io_base;
0236     struct resource *res;
0237     int ret, irq;
0238
0239     irq = platform_get_irq_optional(pdev, 0);
0240     if (irq < 0 && irq != -ENXIO)
0241         return irq;
0242
0243     res = platform_get_resource(pdev, IORESOURCE_IO, 0);
0244     if (!res) {
0245         dev_err(&pdev->dev, "Cannot get I/O\n");
0246         return -ENODEV;
0247     }
0248
0249     io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
0250     if (!io_base)
0251         return -ENOMEM;
0252
0253     gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
0254     if (!gpio)
0255         return -ENOMEM;
0256
0257     raw_spin_lock_init(&gpio->spinlock);
0258     gpio->io_base = io_base;
0259
0260     tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD);
0261
0262     platform_set_drvdata(pdev, gpio);
0263
0264     chip = &gpio->chip;
0265     chip->label = "gpio-tqmx86";
0266     chip->owner = THIS_MODULE;
0267     chip->can_sleep = false;
0268     chip->base = -1;
0269     chip->direction_input = tqmx86_gpio_direction_input;
0270     chip->direction_output = tqmx86_gpio_direction_output;
0271     chip->get_direction = tqmx86_gpio_get_direction;
0272     chip->get = tqmx86_gpio_get;
0273     chip->set = tqmx86_gpio_set;
0274     chip->ngpio = TQMX86_NGPIO;
0275     chip->parent = pdev->dev.parent;
0276
0277     pm_runtime_enable(&pdev->dev);
0278
0279     if (irq > 0) {
0280         struct irq_chip *irq_chip = &gpio->irq_chip;
0281         u8 irq_status;
0282
0283         irq_chip->name = chip->label;
0284         irq_chip->irq_mask = tqmx86_gpio_irq_mask;
0285         irq_chip->irq_unmask = tqmx86_gpio_irq_unmask;
0286         irq_chip->irq_set_type = tqmx86_gpio_irq_set_type;
0287
0288         /* Mask all interrupts */
0289         tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC);
0290
0291         /* Clear all pending interrupts */
0292         irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
0293         tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
0294
0295         girq = &chip->irq;
0296         girq->chip = irq_chip;
0297         girq->parent_handler = tqmx86_gpio_irq_handler;
0298         girq->num_parents = 1;
0299         girq->parents = devm_kcalloc(&pdev->dev, 1,
0300                          sizeof(*girq->parents),
0301                          GFP_KERNEL);
0302         if (!girq->parents) {
0303             ret = -ENOMEM;
0304             goto out_pm_dis;
0305         }
0306         girq->parents[0] = irq;
0307         girq->default_type = IRQ_TYPE_NONE;
0308         girq->handler = handle_simple_irq;
0309         girq->init_valid_mask = tqmx86_init_irq_valid_mask;
0310
0311         irq_domain_set_pm_device(girq->domain, dev);
0312     }
0313
0314     ret = devm_gpiochip_add_data(dev, chip, gpio);
0315     if (ret) {
0316         dev_err(dev, "Could not register GPIO chip\n");
0317         goto out_pm_dis;
0318     }
0319
0320     dev_info(dev, "GPIO functionality initialized with %d pins\n",
0321          chip->ngpio);
0322
0323     return 0;
0324
0325 out_pm_dis:
0326     pm_runtime_disable(&pdev->dev);
0327
0328     return ret;
0329 }
0330
0331 static struct platform_driver tqmx86_gpio_driver = {
0332     .driver = {
0333         .name = "tqmx86-gpio",
0334         .pm = &tqmx86_gpio_dev_pm_ops,
0335     },
0336     .probe      = tqmx86_gpio_probe,
0337 };
0338
0339 module_platform_driver(tqmx86_gpio_driver);
0340
0341 MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver");
0342 MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
0343 MODULE_LICENSE("GPL");
0344 MODULE_ALIAS("platform:tqmx86-gpio");