drivers/gpio/gpio-thunderx.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2016, 2017 Cavium Inc.
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/irq.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/pci.h>
0017 #include <linux/spinlock.h>
0018
0019 #define GPIO_RX_DAT 0x0
0020 #define GPIO_TX_SET 0x8
0021 #define GPIO_TX_CLR 0x10
0022 #define GPIO_CONST  0x90
0023 #define  GPIO_CONST_GPIOS_MASK 0xff
0024 #define GPIO_BIT_CFG    0x400
0025 #define  GPIO_BIT_CFG_TX_OE     BIT(0)
0026 #define  GPIO_BIT_CFG_PIN_XOR       BIT(1)
0027 #define  GPIO_BIT_CFG_INT_EN        BIT(2)
0028 #define  GPIO_BIT_CFG_INT_TYPE      BIT(3)
0029 #define  GPIO_BIT_CFG_FIL_MASK      GENMASK(11, 4)
0030 #define  GPIO_BIT_CFG_FIL_CNT_SHIFT 4
0031 #define  GPIO_BIT_CFG_FIL_SEL_SHIFT 8
0032 #define  GPIO_BIT_CFG_TX_OD     BIT(12)
0033 #define  GPIO_BIT_CFG_PIN_SEL_MASK  GENMASK(25, 16)
0034 #define GPIO_INTR   0x800
0035 #define  GPIO_INTR_INTR         BIT(0)
0036 #define  GPIO_INTR_INTR_W1S     BIT(1)
0037 #define  GPIO_INTR_ENA_W1C      BIT(2)
0038 #define  GPIO_INTR_ENA_W1S      BIT(3)
0039 #define GPIO_2ND_BANK   0x1400
0040
0041 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
0042                  (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
0043
0044 struct thunderx_gpio;
0045
0046 struct thunderx_line {
0047     struct thunderx_gpio    *txgpio;
0048     unsigned int        line;
0049     unsigned int        fil_bits;
0050 };
0051
0052 struct thunderx_gpio {
0053     struct gpio_chip    chip;
0054     u8 __iomem      *register_base;
0055     struct msix_entry   *msix_entries;  /* per line MSI-X */
0056     struct thunderx_line    *line_entries;  /* per line irq info */
0057     raw_spinlock_t      lock;
0058     unsigned long       invert_mask[2];
0059     unsigned long       od_mask[2];
0060     int         base_msi;
0061 };
0062
0063 static unsigned int bit_cfg_reg(unsigned int line)
0064 {
0065     return 8 * line + GPIO_BIT_CFG;
0066 }
0067
0068 static unsigned int intr_reg(unsigned int line)
0069 {
0070     return 8 * line + GPIO_INTR;
0071 }
0072
0073 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
0074                      unsigned int line)
0075 {
0076     u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
0077
0078     return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
0079 }
0080
0081 /*
0082  * Check (and WARN) that the pin is available for GPIO.  We will not
0083  * allow modification of the state of non-GPIO pins from this driver.
0084  */
0085 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
0086                   unsigned int line)
0087 {
0088     bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
0089
0090     WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
0091
0092     return rv;
0093 }
0094
0095 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
0096 {
0097     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0098
0099     return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
0100 }
0101
0102 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
0103 {
0104     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0105
0106     if (!thunderx_gpio_is_gpio(txgpio, line))
0107         return -EIO;
0108
0109     raw_spin_lock(&txgpio->lock);
0110     clear_bit(line, txgpio->invert_mask);
0111     clear_bit(line, txgpio->od_mask);
0112     writeq(txgpio->line_entries[line].fil_bits,
0113            txgpio->register_base + bit_cfg_reg(line));
0114     raw_spin_unlock(&txgpio->lock);
0115     return 0;
0116 }
0117
0118 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
0119                   int value)
0120 {
0121     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0122     int bank = line / 64;
0123     int bank_bit = line % 64;
0124
0125     void __iomem *reg = txgpio->register_base +
0126         (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
0127
0128     writeq(BIT_ULL(bank_bit), reg);
0129 }
0130
0131 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
0132                  int value)
0133 {
0134     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0135     u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
0136
0137     if (!thunderx_gpio_is_gpio(txgpio, line))
0138         return -EIO;
0139
0140     raw_spin_lock(&txgpio->lock);
0141
0142     thunderx_gpio_set(chip, line, value);
0143
0144     if (test_bit(line, txgpio->invert_mask))
0145         bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
0146
0147     if (test_bit(line, txgpio->od_mask))
0148         bit_cfg |= GPIO_BIT_CFG_TX_OD;
0149
0150     writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
0151
0152     raw_spin_unlock(&txgpio->lock);
0153     return 0;
0154 }
0155
0156 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
0157 {
0158     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0159     u64 bit_cfg;
0160
0161     if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
0162         /*
0163          * Say it is input for now to avoid WARNing on
0164          * gpiochip_add_data().  We will WARN if someone
0165          * requests it or tries to use it.
0166          */
0167         return 1;
0168
0169     bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
0170
0171     if (bit_cfg & GPIO_BIT_CFG_TX_OE)
0172         return GPIO_LINE_DIRECTION_OUT;
0173
0174     return GPIO_LINE_DIRECTION_IN;
0175 }
0176
0177 static int thunderx_gpio_set_config(struct gpio_chip *chip,
0178                     unsigned int line,
0179                     unsigned long cfg)
0180 {
0181     bool orig_invert, orig_od, orig_dat, new_invert, new_od;
0182     u32 arg, sel;
0183     u64 bit_cfg;
0184     int bank = line / 64;
0185     int bank_bit = line % 64;
0186     int ret = -ENOTSUPP;
0187     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0188     void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
0189
0190     if (!thunderx_gpio_is_gpio(txgpio, line))
0191         return -EIO;
0192
0193     raw_spin_lock(&txgpio->lock);
0194     orig_invert = test_bit(line, txgpio->invert_mask);
0195     new_invert  = orig_invert;
0196     orig_od = test_bit(line, txgpio->od_mask);
0197     new_od = orig_od;
0198     orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
0199     bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
0200     switch (pinconf_to_config_param(cfg)) {
0201     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0202         /*
0203          * Weird, setting open-drain mode causes signal
0204          * inversion.  Note this so we can compensate in the
0205          * dir_out function.
0206          */
0207         set_bit(line, txgpio->invert_mask);
0208         new_invert  = true;
0209         set_bit(line, txgpio->od_mask);
0210         new_od = true;
0211         ret = 0;
0212         break;
0213     case PIN_CONFIG_DRIVE_PUSH_PULL:
0214         clear_bit(line, txgpio->invert_mask);
0215         new_invert  = false;
0216         clear_bit(line, txgpio->od_mask);
0217         new_od  = false;
0218         ret = 0;
0219         break;
0220     case PIN_CONFIG_INPUT_DEBOUNCE:
0221         arg = pinconf_to_config_argument(cfg);
0222         if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
0223             ret = -EINVAL;
0224             break;
0225         }
0226         arg *= 400; /* scale to 2.5nS clocks. */
0227         sel = 0;
0228         while (arg > 15) {
0229             sel++;
0230             arg++; /* always round up */
0231             arg >>= 1;
0232         }
0233         txgpio->line_entries[line].fil_bits =
0234             (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
0235             (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
0236         bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
0237         bit_cfg |= txgpio->line_entries[line].fil_bits;
0238         writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
0239         ret = 0;
0240         break;
0241     default:
0242         break;
0243     }
0244     raw_spin_unlock(&txgpio->lock);
0245
0246     /*
0247      * If currently output and OPEN_DRAIN changed, install the new
0248      * settings
0249      */
0250     if ((new_invert != orig_invert || new_od != orig_od) &&
0251         (bit_cfg & GPIO_BIT_CFG_TX_OE))
0252         ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
0253
0254     return ret;
0255 }
0256
0257 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
0258 {
0259     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0260     int bank = line / 64;
0261     int bank_bit = line % 64;
0262     u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
0263     u64 masked_bits = read_bits & BIT_ULL(bank_bit);
0264
0265     if (test_bit(line, txgpio->invert_mask))
0266         return masked_bits == 0;
0267     else
0268         return masked_bits != 0;
0269 }
0270
0271 static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
0272                        unsigned long *mask,
0273                        unsigned long *bits)
0274 {
0275     int bank;
0276     u64 set_bits, clear_bits;
0277     struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
0278
0279     for (bank = 0; bank <= chip->ngpio / 64; bank++) {
0280         set_bits = bits[bank] & mask[bank];
0281         clear_bits = ~bits[bank] & mask[bank];
0282         writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
0283         writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
0284     }
0285 }
0286
0287 static void thunderx_gpio_irq_ack(struct irq_data *d)
0288 {
0289     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0290     struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
0291
0292     writeq(GPIO_INTR_INTR,
0293            txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
0294 }
0295
0296 static void thunderx_gpio_irq_mask(struct irq_data *d)
0297 {
0298     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0299     struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
0300
0301     writeq(GPIO_INTR_ENA_W1C,
0302            txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
0303 }
0304
0305 static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
0306 {
0307     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0308     struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
0309
0310     writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
0311            txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
0312 }
0313
0314 static void thunderx_gpio_irq_unmask(struct irq_data *d)
0315 {
0316     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0317     struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
0318
0319     writeq(GPIO_INTR_ENA_W1S,
0320            txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
0321 }
0322
0323 static int thunderx_gpio_irq_set_type(struct irq_data *d,
0324                       unsigned int flow_type)
0325 {
0326     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0327     struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
0328     struct thunderx_line *txline =
0329         &txgpio->line_entries[irqd_to_hwirq(d)];
0330     u64 bit_cfg;
0331
0332     irqd_set_trigger_type(d, flow_type);
0333
0334     bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
0335
0336     if (flow_type & IRQ_TYPE_EDGE_BOTH) {
0337         irq_set_handler_locked(d, handle_fasteoi_ack_irq);
0338         bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
0339     } else {
0340         irq_set_handler_locked(d, handle_fasteoi_mask_irq);
0341     }
0342
0343     raw_spin_lock(&txgpio->lock);
0344     if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
0345         bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
0346         set_bit(txline->line, txgpio->invert_mask);
0347     } else {
0348         clear_bit(txline->line, txgpio->invert_mask);
0349     }
0350     clear_bit(txline->line, txgpio->od_mask);
0351     writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
0352     raw_spin_unlock(&txgpio->lock);
0353
0354     return IRQ_SET_MASK_OK;
0355 }
0356
0357 static void thunderx_gpio_irq_enable(struct irq_data *data)
0358 {
0359     irq_chip_enable_parent(data);
0360     thunderx_gpio_irq_unmask(data);
0361 }
0362
0363 static void thunderx_gpio_irq_disable(struct irq_data *data)
0364 {
0365     thunderx_gpio_irq_mask(data);
0366     irq_chip_disable_parent(data);
0367 }
0368
0369 /*
0370  * Interrupts are chained from underlying MSI-X vectors.  We have
0371  * these irq_chip functions to be able to handle level triggering
0372  * semantics and other acknowledgment tasks associated with the GPIO
0373  * mechanism.
0374  */
0375 static struct irq_chip thunderx_gpio_irq_chip = {
0376     .name           = "GPIO",
0377     .irq_enable     = thunderx_gpio_irq_enable,
0378     .irq_disable        = thunderx_gpio_irq_disable,
0379     .irq_ack        = thunderx_gpio_irq_ack,
0380     .irq_mask       = thunderx_gpio_irq_mask,
0381     .irq_mask_ack       = thunderx_gpio_irq_mask_ack,
0382     .irq_unmask     = thunderx_gpio_irq_unmask,
0383     .irq_eoi        = irq_chip_eoi_parent,
0384     .irq_set_affinity   = irq_chip_set_affinity_parent,
0385     .irq_set_type       = thunderx_gpio_irq_set_type,
0386
0387     .flags          = IRQCHIP_SET_TYPE_MASKED
0388 };
0389
0390 static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
0391                            unsigned int child,
0392                            unsigned int child_type,
0393                            unsigned int *parent,
0394                            unsigned int *parent_type)
0395 {
0396     struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
0397     struct irq_data *irqd;
0398     unsigned int irq;
0399
0400     irq = txgpio->msix_entries[child].vector;
0401     irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq);
0402     if (!irqd)
0403         return -EINVAL;
0404     *parent = irqd_to_hwirq(irqd);
0405     *parent_type = IRQ_TYPE_LEVEL_HIGH;
0406     return 0;
0407 }
0408
0409 static int thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip,
0410                             union gpio_irq_fwspec *gfwspec,
0411                             unsigned int parent_hwirq,
0412                             unsigned int parent_type)
0413 {
0414     msi_alloc_info_t *info = &gfwspec->msiinfo;
0415
0416     info->hwirq = parent_hwirq;
0417     return 0;
0418 }
0419
0420 static int thunderx_gpio_probe(struct pci_dev *pdev,
0421                    const struct pci_device_id *id)
0422 {
0423     void __iomem * const *tbl;
0424     struct device *dev = &pdev->dev;
0425     struct thunderx_gpio *txgpio;
0426     struct gpio_chip *chip;
0427     struct gpio_irq_chip *girq;
0428     int ngpio, i;
0429     int err = 0;
0430
0431     txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
0432     if (!txgpio)
0433         return -ENOMEM;
0434
0435     raw_spin_lock_init(&txgpio->lock);
0436     chip = &txgpio->chip;
0437
0438     pci_set_drvdata(pdev, txgpio);
0439
0440     err = pcim_enable_device(pdev);
0441     if (err) {
0442         dev_err(dev, "Failed to enable PCI device: err %d\n", err);
0443         goto out;
0444     }
0445
0446     err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
0447     if (err) {
0448         dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
0449         goto out;
0450     }
0451
0452     tbl = pcim_iomap_table(pdev);
0453     txgpio->register_base = tbl[0];
0454     if (!txgpio->register_base) {
0455         dev_err(dev, "Cannot map PCI resource\n");
0456         err = -ENOMEM;
0457         goto out;
0458     }
0459
0460     if (pdev->subsystem_device == 0xa10a) {
0461         /* CN88XX has no GPIO_CONST register*/
0462         ngpio = 50;
0463         txgpio->base_msi = 48;
0464     } else {
0465         u64 c = readq(txgpio->register_base + GPIO_CONST);
0466
0467         ngpio = c & GPIO_CONST_GPIOS_MASK;
0468         txgpio->base_msi = (c >> 8) & 0xff;
0469     }
0470
0471     txgpio->msix_entries = devm_kcalloc(dev,
0472                         ngpio, sizeof(struct msix_entry),
0473                         GFP_KERNEL);
0474     if (!txgpio->msix_entries) {
0475         err = -ENOMEM;
0476         goto out;
0477     }
0478
0479     txgpio->line_entries = devm_kcalloc(dev,
0480                         ngpio,
0481                         sizeof(struct thunderx_line),
0482                         GFP_KERNEL);
0483     if (!txgpio->line_entries) {
0484         err = -ENOMEM;
0485         goto out;
0486     }
0487
0488     for (i = 0; i < ngpio; i++) {
0489         u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
0490
0491         txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
0492         txgpio->line_entries[i].line = i;
0493         txgpio->line_entries[i].txgpio = txgpio;
0494         /*
0495          * If something has already programmed the pin, use
0496          * the existing glitch filter settings, otherwise go
0497          * to 400nS.
0498          */
0499         txgpio->line_entries[i].fil_bits = bit_cfg ?
0500             (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
0501
0502         if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
0503             set_bit(i, txgpio->od_mask);
0504         if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
0505             set_bit(i, txgpio->invert_mask);
0506     }
0507
0508
0509     /* Enable all MSI-X for interrupts on all possible lines. */
0510     err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
0511     if (err < 0)
0512         goto out;
0513
0514     chip->label = KBUILD_MODNAME;
0515     chip->parent = dev;
0516     chip->owner = THIS_MODULE;
0517     chip->request = thunderx_gpio_request;
0518     chip->base = -1; /* System allocated */
0519     chip->can_sleep = false;
0520     chip->ngpio = ngpio;
0521     chip->get_direction = thunderx_gpio_get_direction;
0522     chip->direction_input = thunderx_gpio_dir_in;
0523     chip->get = thunderx_gpio_get;
0524     chip->direction_output = thunderx_gpio_dir_out;
0525     chip->set = thunderx_gpio_set;
0526     chip->set_multiple = thunderx_gpio_set_multiple;
0527     chip->set_config = thunderx_gpio_set_config;
0528     girq = &chip->irq;
0529     girq->chip = &thunderx_gpio_irq_chip;
0530     girq->fwnode = of_node_to_fwnode(dev->of_node);
0531     girq->parent_domain =
0532         irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
0533     girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
0534     girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info;
0535     girq->handler = handle_bad_irq;
0536     girq->default_type = IRQ_TYPE_NONE;
0537
0538     err = devm_gpiochip_add_data(dev, chip, txgpio);
0539     if (err)
0540         goto out;
0541
0542     /* Push on irq_data and the domain for each line. */
0543     for (i = 0; i < ngpio; i++) {
0544         struct irq_fwspec fwspec;
0545
0546         fwspec.fwnode = of_node_to_fwnode(dev->of_node);
0547         fwspec.param_count = 2;
0548         fwspec.param[0] = i;
0549         fwspec.param[1] = IRQ_TYPE_NONE;
0550         err = irq_domain_push_irq(girq->domain,
0551                       txgpio->msix_entries[i].vector,
0552                       &fwspec);
0553         if (err < 0)
0554             dev_err(dev, "irq_domain_push_irq: %d\n", err);
0555     }
0556
0557     dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
0558          ngpio, chip->base);
0559     return 0;
0560 out:
0561     pci_set_drvdata(pdev, NULL);
0562     return err;
0563 }
0564
0565 static void thunderx_gpio_remove(struct pci_dev *pdev)
0566 {
0567     int i;
0568     struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
0569
0570     for (i = 0; i < txgpio->chip.ngpio; i++)
0571         irq_domain_pop_irq(txgpio->chip.irq.domain,
0572                    txgpio->msix_entries[i].vector);
0573
0574     irq_domain_remove(txgpio->chip.irq.domain);
0575
0576     pci_set_drvdata(pdev, NULL);
0577 }
0578
0579 static const struct pci_device_id thunderx_gpio_id_table[] = {
0580     { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
0581     { 0, }  /* end of table */
0582 };
0583
0584 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
0585
0586 static struct pci_driver thunderx_gpio_driver = {
0587     .name = KBUILD_MODNAME,
0588     .id_table = thunderx_gpio_id_table,
0589     .probe = thunderx_gpio_probe,
0590     .remove = thunderx_gpio_remove,
0591 };
0592
0593 module_pci_driver(thunderx_gpio_driver);
0594
0595 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
0596 MODULE_LICENSE("GPL");