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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016-2022 NVIDIA Corporation
0004  *
0005  * Author: Thierry Reding <treding@nvidia.com>
0006  *     Dipen Patel <dpatel@nvidia.com>
0007  */
0008 
0009 #include <linux/gpio/driver.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/irq.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/hte.h>
0016 
0017 #include <dt-bindings/gpio/tegra186-gpio.h>
0018 #include <dt-bindings/gpio/tegra194-gpio.h>
0019 #include <dt-bindings/gpio/tegra234-gpio.h>
0020 #include <dt-bindings/gpio/tegra241-gpio.h>
0021 
0022 /* security registers */
0023 #define TEGRA186_GPIO_CTL_SCR 0x0c
0024 #define  TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
0025 #define  TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
0026 
0027 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
0028 
0029 /* control registers */
0030 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
0031 #define  TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
0032 #define  TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
0033 #define  TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
0034 #define  TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
0035 #define  TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
0036 #define  TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
0037 #define  TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
0038 #define  TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
0039 #define  TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
0040 #define  TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
0041 #define  TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
0042 
0043 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
0044 #define  TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
0045 
0046 #define TEGRA186_GPIO_INPUT 0x08
0047 #define  TEGRA186_GPIO_INPUT_HIGH BIT(0)
0048 
0049 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
0050 #define  TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
0051 
0052 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
0053 #define  TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
0054 
0055 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
0056 
0057 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
0058 
0059 struct tegra_gpio_port {
0060     const char *name;
0061     unsigned int bank;
0062     unsigned int port;
0063     unsigned int pins;
0064 };
0065 
0066 struct tegra186_pin_range {
0067     unsigned int offset;
0068     const char *group;
0069 };
0070 
0071 struct tegra_gpio_soc {
0072     const struct tegra_gpio_port *ports;
0073     unsigned int num_ports;
0074     const char *name;
0075     unsigned int instance;
0076 
0077     unsigned int num_irqs_per_bank;
0078 
0079     const struct tegra186_pin_range *pin_ranges;
0080     unsigned int num_pin_ranges;
0081     const char *pinmux;
0082     bool has_gte;
0083 };
0084 
0085 struct tegra_gpio {
0086     struct gpio_chip gpio;
0087     unsigned int num_irq;
0088     unsigned int *irq;
0089 
0090     const struct tegra_gpio_soc *soc;
0091     unsigned int num_irqs_per_bank;
0092     unsigned int num_banks;
0093 
0094     void __iomem *secure;
0095     void __iomem *base;
0096 };
0097 
0098 static const struct tegra_gpio_port *
0099 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
0100 {
0101     unsigned int start = 0, i;
0102 
0103     for (i = 0; i < gpio->soc->num_ports; i++) {
0104         const struct tegra_gpio_port *port = &gpio->soc->ports[i];
0105 
0106         if (*pin >= start && *pin < start + port->pins) {
0107             *pin -= start;
0108             return port;
0109         }
0110 
0111         start += port->pins;
0112     }
0113 
0114     return NULL;
0115 }
0116 
0117 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
0118                         unsigned int pin)
0119 {
0120     const struct tegra_gpio_port *port;
0121     unsigned int offset;
0122 
0123     port = tegra186_gpio_get_port(gpio, &pin);
0124     if (!port)
0125         return NULL;
0126 
0127     offset = port->bank * 0x1000 + port->port * 0x200;
0128 
0129     return gpio->base + offset + pin * 0x20;
0130 }
0131 
0132 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
0133                        unsigned int offset)
0134 {
0135     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0136     void __iomem *base;
0137     u32 value;
0138 
0139     base = tegra186_gpio_get_base(gpio, offset);
0140     if (WARN_ON(base == NULL))
0141         return -ENODEV;
0142 
0143     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0144     if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
0145         return GPIO_LINE_DIRECTION_OUT;
0146 
0147     return GPIO_LINE_DIRECTION_IN;
0148 }
0149 
0150 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
0151                      unsigned int offset)
0152 {
0153     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0154     void __iomem *base;
0155     u32 value;
0156 
0157     base = tegra186_gpio_get_base(gpio, offset);
0158     if (WARN_ON(base == NULL))
0159         return -ENODEV;
0160 
0161     value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
0162     value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
0163     writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
0164 
0165     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0166     value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
0167     value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
0168     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0169 
0170     return 0;
0171 }
0172 
0173 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
0174                       unsigned int offset, int level)
0175 {
0176     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0177     void __iomem *base;
0178     u32 value;
0179 
0180     /* configure output level first */
0181     chip->set(chip, offset, level);
0182 
0183     base = tegra186_gpio_get_base(gpio, offset);
0184     if (WARN_ON(base == NULL))
0185         return -EINVAL;
0186 
0187     /* set the direction */
0188     value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
0189     value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
0190     writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
0191 
0192     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0193     value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
0194     value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
0195     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0196 
0197     return 0;
0198 }
0199 
0200 #define HTE_BOTH_EDGES  (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
0201 
0202 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
0203                   unsigned long flags)
0204 {
0205     struct tegra_gpio *gpio;
0206     void __iomem *base;
0207     int value;
0208 
0209     if (!gc)
0210         return -EINVAL;
0211 
0212     gpio = gpiochip_get_data(gc);
0213     if (!gpio)
0214         return -ENODEV;
0215 
0216     base = tegra186_gpio_get_base(gpio, offset);
0217     if (WARN_ON(base == NULL))
0218         return -EINVAL;
0219 
0220     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0221     value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
0222 
0223     if (flags == HTE_BOTH_EDGES) {
0224         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
0225     } else if (flags == HTE_RISING_EDGE_TS) {
0226         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
0227         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
0228     } else if (flags == HTE_FALLING_EDGE_TS) {
0229         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
0230     }
0231 
0232     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0233 
0234     return 0;
0235 }
0236 
0237 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
0238                    unsigned long flags)
0239 {
0240     struct tegra_gpio *gpio;
0241     void __iomem *base;
0242     int value;
0243 
0244     if (!gc)
0245         return -EINVAL;
0246 
0247     gpio = gpiochip_get_data(gc);
0248     if (!gpio)
0249         return -ENODEV;
0250 
0251     base = tegra186_gpio_get_base(gpio, offset);
0252     if (WARN_ON(base == NULL))
0253         return -EINVAL;
0254 
0255     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0256     value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
0257     if (flags == HTE_BOTH_EDGES) {
0258         value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
0259     } else if (flags == HTE_RISING_EDGE_TS) {
0260         value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
0261         value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
0262     } else if (flags == HTE_FALLING_EDGE_TS) {
0263         value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
0264     }
0265     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0266 
0267     return 0;
0268 }
0269 
0270 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
0271 {
0272     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0273     void __iomem *base;
0274     u32 value;
0275 
0276     base = tegra186_gpio_get_base(gpio, offset);
0277     if (WARN_ON(base == NULL))
0278         return -ENODEV;
0279 
0280     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0281     if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
0282         value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
0283     else
0284         value = readl(base + TEGRA186_GPIO_INPUT);
0285 
0286     return value & BIT(0);
0287 }
0288 
0289 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
0290                   int level)
0291 {
0292     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0293     void __iomem *base;
0294     u32 value;
0295 
0296     base = tegra186_gpio_get_base(gpio, offset);
0297     if (WARN_ON(base == NULL))
0298         return;
0299 
0300     value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
0301     if (level == 0)
0302         value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
0303     else
0304         value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
0305 
0306     writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
0307 }
0308 
0309 static int tegra186_gpio_set_config(struct gpio_chip *chip,
0310                     unsigned int offset,
0311                     unsigned long config)
0312 {
0313     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0314     u32 debounce, value;
0315     void __iomem *base;
0316 
0317     base = tegra186_gpio_get_base(gpio, offset);
0318     if (base == NULL)
0319         return -ENXIO;
0320 
0321     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0322         return -ENOTSUPP;
0323 
0324     debounce = pinconf_to_config_argument(config);
0325 
0326     /*
0327      * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
0328      * time.
0329      */
0330     if (debounce > 255000)
0331         return -EINVAL;
0332 
0333     debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
0334 
0335     value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
0336     writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
0337 
0338     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0339     value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
0340     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0341 
0342     return 0;
0343 }
0344 
0345 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
0346 {
0347     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0348     struct pinctrl_dev *pctldev;
0349     struct device_node *np;
0350     unsigned int i, j;
0351     int err;
0352 
0353     if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
0354         return 0;
0355 
0356     np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
0357     if (!np)
0358         return -ENODEV;
0359 
0360     pctldev = of_pinctrl_get(np);
0361     of_node_put(np);
0362     if (!pctldev)
0363         return -EPROBE_DEFER;
0364 
0365     for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
0366         unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
0367         const char *group = gpio->soc->pin_ranges[i].group;
0368 
0369         port = pin / 8;
0370         pin = pin % 8;
0371 
0372         if (port >= gpio->soc->num_ports) {
0373             dev_warn(chip->parent, "invalid port %u for %s\n",
0374                  port, group);
0375             continue;
0376         }
0377 
0378         for (j = 0; j < port; j++)
0379             pin += gpio->soc->ports[j].pins;
0380 
0381         err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
0382         if (err < 0)
0383             return err;
0384     }
0385 
0386     return 0;
0387 }
0388 
0389 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
0390                   const struct of_phandle_args *spec,
0391                   u32 *flags)
0392 {
0393     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0394     unsigned int port, pin, i, offset = 0;
0395 
0396     if (WARN_ON(chip->of_gpio_n_cells < 2))
0397         return -EINVAL;
0398 
0399     if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
0400         return -EINVAL;
0401 
0402     port = spec->args[0] / 8;
0403     pin = spec->args[0] % 8;
0404 
0405     if (port >= gpio->soc->num_ports) {
0406         dev_err(chip->parent, "invalid port number: %u\n", port);
0407         return -EINVAL;
0408     }
0409 
0410     for (i = 0; i < port; i++)
0411         offset += gpio->soc->ports[i].pins;
0412 
0413     if (flags)
0414         *flags = spec->args[1];
0415 
0416     return offset + pin;
0417 }
0418 
0419 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
0420 
0421 static void tegra186_irq_ack(struct irq_data *data)
0422 {
0423     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0424     struct tegra_gpio *gpio = to_tegra_gpio(gc);
0425     void __iomem *base;
0426 
0427     base = tegra186_gpio_get_base(gpio, data->hwirq);
0428     if (WARN_ON(base == NULL))
0429         return;
0430 
0431     writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
0432 }
0433 
0434 static void tegra186_irq_mask(struct irq_data *data)
0435 {
0436     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0437     struct tegra_gpio *gpio = to_tegra_gpio(gc);
0438     void __iomem *base;
0439     u32 value;
0440 
0441     base = tegra186_gpio_get_base(gpio, data->hwirq);
0442     if (WARN_ON(base == NULL))
0443         return;
0444 
0445     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0446     value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
0447     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0448 
0449     gpiochip_disable_irq(&gpio->gpio, data->hwirq);
0450 }
0451 
0452 static void tegra186_irq_unmask(struct irq_data *data)
0453 {
0454     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0455     struct tegra_gpio *gpio = to_tegra_gpio(gc);
0456     void __iomem *base;
0457     u32 value;
0458 
0459     base = tegra186_gpio_get_base(gpio, data->hwirq);
0460     if (WARN_ON(base == NULL))
0461         return;
0462 
0463     gpiochip_enable_irq(&gpio->gpio, data->hwirq);
0464 
0465     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0466     value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
0467     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0468 }
0469 
0470 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
0471 {
0472     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0473     struct tegra_gpio *gpio = to_tegra_gpio(gc);
0474     void __iomem *base;
0475     u32 value;
0476 
0477     base = tegra186_gpio_get_base(gpio, data->hwirq);
0478     if (WARN_ON(base == NULL))
0479         return -ENODEV;
0480 
0481     value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
0482     value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
0483     value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
0484 
0485     switch (type & IRQ_TYPE_SENSE_MASK) {
0486     case IRQ_TYPE_NONE:
0487         break;
0488 
0489     case IRQ_TYPE_EDGE_RISING:
0490         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
0491         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
0492         break;
0493 
0494     case IRQ_TYPE_EDGE_FALLING:
0495         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
0496         break;
0497 
0498     case IRQ_TYPE_EDGE_BOTH:
0499         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
0500         break;
0501 
0502     case IRQ_TYPE_LEVEL_HIGH:
0503         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
0504         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
0505         break;
0506 
0507     case IRQ_TYPE_LEVEL_LOW:
0508         value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
0509         break;
0510 
0511     default:
0512         return -EINVAL;
0513     }
0514 
0515     writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
0516 
0517     if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
0518         irq_set_handler_locked(data, handle_level_irq);
0519     else
0520         irq_set_handler_locked(data, handle_edge_irq);
0521 
0522     if (data->parent_data)
0523         return irq_chip_set_type_parent(data, type);
0524 
0525     return 0;
0526 }
0527 
0528 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
0529 {
0530     if (data->parent_data)
0531         return irq_chip_set_wake_parent(data, on);
0532 
0533     return 0;
0534 }
0535 
0536 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
0537 {
0538     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0539 
0540     seq_printf(p, dev_name(gc->parent));
0541 }
0542 
0543 static const struct irq_chip tegra186_gpio_irq_chip = {
0544     .irq_ack        = tegra186_irq_ack,
0545     .irq_mask       = tegra186_irq_mask,
0546     .irq_unmask     = tegra186_irq_unmask,
0547     .irq_set_type       = tegra186_irq_set_type,
0548     .irq_set_wake       = tegra186_irq_set_wake,
0549     .irq_print_chip     = tegra186_irq_print_chip,
0550     .flags          = IRQCHIP_IMMUTABLE,
0551     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0552 };
0553 
0554 static void tegra186_gpio_irq(struct irq_desc *desc)
0555 {
0556     struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
0557     struct irq_domain *domain = gpio->gpio.irq.domain;
0558     struct irq_chip *chip = irq_desc_get_chip(desc);
0559     unsigned int parent = irq_desc_get_irq(desc);
0560     unsigned int i, j, offset = 0;
0561 
0562     chained_irq_enter(chip, desc);
0563 
0564     for (i = 0; i < gpio->soc->num_ports; i++) {
0565         const struct tegra_gpio_port *port = &gpio->soc->ports[i];
0566         unsigned int pin;
0567         unsigned long value;
0568         void __iomem *base;
0569 
0570         base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
0571 
0572         /* skip ports that are not associated with this bank */
0573         for (j = 0; j < gpio->num_irqs_per_bank; j++) {
0574             if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
0575                 break;
0576         }
0577 
0578         if (j == gpio->num_irqs_per_bank)
0579             goto skip;
0580 
0581         value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
0582 
0583         for_each_set_bit(pin, &value, port->pins) {
0584             int ret = generic_handle_domain_irq(domain, offset + pin);
0585             WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
0586         }
0587 
0588 skip:
0589         offset += port->pins;
0590     }
0591 
0592     chained_irq_exit(chip, desc);
0593 }
0594 
0595 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
0596                           struct irq_fwspec *fwspec,
0597                           unsigned long *hwirq,
0598                           unsigned int *type)
0599 {
0600     struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
0601     unsigned int port, pin, i, offset = 0;
0602 
0603     if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
0604         return -EINVAL;
0605 
0606     if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
0607         return -EINVAL;
0608 
0609     port = fwspec->param[0] / 8;
0610     pin = fwspec->param[0] % 8;
0611 
0612     if (port >= gpio->soc->num_ports)
0613         return -EINVAL;
0614 
0615     for (i = 0; i < port; i++)
0616         offset += gpio->soc->ports[i].pins;
0617 
0618     *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
0619     *hwirq = offset + pin;
0620 
0621     return 0;
0622 }
0623 
0624 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
0625                         union gpio_irq_fwspec *gfwspec,
0626                         unsigned int parent_hwirq,
0627                         unsigned int parent_type)
0628 {
0629     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0630     struct irq_fwspec *fwspec = &gfwspec->fwspec;
0631 
0632     fwspec->fwnode = chip->irq.parent_domain->fwnode;
0633     fwspec->param_count = 3;
0634     fwspec->param[0] = gpio->soc->instance;
0635     fwspec->param[1] = parent_hwirq;
0636     fwspec->param[2] = parent_type;
0637 
0638     return 0;
0639 }
0640 
0641 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
0642                            unsigned int hwirq,
0643                            unsigned int type,
0644                            unsigned int *parent_hwirq,
0645                            unsigned int *parent_type)
0646 {
0647     *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
0648     *parent_type = type;
0649 
0650     return 0;
0651 }
0652 
0653 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
0654                               unsigned int offset)
0655 {
0656     struct tegra_gpio *gpio = gpiochip_get_data(chip);
0657     unsigned int i;
0658 
0659     for (i = 0; i < gpio->soc->num_ports; i++) {
0660         if (offset < gpio->soc->ports[i].pins)
0661             break;
0662 
0663         offset -= gpio->soc->ports[i].pins;
0664     }
0665 
0666     return offset + i * 8;
0667 }
0668 
0669 static const struct of_device_id tegra186_pmc_of_match[] = {
0670     { .compatible = "nvidia,tegra186-pmc" },
0671     { .compatible = "nvidia,tegra194-pmc" },
0672     { /* sentinel */ }
0673 };
0674 
0675 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
0676 {
0677     struct device *dev = gpio->gpio.parent;
0678     unsigned int i, j;
0679     u32 value;
0680 
0681     for (i = 0; i < gpio->soc->num_ports; i++) {
0682         const struct tegra_gpio_port *port = &gpio->soc->ports[i];
0683         unsigned int offset, p = port->port;
0684         void __iomem *base;
0685 
0686         base = gpio->secure + port->bank * 0x1000 + 0x800;
0687 
0688         value = readl(base + TEGRA186_GPIO_CTL_SCR);
0689 
0690         /*
0691          * For controllers that haven't been locked down yet, make
0692          * sure to program the default interrupt route mapping.
0693          */
0694         if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
0695             (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
0696             /*
0697              * On Tegra194 and later, each pin can be routed to one or more
0698              * interrupts.
0699              */
0700             for (j = 0; j < gpio->num_irqs_per_bank; j++) {
0701                 dev_dbg(dev, "programming default interrupt routing for port %s\n",
0702                     port->name);
0703 
0704                 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
0705 
0706                 /*
0707                  * By default we only want to route GPIO pins to IRQ 0. This works
0708                  * only under the assumption that we're running as the host kernel
0709                  * and hence all GPIO pins are owned by Linux.
0710                  *
0711                  * For cases where Linux is the guest OS, the hypervisor will have
0712                  * to configure the interrupt routing and pass only the valid
0713                  * interrupts via device tree.
0714                  */
0715                 if (j == 0) {
0716                     value = readl(base + offset);
0717                     value = BIT(port->pins) - 1;
0718                     writel(value, base + offset);
0719                 }
0720             }
0721         }
0722     }
0723 }
0724 
0725 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
0726 {
0727     struct device *dev = gpio->gpio.parent;
0728 
0729     if (gpio->num_irq > gpio->num_banks) {
0730         if (gpio->num_irq % gpio->num_banks != 0)
0731             goto error;
0732     }
0733 
0734     if (gpio->num_irq < gpio->num_banks)
0735         goto error;
0736 
0737     gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
0738 
0739     if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
0740         goto error;
0741 
0742     return 0;
0743 
0744 error:
0745     dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
0746         gpio->num_irq, gpio->num_banks);
0747     return -EINVAL;
0748 }
0749 
0750 static int tegra186_gpio_probe(struct platform_device *pdev)
0751 {
0752     unsigned int i, j, offset;
0753     struct gpio_irq_chip *irq;
0754     struct tegra_gpio *gpio;
0755     struct device_node *np;
0756     char **names;
0757     int err;
0758 
0759     gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
0760     if (!gpio)
0761         return -ENOMEM;
0762 
0763     gpio->soc = device_get_match_data(&pdev->dev);
0764     gpio->gpio.label = gpio->soc->name;
0765     gpio->gpio.parent = &pdev->dev;
0766 
0767     /* count the number of banks in the controller */
0768     for (i = 0; i < gpio->soc->num_ports; i++)
0769         if (gpio->soc->ports[i].bank > gpio->num_banks)
0770             gpio->num_banks = gpio->soc->ports[i].bank;
0771 
0772     gpio->num_banks++;
0773 
0774     /* get register apertures */
0775     gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
0776     if (IS_ERR(gpio->secure)) {
0777         gpio->secure = devm_platform_ioremap_resource(pdev, 0);
0778         if (IS_ERR(gpio->secure))
0779             return PTR_ERR(gpio->secure);
0780     }
0781 
0782     gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
0783     if (IS_ERR(gpio->base)) {
0784         gpio->base = devm_platform_ioremap_resource(pdev, 1);
0785         if (IS_ERR(gpio->base))
0786             return PTR_ERR(gpio->base);
0787     }
0788 
0789     err = platform_irq_count(pdev);
0790     if (err < 0)
0791         return err;
0792 
0793     gpio->num_irq = err;
0794 
0795     err = tegra186_gpio_irqs_per_bank(gpio);
0796     if (err < 0)
0797         return err;
0798 
0799     gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
0800                  GFP_KERNEL);
0801     if (!gpio->irq)
0802         return -ENOMEM;
0803 
0804     for (i = 0; i < gpio->num_irq; i++) {
0805         err = platform_get_irq(pdev, i);
0806         if (err < 0)
0807             return err;
0808 
0809         gpio->irq[i] = err;
0810     }
0811 
0812     gpio->gpio.request = gpiochip_generic_request;
0813     gpio->gpio.free = gpiochip_generic_free;
0814     gpio->gpio.get_direction = tegra186_gpio_get_direction;
0815     gpio->gpio.direction_input = tegra186_gpio_direction_input;
0816     gpio->gpio.direction_output = tegra186_gpio_direction_output;
0817     gpio->gpio.get = tegra186_gpio_get;
0818     gpio->gpio.set = tegra186_gpio_set;
0819     gpio->gpio.set_config = tegra186_gpio_set_config;
0820     gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
0821     if (gpio->soc->has_gte) {
0822         gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
0823         gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
0824     }
0825 
0826     gpio->gpio.base = -1;
0827 
0828     for (i = 0; i < gpio->soc->num_ports; i++)
0829         gpio->gpio.ngpio += gpio->soc->ports[i].pins;
0830 
0831     names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
0832                  sizeof(*names), GFP_KERNEL);
0833     if (!names)
0834         return -ENOMEM;
0835 
0836     for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
0837         const struct tegra_gpio_port *port = &gpio->soc->ports[i];
0838         char *name;
0839 
0840         for (j = 0; j < port->pins; j++) {
0841             name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
0842                           "P%s.%02x", port->name, j);
0843             if (!name)
0844                 return -ENOMEM;
0845 
0846             names[offset + j] = name;
0847         }
0848 
0849         offset += port->pins;
0850     }
0851 
0852     gpio->gpio.names = (const char * const *)names;
0853 
0854 #if defined(CONFIG_OF_GPIO)
0855     gpio->gpio.of_gpio_n_cells = 2;
0856     gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
0857 #endif /* CONFIG_OF_GPIO */
0858 
0859     irq = &gpio->gpio.irq;
0860     gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
0861     irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
0862     irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
0863     irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
0864     irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
0865     irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
0866     irq->handler = handle_simple_irq;
0867     irq->default_type = IRQ_TYPE_NONE;
0868     irq->parent_handler = tegra186_gpio_irq;
0869     irq->parent_handler_data = gpio;
0870     irq->num_parents = gpio->num_irq;
0871 
0872     /*
0873      * To simplify things, use a single interrupt per bank for now. Some
0874      * chips support up to 8 interrupts per bank, which can be useful to
0875      * distribute the load and decrease the processing latency for GPIOs
0876      * but it also requires a more complicated interrupt routing than we
0877      * currently program.
0878      */
0879     if (gpio->num_irqs_per_bank > 1) {
0880         irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
0881                         sizeof(*irq->parents), GFP_KERNEL);
0882         if (!irq->parents)
0883             return -ENOMEM;
0884 
0885         for (i = 0; i < gpio->num_banks; i++)
0886             irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
0887 
0888         irq->num_parents = gpio->num_banks;
0889     } else {
0890         irq->num_parents = gpio->num_irq;
0891         irq->parents = gpio->irq;
0892     }
0893 
0894     if (gpio->soc->num_irqs_per_bank > 1)
0895         tegra186_gpio_init_route_mapping(gpio);
0896 
0897     np = of_find_matching_node(NULL, tegra186_pmc_of_match);
0898     if (np) {
0899         irq->parent_domain = irq_find_host(np);
0900         of_node_put(np);
0901 
0902         if (!irq->parent_domain)
0903             return -EPROBE_DEFER;
0904     }
0905 
0906     irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
0907                 sizeof(*irq->map), GFP_KERNEL);
0908     if (!irq->map)
0909         return -ENOMEM;
0910 
0911     for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
0912         const struct tegra_gpio_port *port = &gpio->soc->ports[i];
0913 
0914         for (j = 0; j < port->pins; j++)
0915             irq->map[offset + j] = irq->parents[port->bank];
0916 
0917         offset += port->pins;
0918     }
0919 
0920     return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
0921 }
0922 
0923 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
0924     [TEGRA186_MAIN_GPIO_PORT_##_name] = {           \
0925         .name = #_name,                 \
0926         .bank = _bank,                  \
0927         .port = _port,                  \
0928         .pins = _pins,                  \
0929     }
0930 
0931 static const struct tegra_gpio_port tegra186_main_ports[] = {
0932     TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
0933     TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
0934     TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
0935     TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
0936     TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
0937     TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
0938     TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
0939     TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
0940     TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
0941     TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
0942     TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
0943     TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
0944     TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
0945     TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
0946     TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
0947     TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
0948     TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
0949     TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
0950     TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
0951     TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
0952     TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
0953     TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
0954     TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
0955 };
0956 
0957 static const struct tegra_gpio_soc tegra186_main_soc = {
0958     .num_ports = ARRAY_SIZE(tegra186_main_ports),
0959     .ports = tegra186_main_ports,
0960     .name = "tegra186-gpio",
0961     .instance = 0,
0962     .num_irqs_per_bank = 1,
0963 };
0964 
0965 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins)  \
0966     [TEGRA186_AON_GPIO_PORT_##_name] = {            \
0967         .name = #_name,                 \
0968         .bank = _bank,                  \
0969         .port = _port,                  \
0970         .pins = _pins,                  \
0971     }
0972 
0973 static const struct tegra_gpio_port tegra186_aon_ports[] = {
0974     TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
0975     TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
0976     TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
0977     TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
0978     TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
0979     TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
0980     TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
0981     TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
0982 };
0983 
0984 static const struct tegra_gpio_soc tegra186_aon_soc = {
0985     .num_ports = ARRAY_SIZE(tegra186_aon_ports),
0986     .ports = tegra186_aon_ports,
0987     .name = "tegra186-gpio-aon",
0988     .instance = 1,
0989     .num_irqs_per_bank = 1,
0990 };
0991 
0992 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
0993     [TEGRA194_MAIN_GPIO_PORT_##_name] = {           \
0994         .name = #_name,                 \
0995         .bank = _bank,                  \
0996         .port = _port,                  \
0997         .pins = _pins,                  \
0998     }
0999 
1000 static const struct tegra_gpio_port tegra194_main_ports[] = {
1001     TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1002     TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1003     TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1004     TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1005     TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1006     TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1007     TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1008     TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1009     TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1010     TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1011     TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1012     TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1013     TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1014     TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1015     TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1016     TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1017     TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1018     TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1019     TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1020     TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1021     TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1022     TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1023     TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1024     TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1025     TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1026     TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1027     TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1028     TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1029 };
1030 
1031 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1032     { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1033     { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1034 };
1035 
1036 static const struct tegra_gpio_soc tegra194_main_soc = {
1037     .num_ports = ARRAY_SIZE(tegra194_main_ports),
1038     .ports = tegra194_main_ports,
1039     .name = "tegra194-gpio",
1040     .instance = 0,
1041     .num_irqs_per_bank = 8,
1042     .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1043     .pin_ranges = tegra194_main_pin_ranges,
1044     .pinmux = "nvidia,tegra194-pinmux",
1045 };
1046 
1047 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins)  \
1048     [TEGRA194_AON_GPIO_PORT_##_name] = {            \
1049         .name = #_name,                 \
1050         .bank = _bank,                  \
1051         .port = _port,                  \
1052         .pins = _pins,                  \
1053     }
1054 
1055 static const struct tegra_gpio_port tegra194_aon_ports[] = {
1056     TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1057     TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1058     TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1059     TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1060     TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1061 };
1062 
1063 static const struct tegra_gpio_soc tegra194_aon_soc = {
1064     .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1065     .ports = tegra194_aon_ports,
1066     .name = "tegra194-gpio-aon",
1067     .instance = 1,
1068     .num_irqs_per_bank = 8,
1069     .has_gte = true,
1070 };
1071 
1072 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1073     [TEGRA234_MAIN_GPIO_PORT_##_name] = {           \
1074         .name = #_name,                 \
1075         .bank = _bank,                  \
1076         .port = _port,                  \
1077         .pins = _pins,                  \
1078     }
1079 
1080 static const struct tegra_gpio_port tegra234_main_ports[] = {
1081     TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1082     TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1083     TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1084     TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1085     TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1086     TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1087     TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1088     TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1089     TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1090     TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1091     TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1092     TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1093     TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1094     TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1095     TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1096     TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1097     TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1098     TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1099     TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1100     TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1101     TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1102     TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1103     TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1104     TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1105     TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1106 };
1107 
1108 static const struct tegra_gpio_soc tegra234_main_soc = {
1109     .num_ports = ARRAY_SIZE(tegra234_main_ports),
1110     .ports = tegra234_main_ports,
1111     .name = "tegra234-gpio",
1112     .instance = 0,
1113     .num_irqs_per_bank = 8,
1114 };
1115 
1116 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins)  \
1117     [TEGRA234_AON_GPIO_PORT_##_name] = {            \
1118         .name = #_name,                 \
1119         .bank = _bank,                  \
1120         .port = _port,                  \
1121         .pins = _pins,                  \
1122     }
1123 
1124 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1125     TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1126     TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1127     TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1128     TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1129     TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1130     TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1131 };
1132 
1133 static const struct tegra_gpio_soc tegra234_aon_soc = {
1134     .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1135     .ports = tegra234_aon_ports,
1136     .name = "tegra234-gpio-aon",
1137     .instance = 1,
1138     .num_irqs_per_bank = 8,
1139 };
1140 
1141 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1142     [TEGRA241_MAIN_GPIO_PORT_##_name] = {           \
1143         .name = #_name,                 \
1144         .bank = _bank,                  \
1145         .port = _port,                  \
1146         .pins = _pins,                  \
1147     }
1148 
1149 static const struct tegra_gpio_port tegra241_main_ports[] = {
1150     TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1151     TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1152     TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1153     TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1154     TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1155     TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1156     TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1157     TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1158     TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1159     TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1160     TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1161 };
1162 
1163 static const struct tegra_gpio_soc tegra241_main_soc = {
1164     .num_ports = ARRAY_SIZE(tegra241_main_ports),
1165     .ports = tegra241_main_ports,
1166     .name = "tegra241-gpio",
1167     .instance = 0,
1168     .num_irqs_per_bank = 8,
1169 };
1170 
1171 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins)  \
1172     [TEGRA241_AON_GPIO_PORT_##_name] = {            \
1173         .name = #_name,                 \
1174         .bank = _bank,                  \
1175         .port = _port,                  \
1176         .pins = _pins,                  \
1177     }
1178 
1179 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1180     TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1181     TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1182 };
1183 
1184 static const struct tegra_gpio_soc tegra241_aon_soc = {
1185     .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1186     .ports = tegra241_aon_ports,
1187     .name = "tegra241-gpio-aon",
1188     .instance = 1,
1189     .num_irqs_per_bank = 8,
1190 };
1191 
1192 static const struct of_device_id tegra186_gpio_of_match[] = {
1193     {
1194         .compatible = "nvidia,tegra186-gpio",
1195         .data = &tegra186_main_soc
1196     }, {
1197         .compatible = "nvidia,tegra186-gpio-aon",
1198         .data = &tegra186_aon_soc
1199     }, {
1200         .compatible = "nvidia,tegra194-gpio",
1201         .data = &tegra194_main_soc
1202     }, {
1203         .compatible = "nvidia,tegra194-gpio-aon",
1204         .data = &tegra194_aon_soc
1205     }, {
1206         .compatible = "nvidia,tegra234-gpio",
1207         .data = &tegra234_main_soc
1208     }, {
1209         .compatible = "nvidia,tegra234-gpio-aon",
1210         .data = &tegra234_aon_soc
1211     }, {
1212         /* sentinel */
1213     }
1214 };
1215 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1216 
1217 static const struct acpi_device_id  tegra186_gpio_acpi_match[] = {
1218     { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1219     { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1220     { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1221     { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1222     { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1223     { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1224     {}
1225 };
1226 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1227 
1228 static struct platform_driver tegra186_gpio_driver = {
1229     .driver = {
1230         .name = "tegra186-gpio",
1231         .of_match_table = tegra186_gpio_of_match,
1232         .acpi_match_table = tegra186_gpio_acpi_match,
1233     },
1234     .probe = tegra186_gpio_probe,
1235 };
1236 module_platform_driver(tegra186_gpio_driver);
1237 
1238 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1239 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1240 MODULE_LICENSE("GPL v2");
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