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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-tegra/gpio.c
0004  *
0005  * Copyright (c) 2010 Google, Inc
0006  * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
0007  *
0008  * Author:
0009  *  Erik Gilling <konkers@google.com>
0010  */
0011 
0012 #include <linux/err.h>
0013 #include <linux/init.h>
0014 #include <linux/irq.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/module.h>
0021 #include <linux/irqdomain.h>
0022 #include <linux/irqchip/chained_irq.h>
0023 #include <linux/pinctrl/consumer.h>
0024 #include <linux/pm.h>
0025 
0026 #define GPIO_BANK(x)        ((x) >> 5)
0027 #define GPIO_PORT(x)        (((x) >> 3) & 0x3)
0028 #define GPIO_BIT(x)     ((x) & 0x7)
0029 
0030 #define GPIO_REG(tgi, x)    (GPIO_BANK(x) * tgi->soc->bank_stride + \
0031                     GPIO_PORT(x) * 4)
0032 
0033 #define GPIO_CNF(t, x)      (GPIO_REG(t, x) + 0x00)
0034 #define GPIO_OE(t, x)       (GPIO_REG(t, x) + 0x10)
0035 #define GPIO_OUT(t, x)      (GPIO_REG(t, x) + 0X20)
0036 #define GPIO_IN(t, x)       (GPIO_REG(t, x) + 0x30)
0037 #define GPIO_INT_STA(t, x)  (GPIO_REG(t, x) + 0x40)
0038 #define GPIO_INT_ENB(t, x)  (GPIO_REG(t, x) + 0x50)
0039 #define GPIO_INT_LVL(t, x)  (GPIO_REG(t, x) + 0x60)
0040 #define GPIO_INT_CLR(t, x)  (GPIO_REG(t, x) + 0x70)
0041 #define GPIO_DBC_CNT(t, x)  (GPIO_REG(t, x) + 0xF0)
0042 
0043 
0044 #define GPIO_MSK_CNF(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
0045 #define GPIO_MSK_OE(t, x)   (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
0046 #define GPIO_MSK_OUT(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
0047 #define GPIO_MSK_DBC_EN(t, x)   (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
0048 #define GPIO_MSK_INT_STA(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
0049 #define GPIO_MSK_INT_ENB(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
0050 #define GPIO_MSK_INT_LVL(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
0051 
0052 #define GPIO_INT_LVL_MASK       0x010101
0053 #define GPIO_INT_LVL_EDGE_RISING    0x000101
0054 #define GPIO_INT_LVL_EDGE_FALLING   0x000100
0055 #define GPIO_INT_LVL_EDGE_BOTH      0x010100
0056 #define GPIO_INT_LVL_LEVEL_HIGH     0x000001
0057 #define GPIO_INT_LVL_LEVEL_LOW      0x000000
0058 
0059 struct tegra_gpio_info;
0060 
0061 struct tegra_gpio_bank {
0062     unsigned int bank;
0063 
0064     /*
0065      * IRQ-core code uses raw locking, and thus, nested locking also
0066      * should be raw in order not to trip spinlock debug warnings.
0067      */
0068     raw_spinlock_t lvl_lock[4];
0069 
0070     /* Lock for updating debounce count register */
0071     spinlock_t dbc_lock[4];
0072 
0073 #ifdef CONFIG_PM_SLEEP
0074     u32 cnf[4];
0075     u32 out[4];
0076     u32 oe[4];
0077     u32 int_enb[4];
0078     u32 int_lvl[4];
0079     u32 wake_enb[4];
0080     u32 dbc_enb[4];
0081 #endif
0082     u32 dbc_cnt[4];
0083 };
0084 
0085 struct tegra_gpio_soc_config {
0086     bool debounce_supported;
0087     u32 bank_stride;
0088     u32 upper_offset;
0089 };
0090 
0091 struct tegra_gpio_info {
0092     struct device               *dev;
0093     void __iomem                *regs;
0094     struct tegra_gpio_bank          *bank_info;
0095     const struct tegra_gpio_soc_config  *soc;
0096     struct gpio_chip            gc;
0097     struct irq_chip             ic;
0098     u32                 bank_count;
0099     unsigned int                *irqs;
0100 };
0101 
0102 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
0103                      u32 val, u32 reg)
0104 {
0105     writel_relaxed(val, tgi->regs + reg);
0106 }
0107 
0108 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
0109 {
0110     return readl_relaxed(tgi->regs + reg);
0111 }
0112 
0113 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
0114                        unsigned int bit)
0115 {
0116     return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
0117 }
0118 
0119 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
0120                   unsigned int gpio, u32 value)
0121 {
0122     u32 val;
0123 
0124     val = 0x100 << GPIO_BIT(gpio);
0125     if (value)
0126         val |= 1 << GPIO_BIT(gpio);
0127     tegra_gpio_writel(tgi, val, reg);
0128 }
0129 
0130 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
0131 {
0132     tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
0133 }
0134 
0135 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
0136 {
0137     tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
0138 }
0139 
0140 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
0141 {
0142     return pinctrl_gpio_request(chip->base + offset);
0143 }
0144 
0145 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
0146 {
0147     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0148 
0149     pinctrl_gpio_free(chip->base + offset);
0150     tegra_gpio_disable(tgi, offset);
0151 }
0152 
0153 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
0154                int value)
0155 {
0156     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0157 
0158     tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
0159 }
0160 
0161 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
0162 {
0163     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0164     unsigned int bval = BIT(GPIO_BIT(offset));
0165 
0166     /* If gpio is in output mode then read from the out value */
0167     if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
0168         return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
0169 
0170     return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
0171 }
0172 
0173 static int tegra_gpio_direction_input(struct gpio_chip *chip,
0174                       unsigned int offset)
0175 {
0176     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0177     int ret;
0178 
0179     tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
0180     tegra_gpio_enable(tgi, offset);
0181 
0182     ret = pinctrl_gpio_direction_input(chip->base + offset);
0183     if (ret < 0)
0184         dev_err(tgi->dev,
0185             "Failed to set pinctrl input direction of GPIO %d: %d",
0186              chip->base + offset, ret);
0187 
0188     return ret;
0189 }
0190 
0191 static int tegra_gpio_direction_output(struct gpio_chip *chip,
0192                        unsigned int offset,
0193                        int value)
0194 {
0195     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0196     int ret;
0197 
0198     tegra_gpio_set(chip, offset, value);
0199     tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
0200     tegra_gpio_enable(tgi, offset);
0201 
0202     ret = pinctrl_gpio_direction_output(chip->base + offset);
0203     if (ret < 0)
0204         dev_err(tgi->dev,
0205             "Failed to set pinctrl output direction of GPIO %d: %d",
0206              chip->base + offset, ret);
0207 
0208     return ret;
0209 }
0210 
0211 static int tegra_gpio_get_direction(struct gpio_chip *chip,
0212                     unsigned int offset)
0213 {
0214     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0215     u32 pin_mask = BIT(GPIO_BIT(offset));
0216     u32 cnf, oe;
0217 
0218     cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
0219     if (!(cnf & pin_mask))
0220         return -EINVAL;
0221 
0222     oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
0223 
0224     if (oe & pin_mask)
0225         return GPIO_LINE_DIRECTION_OUT;
0226 
0227     return GPIO_LINE_DIRECTION_IN;
0228 }
0229 
0230 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
0231                    unsigned int debounce)
0232 {
0233     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0234     struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
0235     unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
0236     unsigned long flags;
0237     unsigned int port;
0238 
0239     if (!debounce_ms) {
0240         tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
0241                       offset, 0);
0242         return 0;
0243     }
0244 
0245     debounce_ms = min(debounce_ms, 255U);
0246     port = GPIO_PORT(offset);
0247 
0248     /* There is only one debounce count register per port and hence
0249      * set the maximum of current and requested debounce time.
0250      */
0251     spin_lock_irqsave(&bank->dbc_lock[port], flags);
0252     if (bank->dbc_cnt[port] < debounce_ms) {
0253         tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
0254         bank->dbc_cnt[port] = debounce_ms;
0255     }
0256     spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
0257 
0258     tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
0259 
0260     return 0;
0261 }
0262 
0263 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
0264                  unsigned long config)
0265 {
0266     u32 debounce;
0267 
0268     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0269         return -ENOTSUPP;
0270 
0271     debounce = pinconf_to_config_argument(config);
0272     return tegra_gpio_set_debounce(chip, offset, debounce);
0273 }
0274 
0275 static void tegra_gpio_irq_ack(struct irq_data *d)
0276 {
0277     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0278     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0279     unsigned int gpio = d->hwirq;
0280 
0281     tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
0282 }
0283 
0284 static void tegra_gpio_irq_mask(struct irq_data *d)
0285 {
0286     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0287     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0288     unsigned int gpio = d->hwirq;
0289 
0290     tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
0291 }
0292 
0293 static void tegra_gpio_irq_unmask(struct irq_data *d)
0294 {
0295     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0296     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0297     unsigned int gpio = d->hwirq;
0298 
0299     tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
0300 }
0301 
0302 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0303 {
0304     unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
0305     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0306     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0307     struct tegra_gpio_bank *bank;
0308     unsigned long flags;
0309     int ret;
0310     u32 val;
0311 
0312     bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
0313 
0314     switch (type & IRQ_TYPE_SENSE_MASK) {
0315     case IRQ_TYPE_EDGE_RISING:
0316         lvl_type = GPIO_INT_LVL_EDGE_RISING;
0317         break;
0318 
0319     case IRQ_TYPE_EDGE_FALLING:
0320         lvl_type = GPIO_INT_LVL_EDGE_FALLING;
0321         break;
0322 
0323     case IRQ_TYPE_EDGE_BOTH:
0324         lvl_type = GPIO_INT_LVL_EDGE_BOTH;
0325         break;
0326 
0327     case IRQ_TYPE_LEVEL_HIGH:
0328         lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
0329         break;
0330 
0331     case IRQ_TYPE_LEVEL_LOW:
0332         lvl_type = GPIO_INT_LVL_LEVEL_LOW;
0333         break;
0334 
0335     default:
0336         return -EINVAL;
0337     }
0338 
0339     raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
0340 
0341     val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
0342     val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
0343     val |= lvl_type << GPIO_BIT(gpio);
0344     tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
0345 
0346     raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
0347 
0348     tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
0349     tegra_gpio_enable(tgi, gpio);
0350 
0351     ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
0352     if (ret) {
0353         dev_err(tgi->dev,
0354             "unable to lock Tegra GPIO %u as IRQ\n", gpio);
0355         tegra_gpio_disable(tgi, gpio);
0356         return ret;
0357     }
0358 
0359     if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
0360         irq_set_handler_locked(d, handle_level_irq);
0361     else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0362         irq_set_handler_locked(d, handle_edge_irq);
0363 
0364     if (d->parent_data)
0365         ret = irq_chip_set_type_parent(d, type);
0366 
0367     return ret;
0368 }
0369 
0370 static void tegra_gpio_irq_shutdown(struct irq_data *d)
0371 {
0372     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0373     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0374     unsigned int gpio = d->hwirq;
0375 
0376     tegra_gpio_irq_mask(d);
0377     gpiochip_unlock_as_irq(&tgi->gc, gpio);
0378 }
0379 
0380 static void tegra_gpio_irq_handler(struct irq_desc *desc)
0381 {
0382     struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
0383     struct irq_chip *chip = irq_desc_get_chip(desc);
0384     struct irq_domain *domain = tgi->gc.irq.domain;
0385     unsigned int irq = irq_desc_get_irq(desc);
0386     struct tegra_gpio_bank *bank = NULL;
0387     unsigned int port, pin, gpio, i;
0388     bool unmasked = false;
0389     unsigned long sta;
0390     u32 lvl;
0391 
0392     for (i = 0; i < tgi->bank_count; i++) {
0393         if (tgi->irqs[i] == irq) {
0394             bank = &tgi->bank_info[i];
0395             break;
0396         }
0397     }
0398 
0399     if (WARN_ON(bank == NULL))
0400         return;
0401 
0402     chained_irq_enter(chip, desc);
0403 
0404     for (port = 0; port < 4; port++) {
0405         gpio = tegra_gpio_compose(bank->bank, port, 0);
0406         sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
0407             tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
0408         lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
0409 
0410         for_each_set_bit(pin, &sta, 8) {
0411             int ret;
0412 
0413             tegra_gpio_writel(tgi, 1 << pin,
0414                       GPIO_INT_CLR(tgi, gpio));
0415 
0416             /* if gpio is edge triggered, clear condition
0417              * before executing the handler so that we don't
0418              * miss edges
0419              */
0420             if (!unmasked && lvl & (0x100 << pin)) {
0421                 unmasked = true;
0422                 chained_irq_exit(chip, desc);
0423             }
0424 
0425             ret = generic_handle_domain_irq(domain, gpio + pin);
0426             WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
0427         }
0428     }
0429 
0430     if (!unmasked)
0431         chained_irq_exit(chip, desc);
0432 }
0433 
0434 static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
0435                         unsigned int hwirq,
0436                         unsigned int type,
0437                         unsigned int *parent_hwirq,
0438                         unsigned int *parent_type)
0439 {
0440     *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
0441     *parent_type = type;
0442 
0443     return 0;
0444 }
0445 
0446 static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
0447                          union gpio_irq_fwspec *gfwspec,
0448                          unsigned int parent_hwirq,
0449                          unsigned int parent_type)
0450 {
0451     struct irq_fwspec *fwspec = &gfwspec->fwspec;
0452 
0453     fwspec->fwnode = chip->irq.parent_domain->fwnode;
0454     fwspec->param_count = 3;
0455     fwspec->param[0] = 0;
0456     fwspec->param[1] = parent_hwirq;
0457     fwspec->param[2] = parent_type;
0458 
0459     return 0;
0460 }
0461 
0462 #ifdef CONFIG_PM_SLEEP
0463 static int tegra_gpio_resume(struct device *dev)
0464 {
0465     struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
0466     unsigned int b, p;
0467 
0468     for (b = 0; b < tgi->bank_count; b++) {
0469         struct tegra_gpio_bank *bank = &tgi->bank_info[b];
0470 
0471         for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
0472             unsigned int gpio = (b << 5) | (p << 3);
0473 
0474             tegra_gpio_writel(tgi, bank->cnf[p],
0475                       GPIO_CNF(tgi, gpio));
0476 
0477             if (tgi->soc->debounce_supported) {
0478                 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
0479                           GPIO_DBC_CNT(tgi, gpio));
0480                 tegra_gpio_writel(tgi, bank->dbc_enb[p],
0481                           GPIO_MSK_DBC_EN(tgi, gpio));
0482             }
0483 
0484             tegra_gpio_writel(tgi, bank->out[p],
0485                       GPIO_OUT(tgi, gpio));
0486             tegra_gpio_writel(tgi, bank->oe[p],
0487                       GPIO_OE(tgi, gpio));
0488             tegra_gpio_writel(tgi, bank->int_lvl[p],
0489                       GPIO_INT_LVL(tgi, gpio));
0490             tegra_gpio_writel(tgi, bank->int_enb[p],
0491                       GPIO_INT_ENB(tgi, gpio));
0492         }
0493     }
0494 
0495     return 0;
0496 }
0497 
0498 static int tegra_gpio_suspend(struct device *dev)
0499 {
0500     struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
0501     unsigned int b, p;
0502 
0503     for (b = 0; b < tgi->bank_count; b++) {
0504         struct tegra_gpio_bank *bank = &tgi->bank_info[b];
0505 
0506         for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
0507             unsigned int gpio = (b << 5) | (p << 3);
0508 
0509             bank->cnf[p] = tegra_gpio_readl(tgi,
0510                             GPIO_CNF(tgi, gpio));
0511             bank->out[p] = tegra_gpio_readl(tgi,
0512                             GPIO_OUT(tgi, gpio));
0513             bank->oe[p] = tegra_gpio_readl(tgi,
0514                                GPIO_OE(tgi, gpio));
0515             if (tgi->soc->debounce_supported) {
0516                 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
0517                         GPIO_MSK_DBC_EN(tgi, gpio));
0518                 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
0519                             bank->dbc_enb[p];
0520             }
0521 
0522             bank->int_enb[p] = tegra_gpio_readl(tgi,
0523                         GPIO_INT_ENB(tgi, gpio));
0524             bank->int_lvl[p] = tegra_gpio_readl(tgi,
0525                         GPIO_INT_LVL(tgi, gpio));
0526 
0527             /* Enable gpio irq for wake up source */
0528             tegra_gpio_writel(tgi, bank->wake_enb[p],
0529                       GPIO_INT_ENB(tgi, gpio));
0530         }
0531     }
0532 
0533     return 0;
0534 }
0535 
0536 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
0537 {
0538     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0539     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0540     struct tegra_gpio_bank *bank;
0541     unsigned int gpio = d->hwirq;
0542     u32 port, bit, mask;
0543     int err;
0544 
0545     bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
0546 
0547     port = GPIO_PORT(gpio);
0548     bit = GPIO_BIT(gpio);
0549     mask = BIT(bit);
0550 
0551     err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
0552     if (err)
0553         return err;
0554 
0555     if (d->parent_data) {
0556         err = irq_chip_set_wake_parent(d, enable);
0557         if (err) {
0558             irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
0559             return err;
0560         }
0561     }
0562 
0563     if (enable)
0564         bank->wake_enb[port] |= mask;
0565     else
0566         bank->wake_enb[port] &= ~mask;
0567 
0568     return 0;
0569 }
0570 #endif
0571 
0572 static int tegra_gpio_irq_set_affinity(struct irq_data *data,
0573                        const struct cpumask *dest,
0574                        bool force)
0575 {
0576     if (data->parent_data)
0577         return irq_chip_set_affinity_parent(data, dest, force);
0578 
0579     return -EINVAL;
0580 }
0581 
0582 static int tegra_gpio_irq_request_resources(struct irq_data *d)
0583 {
0584     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0585     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0586 
0587     tegra_gpio_enable(tgi, d->hwirq);
0588 
0589     return gpiochip_reqres_irq(chip, d->hwirq);
0590 }
0591 
0592 static void tegra_gpio_irq_release_resources(struct irq_data *d)
0593 {
0594     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0595     struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
0596 
0597     gpiochip_relres_irq(chip, d->hwirq);
0598     tegra_gpio_enable(tgi, d->hwirq);
0599 }
0600 
0601 #ifdef  CONFIG_DEBUG_FS
0602 
0603 #include <linux/debugfs.h>
0604 #include <linux/seq_file.h>
0605 
0606 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
0607 {
0608     struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
0609     unsigned int i, j;
0610 
0611     for (i = 0; i < tgi->bank_count; i++) {
0612         for (j = 0; j < 4; j++) {
0613             unsigned int gpio = tegra_gpio_compose(i, j, 0);
0614 
0615             seq_printf(s,
0616                 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
0617                 i, j,
0618                 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
0619                 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
0620                 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
0621                 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
0622                 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
0623                 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
0624                 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
0625         }
0626     }
0627     return 0;
0628 }
0629 
0630 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
0631 {
0632     debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
0633                     tegra_dbg_gpio_show);
0634 }
0635 
0636 #else
0637 
0638 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
0639 {
0640 }
0641 
0642 #endif
0643 
0644 static const struct dev_pm_ops tegra_gpio_pm_ops = {
0645     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
0646 };
0647 
0648 static const struct of_device_id tegra_pmc_of_match[] = {
0649     { .compatible = "nvidia,tegra210-pmc", },
0650     { /* sentinel */ },
0651 };
0652 
0653 static int tegra_gpio_probe(struct platform_device *pdev)
0654 {
0655     struct tegra_gpio_bank *bank;
0656     struct tegra_gpio_info *tgi;
0657     struct gpio_irq_chip *irq;
0658     struct device_node *np;
0659     unsigned int i, j;
0660     int ret;
0661 
0662     tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
0663     if (!tgi)
0664         return -ENODEV;
0665 
0666     tgi->soc = of_device_get_match_data(&pdev->dev);
0667     tgi->dev = &pdev->dev;
0668 
0669     ret = platform_irq_count(pdev);
0670     if (ret < 0)
0671         return ret;
0672 
0673     tgi->bank_count = ret;
0674 
0675     if (!tgi->bank_count) {
0676         dev_err(&pdev->dev, "Missing IRQ resource\n");
0677         return -ENODEV;
0678     }
0679 
0680     tgi->gc.label           = "tegra-gpio";
0681     tgi->gc.request         = tegra_gpio_request;
0682     tgi->gc.free            = tegra_gpio_free;
0683     tgi->gc.direction_input     = tegra_gpio_direction_input;
0684     tgi->gc.get         = tegra_gpio_get;
0685     tgi->gc.direction_output    = tegra_gpio_direction_output;
0686     tgi->gc.set         = tegra_gpio_set;
0687     tgi->gc.get_direction       = tegra_gpio_get_direction;
0688     tgi->gc.base            = 0;
0689     tgi->gc.ngpio           = tgi->bank_count * 32;
0690     tgi->gc.parent          = &pdev->dev;
0691 
0692     tgi->ic.name            = "GPIO";
0693     tgi->ic.irq_ack         = tegra_gpio_irq_ack;
0694     tgi->ic.irq_mask        = tegra_gpio_irq_mask;
0695     tgi->ic.irq_unmask      = tegra_gpio_irq_unmask;
0696     tgi->ic.irq_set_type        = tegra_gpio_irq_set_type;
0697     tgi->ic.irq_shutdown        = tegra_gpio_irq_shutdown;
0698 #ifdef CONFIG_PM_SLEEP
0699     tgi->ic.irq_set_wake        = tegra_gpio_irq_set_wake;
0700 #endif
0701     tgi->ic.irq_request_resources   = tegra_gpio_irq_request_resources;
0702     tgi->ic.irq_release_resources   = tegra_gpio_irq_release_resources;
0703 
0704     platform_set_drvdata(pdev, tgi);
0705 
0706     if (tgi->soc->debounce_supported)
0707         tgi->gc.set_config = tegra_gpio_set_config;
0708 
0709     tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
0710                       sizeof(*tgi->bank_info), GFP_KERNEL);
0711     if (!tgi->bank_info)
0712         return -ENOMEM;
0713 
0714     tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
0715                  sizeof(*tgi->irqs), GFP_KERNEL);
0716     if (!tgi->irqs)
0717         return -ENOMEM;
0718 
0719     for (i = 0; i < tgi->bank_count; i++) {
0720         ret = platform_get_irq(pdev, i);
0721         if (ret < 0)
0722             return ret;
0723 
0724         bank = &tgi->bank_info[i];
0725         bank->bank = i;
0726 
0727         tgi->irqs[i] = ret;
0728 
0729         for (j = 0; j < 4; j++) {
0730             raw_spin_lock_init(&bank->lvl_lock[j]);
0731             spin_lock_init(&bank->dbc_lock[j]);
0732         }
0733     }
0734 
0735     irq = &tgi->gc.irq;
0736     irq->chip = &tgi->ic;
0737     irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
0738     irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
0739     irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
0740     irq->handler = handle_simple_irq;
0741     irq->default_type = IRQ_TYPE_NONE;
0742     irq->parent_handler = tegra_gpio_irq_handler;
0743     irq->parent_handler_data = tgi;
0744     irq->num_parents = tgi->bank_count;
0745     irq->parents = tgi->irqs;
0746 
0747     np = of_find_matching_node(NULL, tegra_pmc_of_match);
0748     if (np) {
0749         irq->parent_domain = irq_find_host(np);
0750         of_node_put(np);
0751 
0752         if (!irq->parent_domain)
0753             return -EPROBE_DEFER;
0754 
0755         tgi->ic.irq_set_affinity = tegra_gpio_irq_set_affinity;
0756     }
0757 
0758     tgi->regs = devm_platform_ioremap_resource(pdev, 0);
0759     if (IS_ERR(tgi->regs))
0760         return PTR_ERR(tgi->regs);
0761 
0762     for (i = 0; i < tgi->bank_count; i++) {
0763         for (j = 0; j < 4; j++) {
0764             int gpio = tegra_gpio_compose(i, j, 0);
0765 
0766             tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
0767         }
0768     }
0769 
0770     ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
0771     if (ret < 0)
0772         return ret;
0773 
0774     tegra_gpio_debuginit(tgi);
0775 
0776     return 0;
0777 }
0778 
0779 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
0780     .bank_stride = 0x80,
0781     .upper_offset = 0x800,
0782 };
0783 
0784 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
0785     .bank_stride = 0x100,
0786     .upper_offset = 0x80,
0787 };
0788 
0789 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
0790     .debounce_supported = true,
0791     .bank_stride = 0x100,
0792     .upper_offset = 0x80,
0793 };
0794 
0795 static const struct of_device_id tegra_gpio_of_match[] = {
0796     { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
0797     { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
0798     { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
0799     { },
0800 };
0801 MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
0802 
0803 static struct platform_driver tegra_gpio_driver = {
0804     .driver = {
0805         .name = "tegra-gpio",
0806         .pm = &tegra_gpio_pm_ops,
0807         .of_match_table = tegra_gpio_of_match,
0808     },
0809     .probe = tegra_gpio_probe,
0810 };
0811 module_platform_driver(tegra_gpio_driver);
0812 
0813 MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
0814 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
0815 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
0816 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
0817 MODULE_AUTHOR("Erik Gilling <konkers@google.com>");
0818 MODULE_LICENSE("GPL v2");
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