drivers/gpio/gpio-syscon.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  SYSCON GPIO driver
0004  *
0005  *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0006  */
0007
0008 #include <linux/err.h>
0009 #include <linux/gpio/driver.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <linux/mfd/syscon.h>
0016
0017 #define GPIO_SYSCON_FEAT_IN BIT(0)
0018 #define GPIO_SYSCON_FEAT_OUT    BIT(1)
0019 #define GPIO_SYSCON_FEAT_DIR    BIT(2)
0020
0021 /* SYSCON driver is designed to use 32-bit wide registers */
0022 #define SYSCON_REG_SIZE     (4)
0023 #define SYSCON_REG_BITS     (SYSCON_REG_SIZE * 8)
0024
0025 /**
0026  * struct syscon_gpio_data - Configuration for the device.
0027  * @compatible:     SYSCON driver compatible string.
0028  * @flags:      Set of GPIO_SYSCON_FEAT_ flags:
0029  *          GPIO_SYSCON_FEAT_IN:    GPIOs supports input,
0030  *          GPIO_SYSCON_FEAT_OUT:   GPIOs supports output,
0031  *          GPIO_SYSCON_FEAT_DIR:   GPIOs supports switch direction.
0032  * @bit_count:      Number of bits used as GPIOs.
0033  * @dat_bit_offset: Offset (in bits) to the first GPIO bit.
0034  * @dir_bit_offset: Optional offset (in bits) to the first bit to switch
0035  *          GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
0036  * @set:        HW specific callback to assigns output value
0037  *          for signal "offset"
0038  */
0039
0040 struct syscon_gpio_data {
0041     unsigned int    flags;
0042     unsigned int    bit_count;
0043     unsigned int    dat_bit_offset;
0044     unsigned int    dir_bit_offset;
0045     void        (*set)(struct gpio_chip *chip,
0046                    unsigned offset, int value);
0047 };
0048
0049 struct syscon_gpio_priv {
0050     struct gpio_chip        chip;
0051     struct regmap           *syscon;
0052     const struct syscon_gpio_data   *data;
0053     u32             dreg_offset;
0054     u32             dir_reg_offset;
0055 };
0056
0057 static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
0058 {
0059     struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
0060     unsigned int val, offs;
0061     int ret;
0062
0063     offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
0064
0065     ret = regmap_read(priv->syscon,
0066               (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
0067     if (ret)
0068         return ret;
0069
0070     return !!(val & BIT(offs % SYSCON_REG_BITS));
0071 }
0072
0073 static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
0074 {
0075     struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
0076     unsigned int offs;
0077
0078     offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
0079
0080     regmap_update_bits(priv->syscon,
0081                (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
0082                BIT(offs % SYSCON_REG_BITS),
0083                val ? BIT(offs % SYSCON_REG_BITS) : 0);
0084 }
0085
0086 static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
0087 {
0088     struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
0089
0090     if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
0091         unsigned int offs;
0092
0093         offs = priv->dir_reg_offset +
0094                priv->data->dir_bit_offset + offset;
0095
0096         regmap_update_bits(priv->syscon,
0097                    (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
0098                    BIT(offs % SYSCON_REG_BITS), 0);
0099     }
0100
0101     return 0;
0102 }
0103
0104 static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
0105 {
0106     struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
0107
0108     if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
0109         unsigned int offs;
0110
0111         offs = priv->dir_reg_offset +
0112                priv->data->dir_bit_offset + offset;
0113
0114         regmap_update_bits(priv->syscon,
0115                    (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
0116                    BIT(offs % SYSCON_REG_BITS),
0117                    BIT(offs % SYSCON_REG_BITS));
0118     }
0119
0120     chip->set(chip, offset, val);
0121
0122     return 0;
0123 }
0124
0125 static const struct syscon_gpio_data clps711x_mctrl_gpio = {
0126     /* ARM CLPS711X SYSFLG1 Bits 8-10 */
0127     .flags      = GPIO_SYSCON_FEAT_IN,
0128     .bit_count  = 3,
0129     .dat_bit_offset = 0x40 * 8 + 8,
0130 };
0131
0132 static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
0133                   int val)
0134 {
0135     struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
0136     unsigned int offs;
0137     u8 bit;
0138     u32 data;
0139     int ret;
0140
0141     offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
0142     bit = offs % SYSCON_REG_BITS;
0143     data = (val ? BIT(bit) : 0) | BIT(bit + 16);
0144     ret = regmap_write(priv->syscon,
0145                (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
0146                data);
0147     if (ret < 0)
0148         dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
0149 }
0150
0151 static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
0152     /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
0153     .flags      = GPIO_SYSCON_FEAT_OUT,
0154     .bit_count  = 1,
0155     .dat_bit_offset = 0x0428 * 8 + 1,
0156     .set        = rockchip_gpio_set,
0157 };
0158
0159 #define KEYSTONE_LOCK_BIT BIT(0)
0160
0161 static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
0162 {
0163     struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
0164     unsigned int offs;
0165     int ret;
0166
0167     offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
0168
0169     if (!val)
0170         return;
0171
0172     ret = regmap_update_bits(
0173             priv->syscon,
0174             (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
0175             BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
0176             BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
0177     if (ret < 0)
0178         dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
0179 }
0180
0181 static const struct syscon_gpio_data keystone_dsp_gpio = {
0182     /* ARM Keystone 2 */
0183     .flags      = GPIO_SYSCON_FEAT_OUT,
0184     .bit_count  = 28,
0185     .dat_bit_offset = 4,
0186     .set        = keystone_gpio_set,
0187 };
0188
0189 static const struct of_device_id syscon_gpio_ids[] = {
0190     {
0191         .compatible = "cirrus,ep7209-mctrl-gpio",
0192         .data       = &clps711x_mctrl_gpio,
0193     },
0194     {
0195         .compatible = "ti,keystone-dsp-gpio",
0196         .data       = &keystone_dsp_gpio,
0197     },
0198     {
0199         .compatible = "rockchip,rk3328-grf-gpio",
0200         .data       = &rockchip_rk3328_gpio_mute,
0201     },
0202     { }
0203 };
0204 MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
0205
0206 static int syscon_gpio_probe(struct platform_device *pdev)
0207 {
0208     struct device *dev = &pdev->dev;
0209     struct syscon_gpio_priv *priv;
0210     struct device_node *np = dev->of_node;
0211     int ret;
0212
0213     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0214     if (!priv)
0215         return -ENOMEM;
0216
0217     priv->data = of_device_get_match_data(dev);
0218
0219     priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
0220     if (IS_ERR(priv->syscon) && np->parent)
0221         priv->syscon = syscon_node_to_regmap(np->parent);
0222     if (IS_ERR(priv->syscon))
0223         return PTR_ERR(priv->syscon);
0224
0225     ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
0226                      &priv->dreg_offset);
0227     if (ret)
0228         dev_err(dev, "can't read the data register offset!\n");
0229
0230     priv->dreg_offset <<= 3;
0231
0232     ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
0233                      &priv->dir_reg_offset);
0234     if (ret)
0235         dev_dbg(dev, "can't read the dir register offset!\n");
0236
0237     priv->dir_reg_offset <<= 3;
0238
0239     priv->chip.parent = dev;
0240     priv->chip.owner = THIS_MODULE;
0241     priv->chip.label = dev_name(dev);
0242     priv->chip.base = -1;
0243     priv->chip.ngpio = priv->data->bit_count;
0244     priv->chip.get = syscon_gpio_get;
0245     if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
0246         priv->chip.direction_input = syscon_gpio_dir_in;
0247     if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
0248         priv->chip.set = priv->data->set ? : syscon_gpio_set;
0249         priv->chip.direction_output = syscon_gpio_dir_out;
0250     }
0251
0252     platform_set_drvdata(pdev, priv);
0253
0254     return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
0255 }
0256
0257 static struct platform_driver syscon_gpio_driver = {
0258     .driver = {
0259         .name       = "gpio-syscon",
0260         .of_match_table = syscon_gpio_ids,
0261     },
0262     .probe  = syscon_gpio_probe,
0263 };
0264 module_platform_driver(syscon_gpio_driver);
0265
0266 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
0267 MODULE_DESCRIPTION("SYSCON GPIO driver");
0268 MODULE_LICENSE("GPL");