drivers/gpio/gpio-stp-xway.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
0005  */
0006
0007 #include <linux/slab.h>
0008 #include <linux/init.h>
0009 #include <linux/module.h>
0010 #include <linux/types.h>
0011 #include <linux/of_platform.h>
0012 #include <linux/mutex.h>
0013 #include <linux/gpio/driver.h>
0014 #include <linux/io.h>
0015 #include <linux/clk.h>
0016 #include <linux/err.h>
0017
0018 /*
0019  * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
0020  * peripheral controller used to drive external shift register cascades. At most
0021  * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
0022  * to drive the 2 LSBs of the cascade automatically.
0023  */
0024
0025 /* control register 0 */
0026 #define XWAY_STP_CON0       0x00
0027 /* control register 1 */
0028 #define XWAY_STP_CON1       0x04
0029 /* data register 0 */
0030 #define XWAY_STP_CPU0       0x08
0031 /* data register 1 */
0032 #define XWAY_STP_CPU1       0x0C
0033 /* access register */
0034 #define XWAY_STP_AR     0x10
0035
0036 /* software or hardware update select bit */
0037 #define XWAY_STP_CON_SWU    BIT(31)
0038
0039 /* automatic update rates */
0040 #define XWAY_STP_2HZ        0
0041 #define XWAY_STP_4HZ        BIT(23)
0042 #define XWAY_STP_8HZ        BIT(24)
0043 #define XWAY_STP_10HZ       (BIT(24) | BIT(23))
0044 #define XWAY_STP_SPEED_MASK (BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
0045
0046 #define XWAY_STP_FPIS_VALUE BIT(21)
0047 #define XWAY_STP_FPIS_MASK  (BIT(20) | BIT(21))
0048
0049 /* clock source for automatic update */
0050 #define XWAY_STP_UPD_FPI    BIT(31)
0051 #define XWAY_STP_UPD_MASK   (BIT(31) | BIT(30))
0052
0053 /* let the adsl core drive the 2 LSBs */
0054 #define XWAY_STP_ADSL_SHIFT 24
0055 #define XWAY_STP_ADSL_MASK  0x3
0056
0057 /* 2 groups of 3 bits can be driven by the phys */
0058 #define XWAY_STP_PHY_MASK   0x7
0059 #define XWAY_STP_PHY1_SHIFT 27
0060 #define XWAY_STP_PHY2_SHIFT 3
0061 #define XWAY_STP_PHY3_SHIFT 6
0062 #define XWAY_STP_PHY4_SHIFT 15
0063
0064 /* STP has 3 groups of 8 bits */
0065 #define XWAY_STP_GROUP0     BIT(0)
0066 #define XWAY_STP_GROUP1     BIT(1)
0067 #define XWAY_STP_GROUP2     BIT(2)
0068 #define XWAY_STP_GROUP_MASK (0x7)
0069
0070 /* Edge configuration bits */
0071 #define XWAY_STP_FALLING    BIT(26)
0072 #define XWAY_STP_EDGE_MASK  BIT(26)
0073
0074 #define xway_stp_r32(m, reg)        __raw_readl(m + reg)
0075 #define xway_stp_w32(m, val, reg)   __raw_writel(val, m + reg)
0076 #define xway_stp_w32_mask(m, clear, set, reg) \
0077         xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
0078
0079 struct xway_stp {
0080     struct gpio_chip gc;
0081     void __iomem *virt;
0082     u32 edge;   /* rising or falling edge triggered shift register */
0083     u32 shadow; /* shadow the shift registers state */
0084     u8 groups;  /* we can drive 1-3 groups of 8bit each */
0085     u8 dsl;     /* the 2 LSBs can be driven by the dsl core */
0086     u8 phy1;    /* 3 bits can be driven by phy1 */
0087     u8 phy2;    /* 3 bits can be driven by phy2 */
0088     u8 phy3;    /* 3 bits can be driven by phy3 */
0089     u8 phy4;    /* 3 bits can be driven by phy4 */
0090     u8 reserved;    /* mask out the hw driven bits in gpio_request */
0091 };
0092
0093 /**
0094  * xway_stp_get() - gpio_chip->get - get gpios.
0095  * @gc:     Pointer to gpio_chip device structure.
0096  * @gpio:   GPIO signal number.
0097  *
0098  * Gets the shadow value.
0099  */
0100 static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
0101 {
0102     struct xway_stp *chip = gpiochip_get_data(gc);
0103
0104     return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
0105 }
0106
0107 /**
0108  * xway_stp_set() - gpio_chip->set - set gpios.
0109  * @gc:     Pointer to gpio_chip device structure.
0110  * @gpio:   GPIO signal number.
0111  * @val:    Value to be written to specified signal.
0112  *
0113  * Set the shadow value and call ltq_ebu_apply.
0114  */
0115 static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
0116 {
0117     struct xway_stp *chip = gpiochip_get_data(gc);
0118
0119     if (val)
0120         chip->shadow |= BIT(gpio);
0121     else
0122         chip->shadow &= ~BIT(gpio);
0123     xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
0124     if (!chip->reserved)
0125         xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
0126 }
0127
0128 /**
0129  * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
0130  * @gc:     Pointer to gpio_chip device structure.
0131  * @gpio:   GPIO signal number.
0132  * @val:    Value to be written to specified signal.
0133  *
0134  * Same as xway_stp_set, always returns 0.
0135  */
0136 static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
0137 {
0138     xway_stp_set(gc, gpio, val);
0139
0140     return 0;
0141 }
0142
0143 /**
0144  * xway_stp_request() - gpio_chip->request
0145  * @gc:     Pointer to gpio_chip device structure.
0146  * @gpio:   GPIO signal number.
0147  *
0148  * We mask out the HW driven pins
0149  */
0150 static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
0151 {
0152     struct xway_stp *chip = gpiochip_get_data(gc);
0153
0154     if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
0155         dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
0156         return -ENODEV;
0157     }
0158
0159     return 0;
0160 }
0161
0162 /**
0163  * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
0164  * @chip: Pointer to the xway_stp chip structure
0165  */
0166 static void xway_stp_hw_init(struct xway_stp *chip)
0167 {
0168     /* sane defaults */
0169     xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
0170     xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
0171     xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
0172     xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
0173     xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
0174
0175     /* apply edge trigger settings for the shift register */
0176     xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
0177                 chip->edge, XWAY_STP_CON0);
0178
0179     /* apply led group settings */
0180     xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
0181                 chip->groups, XWAY_STP_CON1);
0182
0183     /* tell the hardware which pins are controlled by the dsl modem */
0184     xway_stp_w32_mask(chip->virt,
0185             XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
0186             chip->dsl << XWAY_STP_ADSL_SHIFT,
0187             XWAY_STP_CON0);
0188
0189     /* tell the hardware which pins are controlled by the phys */
0190     xway_stp_w32_mask(chip->virt,
0191             XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
0192             chip->phy1 << XWAY_STP_PHY1_SHIFT,
0193             XWAY_STP_CON0);
0194     xway_stp_w32_mask(chip->virt,
0195             XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
0196             chip->phy2 << XWAY_STP_PHY2_SHIFT,
0197             XWAY_STP_CON1);
0198
0199     if (of_machine_is_compatible("lantiq,grx390")
0200         || of_machine_is_compatible("lantiq,ar10")) {
0201         xway_stp_w32_mask(chip->virt,
0202                 XWAY_STP_PHY_MASK << XWAY_STP_PHY3_SHIFT,
0203                 chip->phy3 << XWAY_STP_PHY3_SHIFT,
0204                 XWAY_STP_CON1);
0205     }
0206
0207     if (of_machine_is_compatible("lantiq,grx390")) {
0208         xway_stp_w32_mask(chip->virt,
0209                 XWAY_STP_PHY_MASK << XWAY_STP_PHY4_SHIFT,
0210                 chip->phy4 << XWAY_STP_PHY4_SHIFT,
0211                 XWAY_STP_CON1);
0212     }
0213
0214     /* mask out the hw driven bits in gpio_request */
0215     chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5)
0216         | (chip->phy1 << 2) | chip->dsl;
0217
0218     /*
0219      * if we have pins that are driven by hw, we need to tell the stp what
0220      * clock to use as a timer.
0221      */
0222     if (chip->reserved) {
0223         xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
0224             XWAY_STP_UPD_FPI, XWAY_STP_CON1);
0225         xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK,
0226             XWAY_STP_10HZ, XWAY_STP_CON1);
0227         xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK,
0228             XWAY_STP_FPIS_VALUE, XWAY_STP_CON1);
0229     }
0230 }
0231
0232 static int xway_stp_probe(struct platform_device *pdev)
0233 {
0234     u32 shadow, groups, dsl, phy;
0235     struct xway_stp *chip;
0236     struct clk *clk;
0237     int ret = 0;
0238
0239     chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
0240     if (!chip)
0241         return -ENOMEM;
0242
0243     chip->virt = devm_platform_ioremap_resource(pdev, 0);
0244     if (IS_ERR(chip->virt))
0245         return PTR_ERR(chip->virt);
0246
0247     chip->gc.parent = &pdev->dev;
0248     chip->gc.label = "stp-xway";
0249     chip->gc.direction_output = xway_stp_dir_out;
0250     chip->gc.get = xway_stp_get;
0251     chip->gc.set = xway_stp_set;
0252     chip->gc.request = xway_stp_request;
0253     chip->gc.base = -1;
0254     chip->gc.owner = THIS_MODULE;
0255
0256     /* store the shadow value if one was passed by the devicetree */
0257     if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
0258         chip->shadow = shadow;
0259
0260     /* find out which gpio groups should be enabled */
0261     if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
0262         chip->groups = groups & XWAY_STP_GROUP_MASK;
0263     else
0264         chip->groups = XWAY_STP_GROUP0;
0265     chip->gc.ngpio = fls(chip->groups) * 8;
0266
0267     /* find out which gpios are controlled by the dsl core */
0268     if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
0269         chip->dsl = dsl & XWAY_STP_ADSL_MASK;
0270
0271     /* find out which gpios are controlled by the phys */
0272     if (of_machine_is_compatible("lantiq,ar9") ||
0273             of_machine_is_compatible("lantiq,gr9") ||
0274             of_machine_is_compatible("lantiq,vr9") ||
0275             of_machine_is_compatible("lantiq,ar10") ||
0276             of_machine_is_compatible("lantiq,grx390")) {
0277         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
0278             chip->phy1 = phy & XWAY_STP_PHY_MASK;
0279         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
0280             chip->phy2 = phy & XWAY_STP_PHY_MASK;
0281     }
0282
0283     if (of_machine_is_compatible("lantiq,ar10") ||
0284             of_machine_is_compatible("lantiq,grx390")) {
0285         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy))
0286             chip->phy3 = phy & XWAY_STP_PHY_MASK;
0287     }
0288
0289     if (of_machine_is_compatible("lantiq,grx390")) {
0290         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy))
0291             chip->phy4 = phy & XWAY_STP_PHY_MASK;
0292     }
0293
0294     /* check which edge trigger we should use, default to a falling edge */
0295     if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
0296         chip->edge = XWAY_STP_FALLING;
0297
0298     clk = devm_clk_get(&pdev->dev, NULL);
0299     if (IS_ERR(clk)) {
0300         dev_err(&pdev->dev, "Failed to get clock\n");
0301         return PTR_ERR(clk);
0302     }
0303
0304     ret = clk_prepare_enable(clk);
0305     if (ret)
0306         return ret;
0307
0308     xway_stp_hw_init(chip);
0309
0310     ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
0311     if (ret) {
0312         clk_disable_unprepare(clk);
0313         return ret;
0314     }
0315
0316     dev_info(&pdev->dev, "Init done\n");
0317
0318     return 0;
0319 }
0320
0321 static const struct of_device_id xway_stp_match[] = {
0322     { .compatible = "lantiq,gpio-stp-xway" },
0323     {},
0324 };
0325 MODULE_DEVICE_TABLE(of, xway_stp_match);
0326
0327 static struct platform_driver xway_stp_driver = {
0328     .probe = xway_stp_probe,
0329     .driver = {
0330         .name = "gpio-stp-xway",
0331         .of_match_table = xway_stp_match,
0332     },
0333 };
0334
0335 static int __init xway_stp_init(void)
0336 {
0337     return platform_driver_register(&xway_stp_driver);
0338 }
0339
0340 subsys_initcall(xway_stp_init);