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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) ST-Ericsson SA 2010
0004  *
0005  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
0006  */
0007 
0008 #include <linux/init.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/slab.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/of.h>
0014 #include <linux/mfd/stmpe.h>
0015 #include <linux/seq_file.h>
0016 #include <linux/bitops.h>
0017 
0018 /*
0019  * These registers are modified under the irq bus lock and cached to avoid
0020  * unnecessary writes in bus_sync_unlock.
0021  */
0022 enum { REG_RE, REG_FE, REG_IE };
0023 
0024 enum { LSB, CSB, MSB };
0025 
0026 #define CACHE_NR_REGS   3
0027 /* No variant has more than 24 GPIOs */
0028 #define CACHE_NR_BANKS  (24 / 8)
0029 
0030 struct stmpe_gpio {
0031     struct gpio_chip chip;
0032     struct stmpe *stmpe;
0033     struct device *dev;
0034     struct mutex irq_lock;
0035     u32 norequest_mask;
0036     /* Caches of interrupt control registers for bus_lock */
0037     u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
0038     u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
0039 };
0040 
0041 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
0042 {
0043     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
0044     struct stmpe *stmpe = stmpe_gpio->stmpe;
0045     u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
0046     u8 mask = BIT(offset % 8);
0047     int ret;
0048 
0049     ret = stmpe_reg_read(stmpe, reg);
0050     if (ret < 0)
0051         return ret;
0052 
0053     return !!(ret & mask);
0054 }
0055 
0056 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
0057 {
0058     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
0059     struct stmpe *stmpe = stmpe_gpio->stmpe;
0060     int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
0061     u8 reg = stmpe->regs[which + (offset / 8)];
0062     u8 mask = BIT(offset % 8);
0063 
0064     /*
0065      * Some variants have single register for gpio set/clear functionality.
0066      * For them we need to write 0 to clear and 1 to set.
0067      */
0068     if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
0069         stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
0070     else
0071         stmpe_reg_write(stmpe, reg, mask);
0072 }
0073 
0074 static int stmpe_gpio_get_direction(struct gpio_chip *chip,
0075                     unsigned offset)
0076 {
0077     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
0078     struct stmpe *stmpe = stmpe_gpio->stmpe;
0079     u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
0080     u8 mask = BIT(offset % 8);
0081     int ret;
0082 
0083     ret = stmpe_reg_read(stmpe, reg);
0084     if (ret < 0)
0085         return ret;
0086 
0087     if (ret & mask)
0088         return GPIO_LINE_DIRECTION_OUT;
0089 
0090     return GPIO_LINE_DIRECTION_IN;
0091 }
0092 
0093 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
0094                      unsigned offset, int val)
0095 {
0096     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
0097     struct stmpe *stmpe = stmpe_gpio->stmpe;
0098     u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
0099     u8 mask = BIT(offset % 8);
0100 
0101     stmpe_gpio_set(chip, offset, val);
0102 
0103     return stmpe_set_bits(stmpe, reg, mask, mask);
0104 }
0105 
0106 static int stmpe_gpio_direction_input(struct gpio_chip *chip,
0107                     unsigned offset)
0108 {
0109     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
0110     struct stmpe *stmpe = stmpe_gpio->stmpe;
0111     u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
0112     u8 mask = BIT(offset % 8);
0113 
0114     return stmpe_set_bits(stmpe, reg, mask, 0);
0115 }
0116 
0117 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
0118 {
0119     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
0120     struct stmpe *stmpe = stmpe_gpio->stmpe;
0121 
0122     if (stmpe_gpio->norequest_mask & BIT(offset))
0123         return -EINVAL;
0124 
0125     return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
0126 }
0127 
0128 static const struct gpio_chip template_chip = {
0129     .label          = "stmpe",
0130     .owner          = THIS_MODULE,
0131     .get_direction      = stmpe_gpio_get_direction,
0132     .direction_input    = stmpe_gpio_direction_input,
0133     .get            = stmpe_gpio_get,
0134     .direction_output   = stmpe_gpio_direction_output,
0135     .set            = stmpe_gpio_set,
0136     .request        = stmpe_gpio_request,
0137     .can_sleep      = true,
0138 };
0139 
0140 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0141 {
0142     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0143     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0144     int offset = d->hwirq;
0145     int regoffset = offset / 8;
0146     int mask = BIT(offset % 8);
0147 
0148     if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
0149         return -EINVAL;
0150 
0151     /* STMPE801 and STMPE 1600 don't have RE and FE registers */
0152     if (stmpe_gpio->stmpe->partnum == STMPE801 ||
0153         stmpe_gpio->stmpe->partnum == STMPE1600)
0154         return 0;
0155 
0156     if (type & IRQ_TYPE_EDGE_RISING)
0157         stmpe_gpio->regs[REG_RE][regoffset] |= mask;
0158     else
0159         stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
0160 
0161     if (type & IRQ_TYPE_EDGE_FALLING)
0162         stmpe_gpio->regs[REG_FE][regoffset] |= mask;
0163     else
0164         stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
0165 
0166     return 0;
0167 }
0168 
0169 static void stmpe_gpio_irq_lock(struct irq_data *d)
0170 {
0171     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0172     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0173 
0174     mutex_lock(&stmpe_gpio->irq_lock);
0175 }
0176 
0177 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
0178 {
0179     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0180     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0181     struct stmpe *stmpe = stmpe_gpio->stmpe;
0182     int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
0183     static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
0184         [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
0185         [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
0186         [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
0187         [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
0188         [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
0189         [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
0190         [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
0191         [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
0192         [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
0193     };
0194     int i, j;
0195 
0196     /*
0197      * STMPE1600: to be able to get IRQ from pins,
0198      * a read must be done on GPMR register, or a write in
0199      * GPSR or GPCR registers
0200      */
0201     if (stmpe->partnum == STMPE1600) {
0202         stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
0203         stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
0204     }
0205 
0206     for (i = 0; i < CACHE_NR_REGS; i++) {
0207         /* STMPE801 and STMPE1600 don't have RE and FE registers */
0208         if ((stmpe->partnum == STMPE801 ||
0209              stmpe->partnum == STMPE1600) &&
0210              (i != REG_IE))
0211             continue;
0212 
0213         for (j = 0; j < num_banks; j++) {
0214             u8 old = stmpe_gpio->oldregs[i][j];
0215             u8 new = stmpe_gpio->regs[i][j];
0216 
0217             if (new == old)
0218                 continue;
0219 
0220             stmpe_gpio->oldregs[i][j] = new;
0221             stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
0222         }
0223     }
0224 
0225     mutex_unlock(&stmpe_gpio->irq_lock);
0226 }
0227 
0228 static void stmpe_gpio_irq_mask(struct irq_data *d)
0229 {
0230     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0231     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0232     int offset = d->hwirq;
0233     int regoffset = offset / 8;
0234     int mask = BIT(offset % 8);
0235 
0236     stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
0237 }
0238 
0239 static void stmpe_gpio_irq_unmask(struct irq_data *d)
0240 {
0241     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0242     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0243     int offset = d->hwirq;
0244     int regoffset = offset / 8;
0245     int mask = BIT(offset % 8);
0246 
0247     stmpe_gpio->regs[REG_IE][regoffset] |= mask;
0248 }
0249 
0250 static void stmpe_dbg_show_one(struct seq_file *s,
0251                    struct gpio_chip *gc,
0252                    unsigned offset, unsigned gpio)
0253 {
0254     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0255     struct stmpe *stmpe = stmpe_gpio->stmpe;
0256     const char *label = gpiochip_is_requested(gc, offset);
0257     bool val = !!stmpe_gpio_get(gc, offset);
0258     u8 bank = offset / 8;
0259     u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
0260     u8 mask = BIT(offset % 8);
0261     int ret;
0262     u8 dir;
0263 
0264     ret = stmpe_reg_read(stmpe, dir_reg);
0265     if (ret < 0)
0266         return;
0267     dir = !!(ret & mask);
0268 
0269     if (dir) {
0270         seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
0271                gpio, label ?: "(none)",
0272                val ? "hi" : "lo");
0273     } else {
0274         u8 edge_det_reg;
0275         u8 rise_reg;
0276         u8 fall_reg;
0277         u8 irqen_reg;
0278 
0279         static const char * const edge_det_values[] = {
0280             "edge-inactive",
0281             "edge-asserted",
0282             "not-supported"
0283         };
0284         static const char * const rise_values[] = {
0285             "no-rising-edge-detection",
0286             "rising-edge-detection",
0287             "not-supported"
0288         };
0289         static const char * const fall_values[] = {
0290             "no-falling-edge-detection",
0291             "falling-edge-detection",
0292             "not-supported"
0293         };
0294         #define NOT_SUPPORTED_IDX 2
0295         u8 edge_det = NOT_SUPPORTED_IDX;
0296         u8 rise = NOT_SUPPORTED_IDX;
0297         u8 fall = NOT_SUPPORTED_IDX;
0298         bool irqen;
0299 
0300         switch (stmpe->partnum) {
0301         case STMPE610:
0302         case STMPE811:
0303         case STMPE1601:
0304         case STMPE2401:
0305         case STMPE2403:
0306             edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
0307             ret = stmpe_reg_read(stmpe, edge_det_reg);
0308             if (ret < 0)
0309                 return;
0310             edge_det = !!(ret & mask);
0311             fallthrough;
0312         case STMPE1801:
0313             rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
0314             fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
0315 
0316             ret = stmpe_reg_read(stmpe, rise_reg);
0317             if (ret < 0)
0318                 return;
0319             rise = !!(ret & mask);
0320             ret = stmpe_reg_read(stmpe, fall_reg);
0321             if (ret < 0)
0322                 return;
0323             fall = !!(ret & mask);
0324             fallthrough;
0325         case STMPE801:
0326         case STMPE1600:
0327             irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
0328             break;
0329 
0330         default:
0331             return;
0332         }
0333 
0334         ret = stmpe_reg_read(stmpe, irqen_reg);
0335         if (ret < 0)
0336             return;
0337         irqen = !!(ret & mask);
0338 
0339         seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
0340                gpio, label ?: "(none)",
0341                val ? "hi" : "lo",
0342                edge_det_values[edge_det],
0343                irqen ? "IRQ-enabled" : "IRQ-disabled",
0344                rise_values[rise],
0345                fall_values[fall]);
0346     }
0347 }
0348 
0349 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
0350 {
0351     unsigned i;
0352     unsigned gpio = gc->base;
0353 
0354     for (i = 0; i < gc->ngpio; i++, gpio++) {
0355         stmpe_dbg_show_one(s, gc, i, gpio);
0356         seq_putc(s, '\n');
0357     }
0358 }
0359 
0360 static struct irq_chip stmpe_gpio_irq_chip = {
0361     .name           = "stmpe-gpio",
0362     .irq_bus_lock       = stmpe_gpio_irq_lock,
0363     .irq_bus_sync_unlock    = stmpe_gpio_irq_sync_unlock,
0364     .irq_mask       = stmpe_gpio_irq_mask,
0365     .irq_unmask     = stmpe_gpio_irq_unmask,
0366     .irq_set_type       = stmpe_gpio_irq_set_type,
0367 };
0368 
0369 #define MAX_GPIOS 24
0370 
0371 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
0372 {
0373     struct stmpe_gpio *stmpe_gpio = dev;
0374     struct stmpe *stmpe = stmpe_gpio->stmpe;
0375     u8 statmsbreg;
0376     int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
0377     u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
0378     int ret;
0379     int i;
0380 
0381     /*
0382      * the stmpe_block_read() call below, imposes to set statmsbreg
0383      * with the register located at the lowest address. As STMPE1600
0384      * variant is the only one which respect registers address's order
0385      * (LSB regs located at lowest address than MSB ones) whereas all
0386      * the others have a registers layout with MSB located before the
0387      * LSB regs.
0388      */
0389     if (stmpe->partnum == STMPE1600)
0390         statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
0391     else
0392         statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
0393 
0394     ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
0395     if (ret < 0)
0396         return IRQ_NONE;
0397 
0398     for (i = 0; i < num_banks; i++) {
0399         int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
0400                num_banks - i - 1;
0401         unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
0402         unsigned int stat = status[i];
0403 
0404         stat &= enabled;
0405         if (!stat)
0406             continue;
0407 
0408         while (stat) {
0409             int bit = __ffs(stat);
0410             int line = bank * 8 + bit;
0411             int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
0412                              line);
0413 
0414             handle_nested_irq(child_irq);
0415             stat &= ~BIT(bit);
0416         }
0417 
0418         /*
0419          * interrupt status register write has no effect on
0420          * 801/1801/1600, bits are cleared when read.
0421          * Edge detect register is not present on 801/1600/1801
0422          */
0423         if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
0424             stmpe->partnum != STMPE1801) {
0425             stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
0426             stmpe_reg_write(stmpe,
0427                     stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
0428                     status[i]);
0429         }
0430     }
0431 
0432     return IRQ_HANDLED;
0433 }
0434 
0435 static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
0436                       unsigned long *valid_mask,
0437                       unsigned int ngpios)
0438 {
0439     struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
0440     int i;
0441 
0442     if (!stmpe_gpio->norequest_mask)
0443         return;
0444 
0445     /* Forbid unused lines to be mapped as IRQs */
0446     for (i = 0; i < sizeof(u32); i++) {
0447         if (stmpe_gpio->norequest_mask & BIT(i))
0448             clear_bit(i, valid_mask);
0449     }
0450 }
0451 
0452 static void stmpe_gpio_disable(void *stmpe)
0453 {
0454     stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
0455 }
0456 
0457 static int stmpe_gpio_probe(struct platform_device *pdev)
0458 {
0459     struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
0460     struct device_node *np = pdev->dev.of_node;
0461     struct stmpe_gpio *stmpe_gpio;
0462     int ret, irq;
0463 
0464     if (stmpe->num_gpios > MAX_GPIOS) {
0465         dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
0466         return -EINVAL;
0467     }
0468 
0469     stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
0470     if (!stmpe_gpio)
0471         return -ENOMEM;
0472 
0473     mutex_init(&stmpe_gpio->irq_lock);
0474 
0475     stmpe_gpio->dev = &pdev->dev;
0476     stmpe_gpio->stmpe = stmpe;
0477     stmpe_gpio->chip = template_chip;
0478     stmpe_gpio->chip.ngpio = stmpe->num_gpios;
0479     stmpe_gpio->chip.parent = &pdev->dev;
0480     stmpe_gpio->chip.base = -1;
0481 
0482     if (IS_ENABLED(CONFIG_DEBUG_FS))
0483                 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
0484 
0485     of_property_read_u32(np, "st,norequest-mask",
0486             &stmpe_gpio->norequest_mask);
0487 
0488     irq = platform_get_irq(pdev, 0);
0489     if (irq < 0)
0490         dev_info(&pdev->dev,
0491             "device configured in no-irq mode: "
0492             "irqs are not available\n");
0493 
0494     ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
0495     if (ret)
0496         return ret;
0497 
0498     ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
0499     if (ret)
0500         return ret;
0501 
0502     if (irq > 0) {
0503         struct gpio_irq_chip *girq;
0504 
0505         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0506                 stmpe_gpio_irq, IRQF_ONESHOT,
0507                 "stmpe-gpio", stmpe_gpio);
0508         if (ret) {
0509             dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
0510             return ret;
0511         }
0512 
0513         girq = &stmpe_gpio->chip.irq;
0514         girq->chip = &stmpe_gpio_irq_chip;
0515         /* This will let us handle the parent IRQ in the driver */
0516         girq->parent_handler = NULL;
0517         girq->num_parents = 0;
0518         girq->parents = NULL;
0519         girq->default_type = IRQ_TYPE_NONE;
0520         girq->handler = handle_simple_irq;
0521         girq->threaded = true;
0522         girq->init_valid_mask = stmpe_init_irq_valid_mask;
0523     }
0524 
0525     return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
0526 }
0527 
0528 static struct platform_driver stmpe_gpio_driver = {
0529     .driver = {
0530         .suppress_bind_attrs    = true,
0531         .name           = "stmpe-gpio",
0532     },
0533     .probe      = stmpe_gpio_probe,
0534 };
0535 
0536 static int __init stmpe_gpio_init(void)
0537 {
0538     return platform_driver_register(&stmpe_gpio_driver);
0539 }
0540 subsys_initcall(stmpe_gpio_init);
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