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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * STMicroelectronics ConneXt (STA2X11) GPIO driver
0004  *
0005  * Copyright 2012 ST Microelectronics (Alessandro Rubini)
0006  * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
0007  * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
0008  */
0009 
0010 #include <linux/init.h>
0011 #include <linux/kernel.h>
0012 #include <linux/slab.h>
0013 #include <linux/gpio/driver.h>
0014 #include <linux/bitops.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irq.h>
0017 #include <linux/pci.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/mfd/sta2x11-mfd.h>
0020 
0021 struct gsta_regs {
0022     u32 dat;        /* 0x00 */
0023     u32 dats;
0024     u32 datc;
0025     u32 pdis;
0026     u32 dir;        /* 0x10 */
0027     u32 dirs;
0028     u32 dirc;
0029     u32 unused_1c;
0030     u32 afsela;     /* 0x20 */
0031     u32 unused_24[7];
0032     u32 rimsc;      /* 0x40 */
0033     u32 fimsc;
0034     u32 is;
0035     u32 ic;
0036 };
0037 
0038 struct gsta_gpio {
0039     spinlock_t          lock;
0040     struct device           *dev;
0041     void __iomem            *reg_base;
0042     struct gsta_regs __iomem    *regs[GSTA_NR_BLOCKS];
0043     struct gpio_chip        gpio;
0044     int             irq_base;
0045     /* FIXME: save the whole config here (AF, ...) */
0046     unsigned            irq_type[GSTA_NR_GPIO];
0047 };
0048 
0049 /*
0050  * gpio methods
0051  */
0052 
0053 static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
0054 {
0055     struct gsta_gpio *chip = gpiochip_get_data(gpio);
0056     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0057     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0058 
0059     if (val)
0060         writel(bit, &regs->dats);
0061     else
0062         writel(bit, &regs->datc);
0063 }
0064 
0065 static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
0066 {
0067     struct gsta_gpio *chip = gpiochip_get_data(gpio);
0068     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0069     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0070 
0071     return !!(readl(&regs->dat) & bit);
0072 }
0073 
0074 static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
0075                       int val)
0076 {
0077     struct gsta_gpio *chip = gpiochip_get_data(gpio);
0078     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0079     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0080 
0081     writel(bit, &regs->dirs);
0082     /* Data register after direction, otherwise pullup/down is selected */
0083     if (val)
0084         writel(bit, &regs->dats);
0085     else
0086         writel(bit, &regs->datc);
0087     return 0;
0088 }
0089 
0090 static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
0091 {
0092     struct gsta_gpio *chip = gpiochip_get_data(gpio);
0093     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0094     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0095 
0096     writel(bit, &regs->dirc);
0097     return 0;
0098 }
0099 
0100 static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
0101 {
0102     struct gsta_gpio *chip = gpiochip_get_data(gpio);
0103     return chip->irq_base + offset;
0104 }
0105 
0106 static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
0107 {
0108     struct gpio_chip *gpio = &chip->gpio;
0109 
0110     /*
0111      * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
0112      * from the end. However, for compatibility, we need the first
0113      * ConneXt device to start from gpio 0: it's the main chipset
0114      * on most boards so documents and drivers assume gpio0..gpio127
0115      */
0116     static int gpio_base;
0117 
0118     gpio->label = dev_name(chip->dev);
0119     gpio->owner = THIS_MODULE;
0120     gpio->direction_input = gsta_gpio_direction_input;
0121     gpio->get = gsta_gpio_get;
0122     gpio->direction_output = gsta_gpio_direction_output;
0123     gpio->set = gsta_gpio_set;
0124     gpio->dbg_show = NULL;
0125     gpio->base = gpio_base;
0126     gpio->ngpio = GSTA_NR_GPIO;
0127     gpio->can_sleep = false;
0128     gpio->to_irq = gsta_gpio_to_irq;
0129 
0130     /*
0131      * After the first device, turn to dynamic gpio numbers.
0132      * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
0133      */
0134     if (!gpio_base)
0135         gpio_base = -1;
0136 }
0137 
0138 /*
0139  * Special method: alternate functions and pullup/pulldown. This is only
0140  * invoked on startup to configure gpio's according to platform data.
0141  * FIXME : this functionality shall be managed (and exported to other drivers)
0142  * via the pin control subsystem.
0143  */
0144 static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
0145 {
0146     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0147     unsigned long flags;
0148     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0149     u32 val;
0150     int err = 0;
0151 
0152     pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
0153 
0154     if (cfg == PINMUX_TYPE_NONE)
0155         return;
0156 
0157     /* Alternate function or not? */
0158     spin_lock_irqsave(&chip->lock, flags);
0159     val = readl(&regs->afsela);
0160     if (cfg == PINMUX_TYPE_FUNCTION)
0161         val |= bit;
0162     else
0163         val &= ~bit;
0164     writel(val | bit, &regs->afsela);
0165     if (cfg == PINMUX_TYPE_FUNCTION) {
0166         spin_unlock_irqrestore(&chip->lock, flags);
0167         return;
0168     }
0169 
0170     /* not alternate function: set details */
0171     switch (cfg) {
0172     case PINMUX_TYPE_OUTPUT_LOW:
0173         writel(bit, &regs->dirs);
0174         writel(bit, &regs->datc);
0175         break;
0176     case PINMUX_TYPE_OUTPUT_HIGH:
0177         writel(bit, &regs->dirs);
0178         writel(bit, &regs->dats);
0179         break;
0180     case PINMUX_TYPE_INPUT:
0181         writel(bit, &regs->dirc);
0182         val = readl(&regs->pdis) | bit;
0183         writel(val, &regs->pdis);
0184         break;
0185     case PINMUX_TYPE_INPUT_PULLUP:
0186         writel(bit, &regs->dirc);
0187         val = readl(&regs->pdis) & ~bit;
0188         writel(val, &regs->pdis);
0189         writel(bit, &regs->dats);
0190         break;
0191     case PINMUX_TYPE_INPUT_PULLDOWN:
0192         writel(bit, &regs->dirc);
0193         val = readl(&regs->pdis) & ~bit;
0194         writel(val, &regs->pdis);
0195         writel(bit, &regs->datc);
0196         break;
0197     default:
0198         err = 1;
0199     }
0200     spin_unlock_irqrestore(&chip->lock, flags);
0201     if (err)
0202         pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
0203                __func__, chip, nr, cfg);
0204 }
0205 
0206 /*
0207  * Irq methods
0208  */
0209 
0210 static void gsta_irq_disable(struct irq_data *data)
0211 {
0212     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0213     struct gsta_gpio *chip = gc->private;
0214     int nr = data->irq - chip->irq_base;
0215     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0216     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0217     u32 val;
0218     unsigned long flags;
0219 
0220     spin_lock_irqsave(&chip->lock, flags);
0221     if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
0222         val = readl(&regs->rimsc) & ~bit;
0223         writel(val, &regs->rimsc);
0224     }
0225     if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
0226         val = readl(&regs->fimsc) & ~bit;
0227         writel(val, &regs->fimsc);
0228     }
0229     spin_unlock_irqrestore(&chip->lock, flags);
0230     return;
0231 }
0232 
0233 static void gsta_irq_enable(struct irq_data *data)
0234 {
0235     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0236     struct gsta_gpio *chip = gc->private;
0237     int nr = data->irq - chip->irq_base;
0238     struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
0239     u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
0240     u32 val;
0241     int type;
0242     unsigned long flags;
0243 
0244     type = chip->irq_type[nr];
0245 
0246     spin_lock_irqsave(&chip->lock, flags);
0247     val = readl(&regs->rimsc);
0248     if (type & IRQ_TYPE_EDGE_RISING)
0249         writel(val | bit, &regs->rimsc);
0250     else
0251         writel(val & ~bit, &regs->rimsc);
0252     val = readl(&regs->rimsc);
0253     if (type & IRQ_TYPE_EDGE_FALLING)
0254         writel(val | bit, &regs->fimsc);
0255     else
0256         writel(val & ~bit, &regs->fimsc);
0257     spin_unlock_irqrestore(&chip->lock, flags);
0258     return;
0259 }
0260 
0261 static int gsta_irq_type(struct irq_data *d, unsigned int type)
0262 {
0263     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0264     struct gsta_gpio *chip = gc->private;
0265     int nr = d->irq - chip->irq_base;
0266 
0267     /* We only support edge interrupts */
0268     if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
0269         pr_debug("%s: unsupported type 0x%x\n", __func__, type);
0270         return -EINVAL;
0271     }
0272 
0273     chip->irq_type[nr] = type; /* used for enable/disable */
0274 
0275     gsta_irq_enable(d);
0276     return 0;
0277 }
0278 
0279 static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
0280 {
0281     struct gsta_gpio *chip = dev_id;
0282     struct gsta_regs __iomem *regs;
0283     u32 is;
0284     int i, nr, base;
0285     irqreturn_t ret = IRQ_NONE;
0286 
0287     for (i = 0; i < GSTA_NR_BLOCKS; i++) {
0288         regs = chip->regs[i];
0289         base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
0290         while ((is = readl(&regs->is))) {
0291             nr = __ffs(is);
0292             irq = base + nr;
0293             generic_handle_irq(irq);
0294             writel(1 << nr, &regs->ic);
0295             ret = IRQ_HANDLED;
0296         }
0297     }
0298     return ret;
0299 }
0300 
0301 static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
0302 {
0303     struct irq_chip_generic *gc;
0304     struct irq_chip_type *ct;
0305     int rv;
0306 
0307     gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
0308                      chip->irq_base,
0309                      chip->reg_base, handle_simple_irq);
0310     if (!gc)
0311         return -ENOMEM;
0312 
0313     gc->private = chip;
0314     ct = gc->chip_types;
0315 
0316     ct->chip.irq_set_type = gsta_irq_type;
0317     ct->chip.irq_disable = gsta_irq_disable;
0318     ct->chip.irq_enable = gsta_irq_enable;
0319 
0320     /* FIXME: this makes at most 32 interrupts. Request 0 by now */
0321     rv = devm_irq_setup_generic_chip(chip->dev, gc,
0322                      0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */,
0323                      0, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
0324     if (rv)
0325         return rv;
0326 
0327     /* Set up all 128 interrupts: code from setup_generic_chip */
0328     {
0329         struct irq_chip_type *ct = gc->chip_types;
0330         int i, j;
0331         for (j = 0; j < GSTA_NR_GPIO; j++) {
0332             i = chip->irq_base + j;
0333             irq_set_chip_and_handler(i, &ct->chip, ct->handler);
0334             irq_set_chip_data(i, gc);
0335             irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
0336         }
0337         gc->irq_cnt = i - gc->irq_base;
0338     }
0339 
0340     return 0;
0341 }
0342 
0343 /* The platform device used here is instantiated by the MFD device */
0344 static int gsta_probe(struct platform_device *dev)
0345 {
0346     int i, err;
0347     struct pci_dev *pdev;
0348     struct sta2x11_gpio_pdata *gpio_pdata;
0349     struct gsta_gpio *chip;
0350 
0351     pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
0352     gpio_pdata = dev_get_platdata(&pdev->dev);
0353 
0354     if (gpio_pdata == NULL)
0355         dev_err(&dev->dev, "no gpio config\n");
0356     pr_debug("gpio config: %p\n", gpio_pdata);
0357 
0358     chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
0359     if (!chip)
0360         return -ENOMEM;
0361     chip->dev = &dev->dev;
0362     chip->reg_base = devm_platform_ioremap_resource(dev, 0);
0363     if (IS_ERR(chip->reg_base))
0364         return PTR_ERR(chip->reg_base);
0365 
0366     for (i = 0; i < GSTA_NR_BLOCKS; i++) {
0367         chip->regs[i] = chip->reg_base + i * 4096;
0368         /* disable all irqs */
0369         writel(0, &chip->regs[i]->rimsc);
0370         writel(0, &chip->regs[i]->fimsc);
0371         writel(~0, &chip->regs[i]->ic);
0372     }
0373     spin_lock_init(&chip->lock);
0374     gsta_gpio_setup(chip);
0375     if (gpio_pdata)
0376         for (i = 0; i < GSTA_NR_GPIO; i++)
0377             gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
0378 
0379     /* 384 was used in previous code: be compatible for other drivers */
0380     err = devm_irq_alloc_descs(&dev->dev, -1, 384,
0381                    GSTA_NR_GPIO, NUMA_NO_NODE);
0382     if (err < 0) {
0383         dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
0384              -err);
0385         return err;
0386     }
0387     chip->irq_base = err;
0388 
0389     err = gsta_alloc_irq_chip(chip);
0390     if (err)
0391         return err;
0392 
0393     err = devm_request_irq(&dev->dev, pdev->irq, gsta_gpio_handler,
0394                    IRQF_SHARED, KBUILD_MODNAME, chip);
0395     if (err < 0) {
0396         dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
0397             -err);
0398         return err;
0399     }
0400 
0401     return devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
0402 }
0403 
0404 static struct platform_driver sta2x11_gpio_platform_driver = {
0405     .driver = {
0406         .name   = "sta2x11-gpio",
0407         .suppress_bind_attrs = true,
0408     },
0409     .probe = gsta_probe,
0410 };
0411 builtin_platform_driver(sta2x11_gpio_platform_driver);
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