drivers/gpio/gpio-spear-spics.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPEAr platform SPI chipselect abstraction over gpiolib
0004  *
0005  * Copyright (C) 2012 ST Microelectronics
0006  * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
0007  */
0008
0009 #include <linux/err.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/io.h>
0012 #include <linux/init.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/types.h>
0016
0017 /* maximum chipselects */
0018 #define NUM_OF_GPIO 4
0019
0020 /*
0021  * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
0022  * through system registers. This register lies outside spi (pl022)
0023  * address space into system registers.
0024  *
0025  * It provides control for spi chip select lines so that any chipselect
0026  * (out of 4 possible chipselects in pl022) can be made low to select
0027  * the particular slave.
0028  */
0029
0030 /**
0031  * struct spear_spics - represents spi chip select control
0032  * @base: base address
0033  * @perip_cfg: configuration register
0034  * @sw_enable_bit: bit to enable s/w control over chipselects
0035  * @cs_value_bit: bit to program high or low chipselect
0036  * @cs_enable_mask: mask to select bits required to select chipselect
0037  * @cs_enable_shift: bit pos of cs_enable_mask
0038  * @use_count: use count of a spi controller cs lines
0039  * @last_off: stores last offset caller of set_value()
0040  * @chip: gpio_chip abstraction
0041  */
0042 struct spear_spics {
0043     void __iomem        *base;
0044     u32         perip_cfg;
0045     u32         sw_enable_bit;
0046     u32         cs_value_bit;
0047     u32         cs_enable_mask;
0048     u32         cs_enable_shift;
0049     unsigned long       use_count;
0050     int         last_off;
0051     struct gpio_chip    chip;
0052 };
0053
0054 /* gpio framework specific routines */
0055 static int spics_get_value(struct gpio_chip *chip, unsigned offset)
0056 {
0057     return -ENXIO;
0058 }
0059
0060 static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
0061 {
0062     struct spear_spics *spics = gpiochip_get_data(chip);
0063     u32 tmp;
0064
0065     /* select chip select from register */
0066     tmp = readl_relaxed(spics->base + spics->perip_cfg);
0067     if (spics->last_off != offset) {
0068         spics->last_off = offset;
0069         tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
0070         tmp |= offset << spics->cs_enable_shift;
0071     }
0072
0073     /* toggle chip select line */
0074     tmp &= ~(0x1 << spics->cs_value_bit);
0075     tmp |= value << spics->cs_value_bit;
0076     writel_relaxed(tmp, spics->base + spics->perip_cfg);
0077 }
0078
0079 static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
0080 {
0081     return -ENXIO;
0082 }
0083
0084 static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
0085         int value)
0086 {
0087     spics_set_value(chip, offset, value);
0088     return 0;
0089 }
0090
0091 static int spics_request(struct gpio_chip *chip, unsigned offset)
0092 {
0093     struct spear_spics *spics = gpiochip_get_data(chip);
0094     u32 tmp;
0095
0096     if (!spics->use_count++) {
0097         tmp = readl_relaxed(spics->base + spics->perip_cfg);
0098         tmp |= 0x1 << spics->sw_enable_bit;
0099         tmp |= 0x1 << spics->cs_value_bit;
0100         writel_relaxed(tmp, spics->base + spics->perip_cfg);
0101     }
0102
0103     return 0;
0104 }
0105
0106 static void spics_free(struct gpio_chip *chip, unsigned offset)
0107 {
0108     struct spear_spics *spics = gpiochip_get_data(chip);
0109     u32 tmp;
0110
0111     if (!--spics->use_count) {
0112         tmp = readl_relaxed(spics->base + spics->perip_cfg);
0113         tmp &= ~(0x1 << spics->sw_enable_bit);
0114         writel_relaxed(tmp, spics->base + spics->perip_cfg);
0115     }
0116 }
0117
0118 static int spics_gpio_probe(struct platform_device *pdev)
0119 {
0120     struct device_node *np = pdev->dev.of_node;
0121     struct spear_spics *spics;
0122
0123     spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
0124     if (!spics)
0125         return -ENOMEM;
0126
0127     spics->base = devm_platform_ioremap_resource(pdev, 0);
0128     if (IS_ERR(spics->base))
0129         return PTR_ERR(spics->base);
0130
0131     if (of_property_read_u32(np, "st-spics,peripcfg-reg",
0132                 &spics->perip_cfg))
0133         goto err_dt_data;
0134     if (of_property_read_u32(np, "st-spics,sw-enable-bit",
0135                 &spics->sw_enable_bit))
0136         goto err_dt_data;
0137     if (of_property_read_u32(np, "st-spics,cs-value-bit",
0138                 &spics->cs_value_bit))
0139         goto err_dt_data;
0140     if (of_property_read_u32(np, "st-spics,cs-enable-mask",
0141                 &spics->cs_enable_mask))
0142         goto err_dt_data;
0143     if (of_property_read_u32(np, "st-spics,cs-enable-shift",
0144                 &spics->cs_enable_shift))
0145         goto err_dt_data;
0146
0147     spics->chip.ngpio = NUM_OF_GPIO;
0148     spics->chip.base = -1;
0149     spics->chip.request = spics_request;
0150     spics->chip.free = spics_free;
0151     spics->chip.direction_input = spics_direction_input;
0152     spics->chip.direction_output = spics_direction_output;
0153     spics->chip.get = spics_get_value;
0154     spics->chip.set = spics_set_value;
0155     spics->chip.label = dev_name(&pdev->dev);
0156     spics->chip.parent = &pdev->dev;
0157     spics->chip.owner = THIS_MODULE;
0158     spics->last_off = -1;
0159
0160     return devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics);
0161
0162 err_dt_data:
0163     dev_err(&pdev->dev, "DT probe failed\n");
0164     return -EINVAL;
0165 }
0166
0167 static const struct of_device_id spics_gpio_of_match[] = {
0168     { .compatible = "st,spear-spics-gpio" },
0169     {}
0170 };
0171
0172 static struct platform_driver spics_gpio_driver = {
0173     .probe = spics_gpio_probe,
0174     .driver = {
0175         .name = "spear-spics-gpio",
0176         .of_match_table = spics_gpio_of_match,
0177     },
0178 };
0179
0180 static int __init spics_gpio_init(void)
0181 {
0182     return platform_driver_register(&spics_gpio_driver);
0183 }
0184 subsys_initcall(spics_gpio_init);