drivers/gpio/gpio-sodaville.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  GPIO interface for Intel Sodaville SoCs.
0004  *
0005  *  Copyright (c) 2010, 2011 Intel Corporation
0006  *
0007  *  Author: Hans J. Koch <hjk@linutronix.de>
0008  */
0009
0010 #include <linux/errno.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/irq.h>
0016 #include <linux/kernel.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/pci.h>
0019 #include <linux/platform_device.h>
0020
0021 #define DRV_NAME        "sdv_gpio"
0022 #define SDV_NUM_PUB_GPIOS   12
0023 #define PCI_DEVICE_ID_SDV_GPIO  0x2e67
0024 #define GPIO_BAR        0
0025
0026 #define GPOUTR      0x00
0027 #define GPOER       0x04
0028 #define GPINR       0x08
0029
0030 #define GPSTR       0x0c
0031 #define GPIT1R0     0x10
0032 #define GPIO_INT    0x14
0033 #define GPIT1R1     0x18
0034
0035 #define GPMUXCTL    0x1c
0036
0037 struct sdv_gpio_chip_data {
0038     int irq_base;
0039     void __iomem *gpio_pub_base;
0040     struct irq_domain *id;
0041     struct irq_chip_generic *gc;
0042     struct gpio_chip chip;
0043 };
0044
0045 static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
0046 {
0047     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0048     struct sdv_gpio_chip_data *sd = gc->private;
0049     void __iomem *type_reg;
0050     u32 reg;
0051
0052     if (d->hwirq < 8)
0053         type_reg = sd->gpio_pub_base + GPIT1R0;
0054     else
0055         type_reg = sd->gpio_pub_base + GPIT1R1;
0056
0057     reg = readl(type_reg);
0058
0059     switch (type) {
0060     case IRQ_TYPE_LEVEL_HIGH:
0061         reg &= ~BIT(4 * (d->hwirq % 8));
0062         break;
0063
0064     case IRQ_TYPE_LEVEL_LOW:
0065         reg |= BIT(4 * (d->hwirq % 8));
0066         break;
0067
0068     default:
0069         return -EINVAL;
0070     }
0071
0072     writel(reg, type_reg);
0073     return 0;
0074 }
0075
0076 static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
0077 {
0078     struct sdv_gpio_chip_data *sd = data;
0079     unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
0080     int irq_bit;
0081
0082     irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
0083     if (!irq_stat)
0084         return IRQ_NONE;
0085
0086     for_each_set_bit(irq_bit, &irq_stat, 32)
0087         generic_handle_domain_irq(sd->id, irq_bit);
0088
0089     return IRQ_HANDLED;
0090 }
0091
0092 static int sdv_xlate(struct irq_domain *h, struct device_node *node,
0093         const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
0094         u32 *out_type)
0095 {
0096     u32 line, type;
0097
0098     if (node != irq_domain_get_of_node(h))
0099         return -EINVAL;
0100
0101     if (intsize < 2)
0102         return -EINVAL;
0103
0104     line = *intspec;
0105     *out_hwirq = line;
0106
0107     intspec++;
0108     type = *intspec;
0109
0110     switch (type) {
0111     case IRQ_TYPE_LEVEL_LOW:
0112     case IRQ_TYPE_LEVEL_HIGH:
0113         *out_type = type;
0114         break;
0115     default:
0116         return -EINVAL;
0117     }
0118     return 0;
0119 }
0120
0121 static const struct irq_domain_ops irq_domain_sdv_ops = {
0122     .xlate = sdv_xlate,
0123 };
0124
0125 static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
0126         struct pci_dev *pdev)
0127 {
0128     struct irq_chip_type *ct;
0129     int ret;
0130
0131     sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
0132                         SDV_NUM_PUB_GPIOS, -1);
0133     if (sd->irq_base < 0)
0134         return sd->irq_base;
0135
0136     /* mask + ACK all interrupt sources */
0137     writel(0, sd->gpio_pub_base + GPIO_INT);
0138     writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
0139
0140     ret = devm_request_irq(&pdev->dev, pdev->irq,
0141                    sdv_gpio_pub_irq_handler, IRQF_SHARED,
0142                    "sdv_gpio", sd);
0143     if (ret)
0144         return ret;
0145
0146     /*
0147      * This gpio irq controller latches level irqs. Testing shows that if
0148      * we unmask & ACK the IRQ before the source of the interrupt is gone
0149      * then the interrupt is active again.
0150      */
0151     sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
0152                          sd->irq_base,
0153                          sd->gpio_pub_base,
0154                          handle_fasteoi_irq);
0155     if (!sd->gc)
0156         return -ENOMEM;
0157
0158     sd->gc->private = sd;
0159     ct = sd->gc->chip_types;
0160     ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
0161     ct->regs.eoi = GPSTR;
0162     ct->regs.mask = GPIO_INT;
0163     ct->chip.irq_mask = irq_gc_mask_clr_bit;
0164     ct->chip.irq_unmask = irq_gc_mask_set_bit;
0165     ct->chip.irq_eoi = irq_gc_eoi;
0166     ct->chip.irq_set_type = sdv_gpio_pub_set_type;
0167
0168     irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
0169             IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
0170             IRQ_LEVEL | IRQ_NOPROBE);
0171
0172     sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
0173                 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
0174     if (!sd->id)
0175         return -ENODEV;
0176
0177     return 0;
0178 }
0179
0180 static int sdv_gpio_probe(struct pci_dev *pdev,
0181                     const struct pci_device_id *pci_id)
0182 {
0183     struct sdv_gpio_chip_data *sd;
0184     int ret;
0185     u32 mux_val;
0186
0187     sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
0188     if (!sd)
0189         return -ENOMEM;
0190
0191     ret = pcim_enable_device(pdev);
0192     if (ret) {
0193         dev_err(&pdev->dev, "can't enable device.\n");
0194         return ret;
0195     }
0196
0197     ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
0198     if (ret) {
0199         dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
0200         return ret;
0201     }
0202
0203     sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
0204
0205     ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
0206     if (!ret)
0207         writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
0208
0209     ret = bgpio_init(&sd->chip, &pdev->dev, 4,
0210             sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
0211             NULL, sd->gpio_pub_base + GPOER, NULL, 0);
0212     if (ret)
0213         return ret;
0214
0215     sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
0216
0217     ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
0218     if (ret < 0) {
0219         dev_err(&pdev->dev, "gpiochip_add() failed.\n");
0220         return ret;
0221     }
0222
0223     ret = sdv_register_irqsupport(sd, pdev);
0224     if (ret)
0225         return ret;
0226
0227     pci_set_drvdata(pdev, sd);
0228     dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
0229     return 0;
0230 }
0231
0232 static const struct pci_device_id sdv_gpio_pci_ids[] = {
0233     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
0234     { 0, },
0235 };
0236
0237 static struct pci_driver sdv_gpio_driver = {
0238     .driver = {
0239         .suppress_bind_attrs = true,
0240     },
0241     .name = DRV_NAME,
0242     .id_table = sdv_gpio_pci_ids,
0243     .probe = sdv_gpio_probe,
0244 };
0245 builtin_pci_driver(sdv_gpio_driver);