drivers/gpio/gpio-sifive.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2019 SiFive
0004  */
0005
0006 #include <linux/bitops.h>
0007 #include <linux/device.h>
0008 #include <linux/errno.h>
0009 #include <linux/of_irq.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/init.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/slab.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/regmap.h>
0016
0017 #define SIFIVE_GPIO_INPUT_VAL   0x00
0018 #define SIFIVE_GPIO_INPUT_EN    0x04
0019 #define SIFIVE_GPIO_OUTPUT_EN   0x08
0020 #define SIFIVE_GPIO_OUTPUT_VAL  0x0C
0021 #define SIFIVE_GPIO_RISE_IE 0x18
0022 #define SIFIVE_GPIO_RISE_IP 0x1C
0023 #define SIFIVE_GPIO_FALL_IE 0x20
0024 #define SIFIVE_GPIO_FALL_IP 0x24
0025 #define SIFIVE_GPIO_HIGH_IE 0x28
0026 #define SIFIVE_GPIO_HIGH_IP 0x2C
0027 #define SIFIVE_GPIO_LOW_IE  0x30
0028 #define SIFIVE_GPIO_LOW_IP  0x34
0029 #define SIFIVE_GPIO_OUTPUT_XOR  0x40
0030
0031 #define SIFIVE_GPIO_MAX     32
0032
0033 struct sifive_gpio {
0034     void __iomem        *base;
0035     struct gpio_chip    gc;
0036     struct regmap       *regs;
0037     unsigned long       irq_state;
0038     unsigned int        trigger[SIFIVE_GPIO_MAX];
0039     unsigned int        irq_number[SIFIVE_GPIO_MAX];
0040 };
0041
0042 static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
0043 {
0044     unsigned long flags;
0045     unsigned int trigger;
0046
0047     raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
0048     trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
0049     regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
0050                (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
0051     regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
0052                (trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
0053     regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
0054                (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
0055     regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
0056                (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
0057     raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
0058 }
0059
0060 static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
0061 {
0062     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0063     struct sifive_gpio *chip = gpiochip_get_data(gc);
0064     int offset = irqd_to_hwirq(d);
0065
0066     if (offset < 0 || offset >= gc->ngpio)
0067         return -EINVAL;
0068
0069     chip->trigger[offset] = trigger;
0070     sifive_gpio_set_ie(chip, offset);
0071     return 0;
0072 }
0073
0074 static void sifive_gpio_irq_enable(struct irq_data *d)
0075 {
0076     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0077     struct sifive_gpio *chip = gpiochip_get_data(gc);
0078     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0079     int offset = hwirq % SIFIVE_GPIO_MAX;
0080     u32 bit = BIT(offset);
0081     unsigned long flags;
0082
0083     gpiochip_enable_irq(gc, hwirq);
0084     irq_chip_enable_parent(d);
0085
0086     /* Switch to input */
0087     gc->direction_input(gc, offset);
0088
0089     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0090     /* Clear any sticky pending interrupts */
0091     regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
0092     regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
0093     regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
0094     regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
0095     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0096
0097     /* Enable interrupts */
0098     assign_bit(offset, &chip->irq_state, 1);
0099     sifive_gpio_set_ie(chip, offset);
0100 }
0101
0102 static void sifive_gpio_irq_disable(struct irq_data *d)
0103 {
0104     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0105     struct sifive_gpio *chip = gpiochip_get_data(gc);
0106     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0107     int offset = hwirq % SIFIVE_GPIO_MAX;
0108
0109     assign_bit(offset, &chip->irq_state, 0);
0110     sifive_gpio_set_ie(chip, offset);
0111     irq_chip_disable_parent(d);
0112     gpiochip_disable_irq(gc, hwirq);
0113 }
0114
0115 static void sifive_gpio_irq_eoi(struct irq_data *d)
0116 {
0117     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0118     struct sifive_gpio *chip = gpiochip_get_data(gc);
0119     int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
0120     u32 bit = BIT(offset);
0121     unsigned long flags;
0122
0123     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0124     /* Clear all pending interrupts */
0125     regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
0126     regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
0127     regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
0128     regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
0129     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0130
0131     irq_chip_eoi_parent(d);
0132 }
0133
0134 static int sifive_gpio_irq_set_affinity(struct irq_data *data,
0135                     const struct cpumask *dest,
0136                     bool force)
0137 {
0138     if (data->parent_data)
0139         return irq_chip_set_affinity_parent(data, dest, force);
0140
0141     return -EINVAL;
0142 }
0143
0144 static const struct irq_chip sifive_gpio_irqchip = {
0145     .name       = "sifive-gpio",
0146     .irq_set_type   = sifive_gpio_irq_set_type,
0147     .irq_mask   = irq_chip_mask_parent,
0148     .irq_unmask = irq_chip_unmask_parent,
0149     .irq_enable = sifive_gpio_irq_enable,
0150     .irq_disable    = sifive_gpio_irq_disable,
0151     .irq_eoi    = sifive_gpio_irq_eoi,
0152     .irq_set_affinity = sifive_gpio_irq_set_affinity,
0153     .flags      = IRQCHIP_IMMUTABLE,
0154     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0155 };
0156
0157 static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
0158                          unsigned int child,
0159                          unsigned int child_type,
0160                          unsigned int *parent,
0161                          unsigned int *parent_type)
0162 {
0163     struct sifive_gpio *chip = gpiochip_get_data(gc);
0164     struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);
0165
0166     *parent_type = IRQ_TYPE_NONE;
0167     *parent = irqd_to_hwirq(d);
0168
0169     return 0;
0170 }
0171
0172 static const struct regmap_config sifive_gpio_regmap_config = {
0173     .reg_bits = 32,
0174     .reg_stride = 4,
0175     .val_bits = 32,
0176     .fast_io = true,
0177     .disable_locking = true,
0178 };
0179
0180 static int sifive_gpio_probe(struct platform_device *pdev)
0181 {
0182     struct device *dev = &pdev->dev;
0183     struct device_node *node = pdev->dev.of_node;
0184     struct device_node *irq_parent;
0185     struct irq_domain *parent;
0186     struct gpio_irq_chip *girq;
0187     struct sifive_gpio *chip;
0188     int ret, ngpio, i;
0189
0190     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0191     if (!chip)
0192         return -ENOMEM;
0193
0194     chip->base = devm_platform_ioremap_resource(pdev, 0);
0195     if (IS_ERR(chip->base)) {
0196         dev_err(dev, "failed to allocate device memory\n");
0197         return PTR_ERR(chip->base);
0198     }
0199
0200     chip->regs = devm_regmap_init_mmio(dev, chip->base,
0201                        &sifive_gpio_regmap_config);
0202     if (IS_ERR(chip->regs))
0203         return PTR_ERR(chip->regs);
0204
0205     ngpio = of_irq_count(node);
0206     if (ngpio > SIFIVE_GPIO_MAX) {
0207         dev_err(dev, "Too many GPIO interrupts (max=%d)\n",
0208             SIFIVE_GPIO_MAX);
0209         return -ENXIO;
0210     }
0211
0212     irq_parent = of_irq_find_parent(node);
0213     if (!irq_parent) {
0214         dev_err(dev, "no IRQ parent node\n");
0215         return -ENODEV;
0216     }
0217     parent = irq_find_host(irq_parent);
0218     if (!parent) {
0219         dev_err(dev, "no IRQ parent domain\n");
0220         return -ENODEV;
0221     }
0222
0223     for (i = 0; i < ngpio; i++)
0224         chip->irq_number[i] = platform_get_irq(pdev, i);
0225
0226     ret = bgpio_init(&chip->gc, dev, 4,
0227              chip->base + SIFIVE_GPIO_INPUT_VAL,
0228              chip->base + SIFIVE_GPIO_OUTPUT_VAL,
0229              NULL,
0230              chip->base + SIFIVE_GPIO_OUTPUT_EN,
0231              chip->base + SIFIVE_GPIO_INPUT_EN,
0232              BGPIOF_READ_OUTPUT_REG_SET);
0233     if (ret) {
0234         dev_err(dev, "unable to init generic GPIO\n");
0235         return ret;
0236     }
0237
0238     /* Disable all GPIO interrupts before enabling parent interrupts */
0239     regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
0240     regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
0241     regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
0242     regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
0243     chip->irq_state = 0;
0244
0245     chip->gc.base = -1;
0246     chip->gc.ngpio = ngpio;
0247     chip->gc.label = dev_name(dev);
0248     chip->gc.parent = dev;
0249     chip->gc.owner = THIS_MODULE;
0250     girq = &chip->gc.irq;
0251     gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
0252     girq->fwnode = of_node_to_fwnode(node);
0253     girq->parent_domain = parent;
0254     girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
0255     girq->handler = handle_bad_irq;
0256     girq->default_type = IRQ_TYPE_NONE;
0257
0258     platform_set_drvdata(pdev, chip);
0259     return gpiochip_add_data(&chip->gc, chip);
0260 }
0261
0262 static const struct of_device_id sifive_gpio_match[] = {
0263     { .compatible = "sifive,gpio0" },
0264     { .compatible = "sifive,fu540-c000-gpio" },
0265     { },
0266 };
0267
0268 static struct platform_driver sifive_gpio_driver = {
0269     .probe      = sifive_gpio_probe,
0270     .driver = {
0271         .name   = "sifive_gpio",
0272         .of_match_table = of_match_ptr(sifive_gpio_match),
0273     },
0274 };
0275 builtin_platform_driver(sifive_gpio_driver)