drivers/gpio/gpio-sch.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * GPIO interface for Intel Poulsbo SCH
0004  *
0005  *  Copyright (c) 2010 CompuLab Ltd
0006  *  Author: Denis Turischev <denis@compulab.co.il>
0007  */
0008
0009 #include <linux/acpi.h>
0010 #include <linux/bitops.h>
0011 #include <linux/errno.h>
0012 #include <linux/gpio/driver.h>
0013 #include <linux/io.h>
0014 #include <linux/irq.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/pci_ids.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/types.h>
0020
0021 #define GEN 0x00
0022 #define GIO 0x04
0023 #define GLV 0x08
0024 #define GTPE    0x0c
0025 #define GTNE    0x10
0026 #define GGPE    0x14
0027 #define GSMI    0x18
0028 #define GTS 0x1c
0029
0030 #define CORE_BANK_OFFSET    0x00
0031 #define RESUME_BANK_OFFSET  0x20
0032
0033 /*
0034  * iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
0035  * Document Number: 328195-001
0036  */
0037 #define GPE0E_GPIO  14
0038
0039 struct sch_gpio {
0040     struct gpio_chip chip;
0041     spinlock_t lock;
0042     unsigned short iobase;
0043     unsigned short resume_base;
0044
0045     /* GPE handling */
0046     u32 gpe;
0047     acpi_gpe_handler gpe_handler;
0048 };
0049
0050 static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
0051                 unsigned int reg)
0052 {
0053     unsigned int base = CORE_BANK_OFFSET;
0054
0055     if (gpio >= sch->resume_base) {
0056         gpio -= sch->resume_base;
0057         base = RESUME_BANK_OFFSET;
0058     }
0059
0060     return base + reg + gpio / 8;
0061 }
0062
0063 static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
0064 {
0065     if (gpio >= sch->resume_base)
0066         gpio -= sch->resume_base;
0067     return gpio % 8;
0068 }
0069
0070 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
0071 {
0072     unsigned short offset, bit;
0073     u8 reg_val;
0074
0075     offset = sch_gpio_offset(sch, gpio, reg);
0076     bit = sch_gpio_bit(sch, gpio);
0077
0078     reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
0079
0080     return reg_val;
0081 }
0082
0083 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
0084                  int val)
0085 {
0086     unsigned short offset, bit;
0087     u8 reg_val;
0088
0089     offset = sch_gpio_offset(sch, gpio, reg);
0090     bit = sch_gpio_bit(sch, gpio);
0091
0092     reg_val = inb(sch->iobase + offset);
0093
0094     if (val)
0095         outb(reg_val | BIT(bit), sch->iobase + offset);
0096     else
0097         outb((reg_val & ~BIT(bit)), sch->iobase + offset);
0098 }
0099
0100 static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
0101 {
0102     struct sch_gpio *sch = gpiochip_get_data(gc);
0103     unsigned long flags;
0104
0105     spin_lock_irqsave(&sch->lock, flags);
0106     sch_gpio_reg_set(sch, gpio_num, GIO, 1);
0107     spin_unlock_irqrestore(&sch->lock, flags);
0108     return 0;
0109 }
0110
0111 static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
0112 {
0113     struct sch_gpio *sch = gpiochip_get_data(gc);
0114
0115     return sch_gpio_reg_get(sch, gpio_num, GLV);
0116 }
0117
0118 static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
0119 {
0120     struct sch_gpio *sch = gpiochip_get_data(gc);
0121     unsigned long flags;
0122
0123     spin_lock_irqsave(&sch->lock, flags);
0124     sch_gpio_reg_set(sch, gpio_num, GLV, val);
0125     spin_unlock_irqrestore(&sch->lock, flags);
0126 }
0127
0128 static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
0129                   int val)
0130 {
0131     struct sch_gpio *sch = gpiochip_get_data(gc);
0132     unsigned long flags;
0133
0134     spin_lock_irqsave(&sch->lock, flags);
0135     sch_gpio_reg_set(sch, gpio_num, GIO, 0);
0136     spin_unlock_irqrestore(&sch->lock, flags);
0137
0138     /*
0139      * according to the datasheet, writing to the level register has no
0140      * effect when GPIO is programmed as input.
0141      * Actually the level register is read-only when configured as input.
0142      * Thus presetting the output level before switching to output is _NOT_ possible.
0143      * Hence we set the level after configuring the GPIO as output.
0144      * But we cannot prevent a short low pulse if direction is set to high
0145      * and an external pull-up is connected.
0146      */
0147     sch_gpio_set(gc, gpio_num, val);
0148     return 0;
0149 }
0150
0151 static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
0152 {
0153     struct sch_gpio *sch = gpiochip_get_data(gc);
0154
0155     if (sch_gpio_reg_get(sch, gpio_num, GIO))
0156         return GPIO_LINE_DIRECTION_IN;
0157
0158     return GPIO_LINE_DIRECTION_OUT;
0159 }
0160
0161 static const struct gpio_chip sch_gpio_chip = {
0162     .label          = "sch_gpio",
0163     .owner          = THIS_MODULE,
0164     .direction_input    = sch_gpio_direction_in,
0165     .get            = sch_gpio_get,
0166     .direction_output   = sch_gpio_direction_out,
0167     .set            = sch_gpio_set,
0168     .get_direction      = sch_gpio_get_direction,
0169 };
0170
0171 static int sch_irq_type(struct irq_data *d, unsigned int type)
0172 {
0173     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0174     struct sch_gpio *sch = gpiochip_get_data(gc);
0175     irq_hw_number_t gpio_num = irqd_to_hwirq(d);
0176     unsigned long flags;
0177     int rising, falling;
0178
0179     switch (type & IRQ_TYPE_SENSE_MASK) {
0180     case IRQ_TYPE_EDGE_RISING:
0181         rising = 1;
0182         falling = 0;
0183         break;
0184     case IRQ_TYPE_EDGE_FALLING:
0185         rising = 0;
0186         falling = 1;
0187         break;
0188     case IRQ_TYPE_EDGE_BOTH:
0189         rising = 1;
0190         falling = 1;
0191         break;
0192     default:
0193         return -EINVAL;
0194     }
0195
0196     spin_lock_irqsave(&sch->lock, flags);
0197
0198     sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
0199     sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
0200
0201     irq_set_handler_locked(d, handle_edge_irq);
0202
0203     spin_unlock_irqrestore(&sch->lock, flags);
0204
0205     return 0;
0206 }
0207
0208 static void sch_irq_ack(struct irq_data *d)
0209 {
0210     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0211     struct sch_gpio *sch = gpiochip_get_data(gc);
0212     irq_hw_number_t gpio_num = irqd_to_hwirq(d);
0213     unsigned long flags;
0214
0215     spin_lock_irqsave(&sch->lock, flags);
0216     sch_gpio_reg_set(sch, gpio_num, GTS, 1);
0217     spin_unlock_irqrestore(&sch->lock, flags);
0218 }
0219
0220 static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
0221 {
0222     struct sch_gpio *sch = gpiochip_get_data(gc);
0223     unsigned long flags;
0224
0225     spin_lock_irqsave(&sch->lock, flags);
0226     sch_gpio_reg_set(sch, gpio_num, GGPE, val);
0227     spin_unlock_irqrestore(&sch->lock, flags);
0228 }
0229
0230 static void sch_irq_mask(struct irq_data *d)
0231 {
0232     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0233     irq_hw_number_t gpio_num = irqd_to_hwirq(d);
0234
0235     sch_irq_mask_unmask(gc, gpio_num, 0);
0236     gpiochip_disable_irq(gc, gpio_num);
0237 }
0238
0239 static void sch_irq_unmask(struct irq_data *d)
0240 {
0241     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0242     irq_hw_number_t gpio_num = irqd_to_hwirq(d);
0243
0244     gpiochip_enable_irq(gc, gpio_num);
0245     sch_irq_mask_unmask(gc, gpio_num, 1);
0246 }
0247
0248 static const struct irq_chip sch_irqchip = {
0249     .name = "sch_gpio",
0250     .irq_ack = sch_irq_ack,
0251     .irq_mask = sch_irq_mask,
0252     .irq_unmask = sch_irq_unmask,
0253     .irq_set_type = sch_irq_type,
0254     .flags = IRQCHIP_IMMUTABLE,
0255     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0256 };
0257
0258 static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
0259 {
0260     struct sch_gpio *sch = context;
0261     struct gpio_chip *gc = &sch->chip;
0262     unsigned long core_status, resume_status;
0263     unsigned long pending;
0264     unsigned long flags;
0265     int offset;
0266     u32 ret;
0267
0268     spin_lock_irqsave(&sch->lock, flags);
0269
0270     core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
0271     resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
0272
0273     spin_unlock_irqrestore(&sch->lock, flags);
0274
0275     pending = (resume_status << sch->resume_base) | core_status;
0276     for_each_set_bit(offset, &pending, sch->chip.ngpio)
0277         generic_handle_domain_irq(gc->irq.domain, offset);
0278
0279     /* Set returning value depending on whether we handled an interrupt */
0280     ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
0281
0282     /* Acknowledge GPE to ACPICA */
0283     ret |= ACPI_REENABLE_GPE;
0284
0285     return ret;
0286 }
0287
0288 static void sch_gpio_remove_gpe_handler(void *data)
0289 {
0290     struct sch_gpio *sch = data;
0291
0292     acpi_disable_gpe(NULL, sch->gpe);
0293     acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
0294 }
0295
0296 static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
0297 {
0298     struct device *dev = sch->chip.parent;
0299     acpi_status status;
0300
0301     status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
0302                       sch->gpe_handler, sch);
0303     if (ACPI_FAILURE(status)) {
0304         dev_err(dev, "Failed to install GPE handler for %u: %s\n",
0305             sch->gpe, acpi_format_exception(status));
0306         return -ENODEV;
0307     }
0308
0309     status = acpi_enable_gpe(NULL, sch->gpe);
0310     if (ACPI_FAILURE(status)) {
0311         dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
0312             sch->gpe, acpi_format_exception(status));
0313         acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
0314         return -ENODEV;
0315     }
0316
0317     return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
0318 }
0319
0320 static int sch_gpio_probe(struct platform_device *pdev)
0321 {
0322     struct gpio_irq_chip *girq;
0323     struct sch_gpio *sch;
0324     struct resource *res;
0325     int ret;
0326
0327     sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
0328     if (!sch)
0329         return -ENOMEM;
0330
0331     res = platform_get_resource(pdev, IORESOURCE_IO, 0);
0332     if (!res)
0333         return -EBUSY;
0334
0335     if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
0336                  pdev->name))
0337         return -EBUSY;
0338
0339     spin_lock_init(&sch->lock);
0340     sch->iobase = res->start;
0341     sch->chip = sch_gpio_chip;
0342     sch->chip.label = dev_name(&pdev->dev);
0343     sch->chip.parent = &pdev->dev;
0344
0345     switch (pdev->id) {
0346     case PCI_DEVICE_ID_INTEL_SCH_LPC:
0347         sch->resume_base = 10;
0348         sch->chip.ngpio = 14;
0349
0350         /*
0351          * GPIO[6:0] enabled by default
0352          * GPIO7 is configured by the CMC as SLPIOVR
0353          * Enable GPIO[9:8] core powered gpios explicitly
0354          */
0355         sch_gpio_reg_set(sch, 8, GEN, 1);
0356         sch_gpio_reg_set(sch, 9, GEN, 1);
0357         /*
0358          * SUS_GPIO[2:0] enabled by default
0359          * Enable SUS_GPIO3 resume powered gpio explicitly
0360          */
0361         sch_gpio_reg_set(sch, 13, GEN, 1);
0362         break;
0363
0364     case PCI_DEVICE_ID_INTEL_ITC_LPC:
0365         sch->resume_base = 5;
0366         sch->chip.ngpio = 14;
0367         break;
0368
0369     case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
0370         sch->resume_base = 21;
0371         sch->chip.ngpio = 30;
0372         break;
0373
0374     case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
0375         sch->resume_base = 2;
0376         sch->chip.ngpio = 8;
0377         break;
0378
0379     default:
0380         return -ENODEV;
0381     }
0382
0383     platform_set_drvdata(pdev, sch);
0384
0385     girq = &sch->chip.irq;
0386     gpio_irq_chip_set_chip(girq, &sch_irqchip);
0387     girq->num_parents = 0;
0388     girq->parents = NULL;
0389     girq->parent_handler = NULL;
0390     girq->default_type = IRQ_TYPE_NONE;
0391     girq->handler = handle_bad_irq;
0392
0393     /* GPE setup is optional */
0394     sch->gpe = GPE0E_GPIO;
0395     sch->gpe_handler = sch_gpio_gpe_handler;
0396
0397     ret = sch_gpio_install_gpe_handler(sch);
0398     if (ret)
0399         dev_warn(&pdev->dev, "Can't setup GPE, no IRQ support\n");
0400
0401     return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
0402 }
0403
0404 static struct platform_driver sch_gpio_driver = {
0405     .driver = {
0406         .name = "sch_gpio",
0407     },
0408     .probe      = sch_gpio_probe,
0409 };
0410
0411 module_platform_driver(sch_gpio_driver);
0412
0413 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
0414 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
0415 MODULE_LICENSE("GPL v2");
0416 MODULE_ALIAS("platform:sch_gpio");