drivers/gpio/gpio-sa1100.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/mach-sa1100/gpio.c
0004  *
0005  * Generic SA-1100 GPIO handling
0006  */
0007 #include <linux/gpio/driver.h>
0008 #include <linux/init.h>
0009 #include <linux/module.h>
0010 #include <linux/io.h>
0011 #include <linux/syscore_ops.h>
0012 #include <soc/sa1100/pwer.h>
0013 #include <mach/hardware.h>
0014 #include <mach/irqs.h>
0015
0016 struct sa1100_gpio_chip {
0017     struct gpio_chip chip;
0018     void __iomem *membase;
0019     int irqbase;
0020     u32 irqmask;
0021     u32 irqrising;
0022     u32 irqfalling;
0023     u32 irqwake;
0024 };
0025
0026 #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip)
0027
0028 enum {
0029     R_GPLR = 0x00,
0030     R_GPDR = 0x04,
0031     R_GPSR = 0x08,
0032     R_GPCR = 0x0c,
0033     R_GRER = 0x10,
0034     R_GFER = 0x14,
0035     R_GEDR = 0x18,
0036     R_GAFR = 0x1c,
0037 };
0038
0039 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
0040 {
0041     return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
0042         BIT(offset);
0043 }
0044
0045 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0046 {
0047     int reg = value ? R_GPSR : R_GPCR;
0048
0049     writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
0050 }
0051
0052 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)
0053 {
0054     void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
0055
0056     if (readl_relaxed(gpdr) & BIT(offset))
0057         return GPIO_LINE_DIRECTION_OUT;
0058
0059     return GPIO_LINE_DIRECTION_IN;
0060 }
0061
0062 static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
0063 {
0064     void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
0065     unsigned long flags;
0066
0067     local_irq_save(flags);
0068     writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
0069     local_irq_restore(flags);
0070
0071     return 0;
0072 }
0073
0074 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
0075 {
0076     void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
0077     unsigned long flags;
0078
0079     local_irq_save(flags);
0080     sa1100_gpio_set(chip, offset, value);
0081     writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
0082     local_irq_restore(flags);
0083
0084     return 0;
0085 }
0086
0087 static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
0088 {
0089     return sa1100_gpio_chip(chip)->irqbase + offset;
0090 }
0091
0092 static struct sa1100_gpio_chip sa1100_gpio_chip = {
0093     .chip = {
0094         .label          = "gpio",
0095         .get_direction      = sa1100_get_direction,
0096         .direction_input    = sa1100_direction_input,
0097         .direction_output   = sa1100_direction_output,
0098         .set            = sa1100_gpio_set,
0099         .get            = sa1100_gpio_get,
0100         .to_irq         = sa1100_to_irq,
0101         .base           = 0,
0102         .ngpio          = GPIO_MAX + 1,
0103     },
0104     .membase = (void *)&GPLR,
0105     .irqbase = IRQ_GPIO0,
0106 };
0107
0108 /*
0109  * SA1100 GPIO edge detection for IRQs:
0110  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
0111  * Use this instead of directly setting GRER/GFER.
0112  */
0113 static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc)
0114 {
0115     void *base = sgc->membase;
0116     u32 grer, gfer;
0117
0118     grer = sgc->irqrising & sgc->irqmask;
0119     gfer = sgc->irqfalling & sgc->irqmask;
0120
0121     writel_relaxed(grer, base + R_GRER);
0122     writel_relaxed(gfer, base + R_GFER);
0123 }
0124
0125 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
0126 {
0127     struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
0128     unsigned int mask = BIT(d->hwirq);
0129
0130     if (type == IRQ_TYPE_PROBE) {
0131         if ((sgc->irqrising | sgc->irqfalling) & mask)
0132             return 0;
0133         type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
0134     }
0135
0136     if (type & IRQ_TYPE_EDGE_RISING)
0137         sgc->irqrising |= mask;
0138     else
0139         sgc->irqrising &= ~mask;
0140     if (type & IRQ_TYPE_EDGE_FALLING)
0141         sgc->irqfalling |= mask;
0142     else
0143         sgc->irqfalling &= ~mask;
0144
0145     sa1100_update_edge_regs(sgc);
0146
0147     return 0;
0148 }
0149
0150 /*
0151  * GPIO IRQs must be acknowledged.
0152  */
0153 static void sa1100_gpio_ack(struct irq_data *d)
0154 {
0155     struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
0156
0157     writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
0158 }
0159
0160 static void sa1100_gpio_mask(struct irq_data *d)
0161 {
0162     struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
0163     unsigned int mask = BIT(d->hwirq);
0164
0165     sgc->irqmask &= ~mask;
0166
0167     sa1100_update_edge_regs(sgc);
0168 }
0169
0170 static void sa1100_gpio_unmask(struct irq_data *d)
0171 {
0172     struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
0173     unsigned int mask = BIT(d->hwirq);
0174
0175     sgc->irqmask |= mask;
0176
0177     sa1100_update_edge_regs(sgc);
0178 }
0179
0180 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
0181 {
0182     struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
0183     int ret = sa11x0_gpio_set_wake(d->hwirq, on);
0184     if (!ret) {
0185         if (on)
0186             sgc->irqwake |= BIT(d->hwirq);
0187         else
0188             sgc->irqwake &= ~BIT(d->hwirq);
0189     }
0190     return ret;
0191 }
0192
0193 /*
0194  * This is for GPIO IRQs
0195  */
0196 static struct irq_chip sa1100_gpio_irq_chip = {
0197     .name       = "GPIO",
0198     .irq_ack    = sa1100_gpio_ack,
0199     .irq_mask   = sa1100_gpio_mask,
0200     .irq_unmask = sa1100_gpio_unmask,
0201     .irq_set_type   = sa1100_gpio_type,
0202     .irq_set_wake   = sa1100_gpio_wake,
0203 };
0204
0205 static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
0206         unsigned int irq, irq_hw_number_t hwirq)
0207 {
0208     struct sa1100_gpio_chip *sgc = d->host_data;
0209
0210     irq_set_chip_data(irq, sgc);
0211     irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq);
0212     irq_set_probe(irq);
0213
0214     return 0;
0215 }
0216
0217 static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
0218     .map = sa1100_gpio_irqdomain_map,
0219     .xlate = irq_domain_xlate_onetwocell,
0220 };
0221
0222 static struct irq_domain *sa1100_gpio_irqdomain;
0223
0224 /*
0225  * IRQ 0-11 (GPIO) handler.  We enter here with the
0226  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
0227  * and call the handler.
0228  */
0229 static void sa1100_gpio_handler(struct irq_desc *desc)
0230 {
0231     struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc);
0232     unsigned int irq, mask;
0233     void __iomem *gedr = sgc->membase + R_GEDR;
0234
0235     mask = readl_relaxed(gedr);
0236     do {
0237         /*
0238          * clear down all currently active IRQ sources.
0239          * We will be processing them all.
0240          */
0241         writel_relaxed(mask, gedr);
0242
0243         irq = sgc->irqbase;
0244         do {
0245             if (mask & 1)
0246                 generic_handle_irq(irq);
0247             mask >>= 1;
0248             irq++;
0249         } while (mask);
0250
0251         mask = readl_relaxed(gedr);
0252     } while (mask);
0253 }
0254
0255 static int sa1100_gpio_suspend(void)
0256 {
0257     struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
0258
0259     /*
0260      * Set the appropriate edges for wakeup.
0261      */
0262     writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
0263     writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
0264
0265     /*
0266      * Clear any pending GPIO interrupts.
0267      */
0268     writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
0269                sgc->membase + R_GEDR);
0270
0271     return 0;
0272 }
0273
0274 static void sa1100_gpio_resume(void)
0275 {
0276     sa1100_update_edge_regs(&sa1100_gpio_chip);
0277 }
0278
0279 static struct syscore_ops sa1100_gpio_syscore_ops = {
0280     .suspend    = sa1100_gpio_suspend,
0281     .resume     = sa1100_gpio_resume,
0282 };
0283
0284 static int __init sa1100_gpio_init_devicefs(void)
0285 {
0286     register_syscore_ops(&sa1100_gpio_syscore_ops);
0287     return 0;
0288 }
0289
0290 device_initcall(sa1100_gpio_init_devicefs);
0291
0292 static const int sa1100_gpio_irqs[] __initconst = {
0293     /* Install handlers for GPIO 0-10 edge detect interrupts */
0294     IRQ_GPIO0_SC,
0295     IRQ_GPIO1_SC,
0296     IRQ_GPIO2_SC,
0297     IRQ_GPIO3_SC,
0298     IRQ_GPIO4_SC,
0299     IRQ_GPIO5_SC,
0300     IRQ_GPIO6_SC,
0301     IRQ_GPIO7_SC,
0302     IRQ_GPIO8_SC,
0303     IRQ_GPIO9_SC,
0304     IRQ_GPIO10_SC,
0305     /* Install handler for GPIO 11-27 edge detect interrupts */
0306     IRQ_GPIO11_27,
0307 };
0308
0309 void __init sa1100_init_gpio(void)
0310 {
0311     struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
0312     int i;
0313
0314     /* clear all GPIO edge detects */
0315     writel_relaxed(0, sgc->membase + R_GFER);
0316     writel_relaxed(0, sgc->membase + R_GRER);
0317     writel_relaxed(-1, sgc->membase + R_GEDR);
0318
0319     gpiochip_add_data(&sa1100_gpio_chip.chip, NULL);
0320
0321     sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
0322             28, IRQ_GPIO0,
0323             &sa1100_gpio_irqdomain_ops, sgc);
0324
0325     for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++)
0326         irq_set_chained_handler_and_data(sa1100_gpio_irqs[i],
0327                          sa1100_gpio_handler, sgc);
0328 }