Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 MundoReader S.L.
0004  * Author: Heiko Stuebner <heiko@sntech.de>
0005  *
0006  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
0007  */
0008 
0009 #include <linux/bitops.h>
0010 #include <linux/clk.h>
0011 #include <linux/device.h>
0012 #include <linux/err.h>
0013 #include <linux/gpio/driver.h>
0014 #include <linux/init.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <linux/of_device.h>
0021 #include <linux/of_irq.h>
0022 #include <linux/pinctrl/pinconf-generic.h>
0023 #include <linux/regmap.h>
0024 
0025 #include "../pinctrl/core.h"
0026 #include "../pinctrl/pinctrl-rockchip.h"
0027 
0028 #define GPIO_TYPE_V1        (0)           /* GPIO Version ID reserved */
0029 #define GPIO_TYPE_V2        (0x01000C2B)  /* GPIO Version ID 0x01000C2B */
0030 #define GPIO_TYPE_V2_1      (0x0101157C)  /* GPIO Version ID 0x0101157C */
0031 
0032 static const struct rockchip_gpio_regs gpio_regs_v1 = {
0033     .port_dr = 0x00,
0034     .port_ddr = 0x04,
0035     .int_en = 0x30,
0036     .int_mask = 0x34,
0037     .int_type = 0x38,
0038     .int_polarity = 0x3c,
0039     .int_status = 0x40,
0040     .int_rawstatus = 0x44,
0041     .debounce = 0x48,
0042     .port_eoi = 0x4c,
0043     .ext_port = 0x50,
0044 };
0045 
0046 static const struct rockchip_gpio_regs gpio_regs_v2 = {
0047     .port_dr = 0x00,
0048     .port_ddr = 0x08,
0049     .int_en = 0x10,
0050     .int_mask = 0x18,
0051     .int_type = 0x20,
0052     .int_polarity = 0x28,
0053     .int_bothedge = 0x30,
0054     .int_status = 0x50,
0055     .int_rawstatus = 0x58,
0056     .debounce = 0x38,
0057     .dbclk_div_en = 0x40,
0058     .dbclk_div_con = 0x48,
0059     .port_eoi = 0x60,
0060     .ext_port = 0x70,
0061     .version_id = 0x78,
0062 };
0063 
0064 static inline void gpio_writel_v2(u32 val, void __iomem *reg)
0065 {
0066     writel((val & 0xffff) | 0xffff0000, reg);
0067     writel((val >> 16) | 0xffff0000, reg + 0x4);
0068 }
0069 
0070 static inline u32 gpio_readl_v2(void __iomem *reg)
0071 {
0072     return readl(reg + 0x4) << 16 | readl(reg);
0073 }
0074 
0075 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
0076                     u32 value, unsigned int offset)
0077 {
0078     void __iomem *reg = bank->reg_base + offset;
0079 
0080     if (bank->gpio_type == GPIO_TYPE_V2)
0081         gpio_writel_v2(value, reg);
0082     else
0083         writel(value, reg);
0084 }
0085 
0086 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
0087                       unsigned int offset)
0088 {
0089     void __iomem *reg = bank->reg_base + offset;
0090     u32 value;
0091 
0092     if (bank->gpio_type == GPIO_TYPE_V2)
0093         value = gpio_readl_v2(reg);
0094     else
0095         value = readl(reg);
0096 
0097     return value;
0098 }
0099 
0100 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
0101                         u32 bit, u32 value,
0102                         unsigned int offset)
0103 {
0104     void __iomem *reg = bank->reg_base + offset;
0105     u32 data;
0106 
0107     if (bank->gpio_type == GPIO_TYPE_V2) {
0108         if (value)
0109             data = BIT(bit % 16) | BIT(bit % 16 + 16);
0110         else
0111             data = BIT(bit % 16 + 16);
0112         writel(data, bit >= 16 ? reg + 0x4 : reg);
0113     } else {
0114         data = readl(reg);
0115         data &= ~BIT(bit);
0116         if (value)
0117             data |= BIT(bit);
0118         writel(data, reg);
0119     }
0120 }
0121 
0122 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
0123                       u32 bit, unsigned int offset)
0124 {
0125     void __iomem *reg = bank->reg_base + offset;
0126     u32 data;
0127 
0128     if (bank->gpio_type == GPIO_TYPE_V2) {
0129         data = readl(bit >= 16 ? reg + 0x4 : reg);
0130         data >>= bit % 16;
0131     } else {
0132         data = readl(reg);
0133         data >>= bit;
0134     }
0135 
0136     return data & (0x1);
0137 }
0138 
0139 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
0140                        unsigned int offset)
0141 {
0142     struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
0143     u32 data;
0144 
0145     data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
0146     if (data)
0147         return GPIO_LINE_DIRECTION_OUT;
0148 
0149     return GPIO_LINE_DIRECTION_IN;
0150 }
0151 
0152 static int rockchip_gpio_set_direction(struct gpio_chip *chip,
0153                        unsigned int offset, bool input)
0154 {
0155     struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
0156     unsigned long flags;
0157     u32 data = input ? 0 : 1;
0158 
0159     raw_spin_lock_irqsave(&bank->slock, flags);
0160     rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
0161     raw_spin_unlock_irqrestore(&bank->slock, flags);
0162 
0163     return 0;
0164 }
0165 
0166 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
0167                   int value)
0168 {
0169     struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
0170     unsigned long flags;
0171 
0172     raw_spin_lock_irqsave(&bank->slock, flags);
0173     rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
0174     raw_spin_unlock_irqrestore(&bank->slock, flags);
0175 }
0176 
0177 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
0178 {
0179     struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
0180     u32 data;
0181 
0182     data = readl(bank->reg_base + bank->gpio_regs->ext_port);
0183     data >>= offset;
0184     data &= 1;
0185 
0186     return data;
0187 }
0188 
0189 static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
0190                       unsigned int offset,
0191                       unsigned int debounce)
0192 {
0193     struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
0194     const struct rockchip_gpio_regs *reg = bank->gpio_regs;
0195     unsigned long flags, div_reg, freq, max_debounce;
0196     bool div_debounce_support;
0197     unsigned int cur_div_reg;
0198     u64 div;
0199 
0200     if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
0201         div_debounce_support = true;
0202         freq = clk_get_rate(bank->db_clk);
0203         max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
0204         if (debounce > max_debounce)
0205             return -EINVAL;
0206 
0207         div = debounce * freq;
0208         div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
0209     } else {
0210         div_debounce_support = false;
0211     }
0212 
0213     raw_spin_lock_irqsave(&bank->slock, flags);
0214 
0215     /* Only the v1 needs to configure div_en and div_con for dbclk */
0216     if (debounce) {
0217         if (div_debounce_support) {
0218             /* Configure the max debounce from consumers */
0219             cur_div_reg = readl(bank->reg_base +
0220                         reg->dbclk_div_con);
0221             if (cur_div_reg < div_reg)
0222                 writel(div_reg, bank->reg_base +
0223                        reg->dbclk_div_con);
0224             rockchip_gpio_writel_bit(bank, offset, 1,
0225                          reg->dbclk_div_en);
0226         }
0227 
0228         rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
0229     } else {
0230         if (div_debounce_support)
0231             rockchip_gpio_writel_bit(bank, offset, 0,
0232                          reg->dbclk_div_en);
0233 
0234         rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
0235     }
0236 
0237     raw_spin_unlock_irqrestore(&bank->slock, flags);
0238 
0239     /* Enable or disable dbclk at last */
0240     if (div_debounce_support) {
0241         if (debounce)
0242             clk_prepare_enable(bank->db_clk);
0243         else
0244             clk_disable_unprepare(bank->db_clk);
0245     }
0246 
0247     return 0;
0248 }
0249 
0250 static int rockchip_gpio_direction_input(struct gpio_chip *gc,
0251                      unsigned int offset)
0252 {
0253     return rockchip_gpio_set_direction(gc, offset, true);
0254 }
0255 
0256 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
0257                       unsigned int offset, int value)
0258 {
0259     rockchip_gpio_set(gc, offset, value);
0260 
0261     return rockchip_gpio_set_direction(gc, offset, false);
0262 }
0263 
0264 /*
0265  * gpiolib set_config callback function. The setting of the pin
0266  * mux function as 'gpio output' will be handled by the pinctrl subsystem
0267  * interface.
0268  */
0269 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
0270                   unsigned long config)
0271 {
0272     enum pin_config_param param = pinconf_to_config_param(config);
0273 
0274     switch (param) {
0275     case PIN_CONFIG_INPUT_DEBOUNCE:
0276         rockchip_gpio_set_debounce(gc, offset, true);
0277         /*
0278          * Rockchip's gpio could only support up to one period
0279          * of the debounce clock(pclk), which is far away from
0280          * satisftying the requirement, as pclk is usually near
0281          * 100MHz shared by all peripherals. So the fact is it
0282          * has crippled debounce capability could only be useful
0283          * to prevent any spurious glitches from waking up the system
0284          * if the gpio is conguired as wakeup interrupt source. Let's
0285          * still return -ENOTSUPP as before, to make sure the caller
0286          * of gpiod_set_debounce won't change its behaviour.
0287          */
0288         return -ENOTSUPP;
0289     default:
0290         return -ENOTSUPP;
0291     }
0292 }
0293 
0294 /*
0295  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
0296  * and a virtual IRQ, if not already present.
0297  */
0298 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
0299 {
0300     struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
0301     unsigned int virq;
0302 
0303     if (!bank->domain)
0304         return -ENXIO;
0305 
0306     virq = irq_create_mapping(bank->domain, offset);
0307 
0308     return (virq) ? : -ENXIO;
0309 }
0310 
0311 static const struct gpio_chip rockchip_gpiolib_chip = {
0312     .request = gpiochip_generic_request,
0313     .free = gpiochip_generic_free,
0314     .set = rockchip_gpio_set,
0315     .get = rockchip_gpio_get,
0316     .get_direction  = rockchip_gpio_get_direction,
0317     .direction_input = rockchip_gpio_direction_input,
0318     .direction_output = rockchip_gpio_direction_output,
0319     .set_config = rockchip_gpio_set_config,
0320     .to_irq = rockchip_gpio_to_irq,
0321     .owner = THIS_MODULE,
0322 };
0323 
0324 static void rockchip_irq_demux(struct irq_desc *desc)
0325 {
0326     struct irq_chip *chip = irq_desc_get_chip(desc);
0327     struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
0328     u32 pend;
0329 
0330     dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
0331 
0332     chained_irq_enter(chip, desc);
0333 
0334     pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
0335 
0336     while (pend) {
0337         unsigned int irq, virq;
0338 
0339         irq = __ffs(pend);
0340         pend &= ~BIT(irq);
0341         virq = irq_find_mapping(bank->domain, irq);
0342 
0343         if (!virq) {
0344             dev_err(bank->dev, "unmapped irq %d\n", irq);
0345             continue;
0346         }
0347 
0348         dev_dbg(bank->dev, "handling irq %d\n", irq);
0349 
0350         /*
0351          * Triggering IRQ on both rising and falling edge
0352          * needs manual intervention.
0353          */
0354         if (bank->toggle_edge_mode & BIT(irq)) {
0355             u32 data, data_old, polarity;
0356             unsigned long flags;
0357 
0358             data = readl_relaxed(bank->reg_base +
0359                          bank->gpio_regs->ext_port);
0360             do {
0361                 raw_spin_lock_irqsave(&bank->slock, flags);
0362 
0363                 polarity = readl_relaxed(bank->reg_base +
0364                              bank->gpio_regs->int_polarity);
0365                 if (data & BIT(irq))
0366                     polarity &= ~BIT(irq);
0367                 else
0368                     polarity |= BIT(irq);
0369                 writel(polarity,
0370                        bank->reg_base +
0371                        bank->gpio_regs->int_polarity);
0372 
0373                 raw_spin_unlock_irqrestore(&bank->slock, flags);
0374 
0375                 data_old = data;
0376                 data = readl_relaxed(bank->reg_base +
0377                              bank->gpio_regs->ext_port);
0378             } while ((data & BIT(irq)) != (data_old & BIT(irq)));
0379         }
0380 
0381         generic_handle_irq(virq);
0382     }
0383 
0384     chained_irq_exit(chip, desc);
0385 }
0386 
0387 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
0388 {
0389     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0390     struct rockchip_pin_bank *bank = gc->private;
0391     u32 mask = BIT(d->hwirq);
0392     u32 polarity;
0393     u32 level;
0394     u32 data;
0395     unsigned long flags;
0396     int ret = 0;
0397 
0398     raw_spin_lock_irqsave(&bank->slock, flags);
0399 
0400     rockchip_gpio_writel_bit(bank, d->hwirq, 0,
0401                  bank->gpio_regs->port_ddr);
0402 
0403     raw_spin_unlock_irqrestore(&bank->slock, flags);
0404 
0405     if (type & IRQ_TYPE_EDGE_BOTH)
0406         irq_set_handler_locked(d, handle_edge_irq);
0407     else
0408         irq_set_handler_locked(d, handle_level_irq);
0409 
0410     raw_spin_lock_irqsave(&bank->slock, flags);
0411 
0412     level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
0413     polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
0414 
0415     if (type == IRQ_TYPE_EDGE_BOTH) {
0416         if (bank->gpio_type == GPIO_TYPE_V2) {
0417             rockchip_gpio_writel_bit(bank, d->hwirq, 1,
0418                          bank->gpio_regs->int_bothedge);
0419             goto out;
0420         } else {
0421             bank->toggle_edge_mode |= mask;
0422             level &= ~mask;
0423 
0424             /*
0425              * Determine gpio state. If 1 next interrupt should be
0426              * low otherwise high.
0427              */
0428             data = readl(bank->reg_base + bank->gpio_regs->ext_port);
0429             if (data & mask)
0430                 polarity &= ~mask;
0431             else
0432                 polarity |= mask;
0433         }
0434     } else {
0435         if (bank->gpio_type == GPIO_TYPE_V2) {
0436             rockchip_gpio_writel_bit(bank, d->hwirq, 0,
0437                          bank->gpio_regs->int_bothedge);
0438         } else {
0439             bank->toggle_edge_mode &= ~mask;
0440         }
0441         switch (type) {
0442         case IRQ_TYPE_EDGE_RISING:
0443             level |= mask;
0444             polarity |= mask;
0445             break;
0446         case IRQ_TYPE_EDGE_FALLING:
0447             level |= mask;
0448             polarity &= ~mask;
0449             break;
0450         case IRQ_TYPE_LEVEL_HIGH:
0451             level &= ~mask;
0452             polarity |= mask;
0453             break;
0454         case IRQ_TYPE_LEVEL_LOW:
0455             level &= ~mask;
0456             polarity &= ~mask;
0457             break;
0458         default:
0459             ret = -EINVAL;
0460             goto out;
0461         }
0462     }
0463 
0464     rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
0465     rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
0466 out:
0467     raw_spin_unlock_irqrestore(&bank->slock, flags);
0468 
0469     return ret;
0470 }
0471 
0472 static int rockchip_irq_reqres(struct irq_data *d)
0473 {
0474     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0475     struct rockchip_pin_bank *bank = gc->private;
0476 
0477     return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
0478 }
0479 
0480 static void rockchip_irq_relres(struct irq_data *d)
0481 {
0482     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0483     struct rockchip_pin_bank *bank = gc->private;
0484 
0485     gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
0486 }
0487 
0488 static void rockchip_irq_suspend(struct irq_data *d)
0489 {
0490     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0491     struct rockchip_pin_bank *bank = gc->private;
0492 
0493     bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
0494     irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
0495 }
0496 
0497 static void rockchip_irq_resume(struct irq_data *d)
0498 {
0499     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0500     struct rockchip_pin_bank *bank = gc->private;
0501 
0502     irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
0503 }
0504 
0505 static void rockchip_irq_enable(struct irq_data *d)
0506 {
0507     irq_gc_mask_clr_bit(d);
0508 }
0509 
0510 static void rockchip_irq_disable(struct irq_data *d)
0511 {
0512     irq_gc_mask_set_bit(d);
0513 }
0514 
0515 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
0516 {
0517     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
0518     struct irq_chip_generic *gc;
0519     int ret;
0520 
0521     bank->domain = irq_domain_add_linear(bank->of_node, 32,
0522                     &irq_generic_chip_ops, NULL);
0523     if (!bank->domain) {
0524         dev_warn(bank->dev, "could not init irq domain for bank %s\n",
0525              bank->name);
0526         return -EINVAL;
0527     }
0528 
0529     ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
0530                          "rockchip_gpio_irq",
0531                          handle_level_irq,
0532                          clr, 0, 0);
0533     if (ret) {
0534         dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
0535             bank->name);
0536         irq_domain_remove(bank->domain);
0537         return -EINVAL;
0538     }
0539 
0540     gc = irq_get_domain_generic_chip(bank->domain, 0);
0541     if (bank->gpio_type == GPIO_TYPE_V2) {
0542         gc->reg_writel = gpio_writel_v2;
0543         gc->reg_readl = gpio_readl_v2;
0544     }
0545 
0546     gc->reg_base = bank->reg_base;
0547     gc->private = bank;
0548     gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
0549     gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
0550     gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
0551     gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
0552     gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
0553     gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
0554     gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
0555     gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
0556     gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
0557     gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
0558     gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
0559     gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres;
0560     gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres;
0561     gc->wake_enabled = IRQ_MSK(bank->nr_pins);
0562 
0563     /*
0564      * Linux assumes that all interrupts start out disabled/masked.
0565      * Our driver only uses the concept of masked and always keeps
0566      * things enabled, so for us that's all masked and all enabled.
0567      */
0568     rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
0569     rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
0570     rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
0571     gc->mask_cache = 0xffffffff;
0572 
0573     irq_set_chained_handler_and_data(bank->irq,
0574                      rockchip_irq_demux, bank);
0575 
0576     return 0;
0577 }
0578 
0579 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
0580 {
0581     struct gpio_chip *gc;
0582     int ret;
0583 
0584     bank->gpio_chip = rockchip_gpiolib_chip;
0585 
0586     gc = &bank->gpio_chip;
0587     gc->base = bank->pin_base;
0588     gc->ngpio = bank->nr_pins;
0589     gc->label = bank->name;
0590     gc->parent = bank->dev;
0591 
0592     ret = gpiochip_add_data(gc, bank);
0593     if (ret) {
0594         dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
0595             gc->label, ret);
0596         return ret;
0597     }
0598 
0599     /*
0600      * For DeviceTree-supported systems, the gpio core checks the
0601      * pinctrl's device node for the "gpio-ranges" property.
0602      * If it is present, it takes care of adding the pin ranges
0603      * for the driver. In this case the driver can skip ahead.
0604      *
0605      * In order to remain compatible with older, existing DeviceTree
0606      * files which don't set the "gpio-ranges" property or systems that
0607      * utilize ACPI the driver has to call gpiochip_add_pin_range().
0608      */
0609     if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
0610         struct device_node *pctlnp = of_get_parent(bank->of_node);
0611         struct pinctrl_dev *pctldev = NULL;
0612 
0613         if (!pctlnp)
0614             return -ENODATA;
0615 
0616         pctldev = of_pinctrl_get(pctlnp);
0617         if (!pctldev)
0618             return -ENODEV;
0619 
0620         ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
0621                          gc->base, gc->ngpio);
0622         if (ret) {
0623             dev_err(bank->dev, "Failed to add pin range\n");
0624             goto fail;
0625         }
0626     }
0627 
0628     ret = rockchip_interrupts_register(bank);
0629     if (ret) {
0630         dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
0631         goto fail;
0632     }
0633 
0634     return 0;
0635 
0636 fail:
0637     gpiochip_remove(&bank->gpio_chip);
0638 
0639     return ret;
0640 }
0641 
0642 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
0643 {
0644     struct resource res;
0645     int id = 0;
0646 
0647     if (of_address_to_resource(bank->of_node, 0, &res)) {
0648         dev_err(bank->dev, "cannot find IO resource for bank\n");
0649         return -ENOENT;
0650     }
0651 
0652     bank->reg_base = devm_ioremap_resource(bank->dev, &res);
0653     if (IS_ERR(bank->reg_base))
0654         return PTR_ERR(bank->reg_base);
0655 
0656     bank->irq = irq_of_parse_and_map(bank->of_node, 0);
0657     if (!bank->irq)
0658         return -EINVAL;
0659 
0660     bank->clk = of_clk_get(bank->of_node, 0);
0661     if (IS_ERR(bank->clk))
0662         return PTR_ERR(bank->clk);
0663 
0664     clk_prepare_enable(bank->clk);
0665     id = readl(bank->reg_base + gpio_regs_v2.version_id);
0666 
0667     /* If not gpio v2, that is default to v1. */
0668     if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
0669         bank->gpio_regs = &gpio_regs_v2;
0670         bank->gpio_type = GPIO_TYPE_V2;
0671         bank->db_clk = of_clk_get(bank->of_node, 1);
0672         if (IS_ERR(bank->db_clk)) {
0673             dev_err(bank->dev, "cannot find debounce clk\n");
0674             clk_disable_unprepare(bank->clk);
0675             return -EINVAL;
0676         }
0677     } else {
0678         bank->gpio_regs = &gpio_regs_v1;
0679         bank->gpio_type = GPIO_TYPE_V1;
0680     }
0681 
0682     return 0;
0683 }
0684 
0685 static struct rockchip_pin_bank *
0686 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
0687 {
0688     struct rockchip_pinctrl *info;
0689     struct rockchip_pin_bank *bank;
0690     int i, found = 0;
0691 
0692     info = pinctrl_dev_get_drvdata(pctldev);
0693     bank = info->ctrl->pin_banks;
0694     for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
0695         if (bank->bank_num == id) {
0696             found = 1;
0697             break;
0698         }
0699     }
0700 
0701     return found ? bank : NULL;
0702 }
0703 
0704 static int rockchip_gpio_probe(struct platform_device *pdev)
0705 {
0706     struct device *dev = &pdev->dev;
0707     struct device_node *np = dev->of_node;
0708     struct device_node *pctlnp = of_get_parent(np);
0709     struct pinctrl_dev *pctldev = NULL;
0710     struct rockchip_pin_bank *bank = NULL;
0711     struct rockchip_pin_deferred *cfg;
0712     static int gpio;
0713     int id, ret;
0714 
0715     if (!np || !pctlnp)
0716         return -ENODEV;
0717 
0718     pctldev = of_pinctrl_get(pctlnp);
0719     if (!pctldev)
0720         return -EPROBE_DEFER;
0721 
0722     id = of_alias_get_id(np, "gpio");
0723     if (id < 0)
0724         id = gpio++;
0725 
0726     bank = rockchip_gpio_find_bank(pctldev, id);
0727     if (!bank)
0728         return -EINVAL;
0729 
0730     bank->dev = dev;
0731     bank->of_node = np;
0732 
0733     raw_spin_lock_init(&bank->slock);
0734 
0735     ret = rockchip_get_bank_data(bank);
0736     if (ret)
0737         return ret;
0738 
0739     /*
0740      * Prevent clashes with a deferred output setting
0741      * being added right at this moment.
0742      */
0743     mutex_lock(&bank->deferred_lock);
0744 
0745     ret = rockchip_gpiolib_register(bank);
0746     if (ret) {
0747         clk_disable_unprepare(bank->clk);
0748         mutex_unlock(&bank->deferred_lock);
0749         return ret;
0750     }
0751 
0752     while (!list_empty(&bank->deferred_pins)) {
0753         cfg = list_first_entry(&bank->deferred_pins,
0754                        struct rockchip_pin_deferred, head);
0755         list_del(&cfg->head);
0756 
0757         switch (cfg->param) {
0758         case PIN_CONFIG_OUTPUT:
0759             ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
0760             if (ret)
0761                 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
0762                      cfg->arg);
0763             break;
0764         case PIN_CONFIG_INPUT_ENABLE:
0765             ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);
0766             if (ret)
0767                 dev_warn(dev, "setting input pin %u failed\n", cfg->pin);
0768             break;
0769         default:
0770             dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
0771             break;
0772         }
0773         kfree(cfg);
0774     }
0775 
0776     mutex_unlock(&bank->deferred_lock);
0777 
0778     platform_set_drvdata(pdev, bank);
0779     dev_info(dev, "probed %pOF\n", np);
0780 
0781     return 0;
0782 }
0783 
0784 static int rockchip_gpio_remove(struct platform_device *pdev)
0785 {
0786     struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
0787 
0788     clk_disable_unprepare(bank->clk);
0789     gpiochip_remove(&bank->gpio_chip);
0790 
0791     return 0;
0792 }
0793 
0794 static const struct of_device_id rockchip_gpio_match[] = {
0795     { .compatible = "rockchip,gpio-bank", },
0796     { .compatible = "rockchip,rk3188-gpio-bank0" },
0797     { },
0798 };
0799 
0800 static struct platform_driver rockchip_gpio_driver = {
0801     .probe      = rockchip_gpio_probe,
0802     .remove     = rockchip_gpio_remove,
0803     .driver     = {
0804         .name   = "rockchip-gpio",
0805         .of_match_table = rockchip_gpio_match,
0806     },
0807 };
0808 
0809 static int __init rockchip_gpio_init(void)
0810 {
0811     return platform_driver_register(&rockchip_gpio_driver);
0812 }
0813 postcore_initcall(rockchip_gpio_init);
0814 
0815 static void __exit rockchip_gpio_exit(void)
0816 {
0817     platform_driver_unregister(&rockchip_gpio_driver);
0818 }
0819 module_exit(rockchip_gpio_exit);
0820 
0821 MODULE_DESCRIPTION("Rockchip gpio driver");
0822 MODULE_ALIAS("platform:rockchip-gpio");
0823 MODULE_LICENSE("GPL v2");
0824 MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!