drivers/gpio/gpio-reg.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * gpio-reg: single register individually fixed-direction GPIOs
0004  *
0005  * Copyright (C) 2016 Russell King
0006  */
0007 #include <linux/gpio/driver.h>
0008 #include <linux/gpio/gpio-reg.h>
0009 #include <linux/io.h>
0010 #include <linux/slab.h>
0011 #include <linux/spinlock.h>
0012
0013 struct gpio_reg {
0014     struct gpio_chip gc;
0015     spinlock_t lock;
0016     u32 direction;
0017     u32 out;
0018     void __iomem *reg;
0019     struct irq_domain *irqdomain;
0020     const int *irqs;
0021 };
0022
0023 #define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
0024
0025 static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
0026 {
0027     struct gpio_reg *r = to_gpio_reg(gc);
0028
0029     return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN :
0030                         GPIO_LINE_DIRECTION_OUT;
0031 }
0032
0033 static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
0034     int value)
0035 {
0036     struct gpio_reg *r = to_gpio_reg(gc);
0037
0038     if (r->direction & BIT(offset))
0039         return -ENOTSUPP;
0040
0041     gc->set(gc, offset, value);
0042     return 0;
0043 }
0044
0045 static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
0046 {
0047     struct gpio_reg *r = to_gpio_reg(gc);
0048
0049     return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
0050 }
0051
0052 static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
0053 {
0054     struct gpio_reg *r = to_gpio_reg(gc);
0055     unsigned long flags;
0056     u32 val, mask = BIT(offset);
0057
0058     spin_lock_irqsave(&r->lock, flags);
0059     val = r->out;
0060     if (value)
0061         val |= mask;
0062     else
0063         val &= ~mask;
0064     r->out = val;
0065     writel_relaxed(val, r->reg);
0066     spin_unlock_irqrestore(&r->lock, flags);
0067 }
0068
0069 static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
0070 {
0071     struct gpio_reg *r = to_gpio_reg(gc);
0072     u32 val, mask = BIT(offset);
0073
0074     if (r->direction & mask) {
0075         /*
0076          * double-read the value, some registers latch after the
0077          * first read.
0078          */
0079         readl_relaxed(r->reg);
0080         val = readl_relaxed(r->reg);
0081     } else {
0082         val = r->out;
0083     }
0084     return !!(val & mask);
0085 }
0086
0087 static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
0088     unsigned long *bits)
0089 {
0090     struct gpio_reg *r = to_gpio_reg(gc);
0091     unsigned long flags;
0092
0093     spin_lock_irqsave(&r->lock, flags);
0094     r->out = (r->out & ~*mask) | (*bits & *mask);
0095     writel_relaxed(r->out, r->reg);
0096     spin_unlock_irqrestore(&r->lock, flags);
0097 }
0098
0099 static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
0100 {
0101     struct gpio_reg *r = to_gpio_reg(gc);
0102     int irq = r->irqs[offset];
0103
0104     if (irq >= 0 && r->irqdomain)
0105         irq = irq_find_mapping(r->irqdomain, irq);
0106
0107     return irq;
0108 }
0109
0110 /**
0111  * gpio_reg_init - add a fixed in/out register as gpio
0112  * @dev: optional struct device associated with this register
0113  * @base: start gpio number, or -1 to allocate
0114  * @num: number of GPIOs, maximum 32
0115  * @label: GPIO chip label
0116  * @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
0117  * @def_out: initial GPIO output value
0118  * @names: array of %num strings describing each GPIO signal or %NULL
0119  * @irqdom: irq domain or %NULL
0120  * @irqs: array of %num ints describing the interrupt mapping for each
0121  *        GPIO signal, or %NULL.  If @irqdom is %NULL, then this
0122  *        describes the Linux interrupt number, otherwise it describes
0123  *        the hardware interrupt number in the specified irq domain.
0124  *
0125  * Add a single-register GPIO device containing up to 32 GPIO signals,
0126  * where each GPIO has a fixed input or output configuration.  Only
0127  * input GPIOs are assumed to be readable from the register, and only
0128  * then after a double-read.  Output values are assumed not to be
0129  * readable.
0130  */
0131 struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
0132     int base, int num, const char *label, u32 direction, u32 def_out,
0133     const char *const *names, struct irq_domain *irqdom, const int *irqs)
0134 {
0135     struct gpio_reg *r;
0136     int ret;
0137
0138     if (dev)
0139         r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
0140     else
0141         r = kzalloc(sizeof(*r), GFP_KERNEL);
0142
0143     if (!r)
0144         return ERR_PTR(-ENOMEM);
0145
0146     spin_lock_init(&r->lock);
0147
0148     r->gc.label = label;
0149     r->gc.get_direction = gpio_reg_get_direction;
0150     r->gc.direction_input = gpio_reg_direction_input;
0151     r->gc.direction_output = gpio_reg_direction_output;
0152     r->gc.set = gpio_reg_set;
0153     r->gc.get = gpio_reg_get;
0154     r->gc.set_multiple = gpio_reg_set_multiple;
0155     if (irqs)
0156         r->gc.to_irq = gpio_reg_to_irq;
0157     r->gc.base = base;
0158     r->gc.ngpio = num;
0159     r->gc.names = names;
0160     r->direction = direction;
0161     r->out = def_out;
0162     r->reg = reg;
0163     r->irqs = irqs;
0164
0165     if (dev)
0166         ret = devm_gpiochip_add_data(dev, &r->gc, r);
0167     else
0168         ret = gpiochip_add_data(&r->gc, r);
0169
0170     return ret ? ERR_PTR(ret) : &r->gc;
0171 }
0172
0173 int gpio_reg_resume(struct gpio_chip *gc)
0174 {
0175     struct gpio_reg *r = to_gpio_reg(gc);
0176     unsigned long flags;
0177
0178     spin_lock_irqsave(&r->lock, flags);
0179     writel_relaxed(r->out, r->reg);
0180     spin_unlock_irqrestore(&r->lock, flags);
0181
0182     return 0;
0183 }