drivers/gpio/gpio-realtek-otto.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 #include <linux/gpio/driver.h>
0004 #include <linux/cpumask.h>
0005 #include <linux/irq.h>
0006 #include <linux/minmax.h>
0007 #include <linux/mod_devicetable.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/property.h>
0011
0012 /*
0013  * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
0014  * An optional second bank, with ports E, F, G, and H, may be present, starting
0015  * at register offset 0x1C.
0016  */
0017
0018 /*
0019  * Pin select: (0) "normal", (1) "dedicate peripheral"
0020  * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits
0021  * in the peripheral registers.
0022  */
0023 #define REALTEK_GPIO_REG_CNR        0x00
0024 /* Clear bit (0) for input, set bit (1) for output */
0025 #define REALTEK_GPIO_REG_DIR        0x08
0026 #define REALTEK_GPIO_REG_DATA       0x0C
0027 /* Read bit for IRQ status, write 1 to clear IRQ */
0028 #define REALTEK_GPIO_REG_ISR        0x10
0029 /* Two bits per GPIO in IMR registers */
0030 #define REALTEK_GPIO_REG_IMR        0x14
0031 #define REALTEK_GPIO_REG_IMR_AB     0x14
0032 #define REALTEK_GPIO_REG_IMR_CD     0x18
0033 #define REALTEK_GPIO_IMR_LINE_MASK  GENMASK(1, 0)
0034 #define REALTEK_GPIO_IRQ_EDGE_FALLING   1
0035 #define REALTEK_GPIO_IRQ_EDGE_RISING    2
0036 #define REALTEK_GPIO_IRQ_EDGE_BOTH  3
0037
0038 #define REALTEK_GPIO_MAX        32
0039 #define REALTEK_GPIO_PORTS_PER_BANK 4
0040
0041 /**
0042  * realtek_gpio_ctrl - Realtek Otto GPIO driver data
0043  *
0044  * @gc: Associated gpio_chip instance
0045  * @base: Base address of the register block for a GPIO bank
0046  * @lock: Lock for accessing the IRQ registers and values
0047  * @intr_mask: Mask for interrupts lines
0048  * @intr_type: Interrupt type selection
0049  * @bank_read: Read a bank setting as a single 32-bit value
0050  * @bank_write: Write a bank setting as a single 32-bit value
0051  * @imr_line_pos: Bit shift of an IRQ line's IMR value.
0052  *
0053  * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
0054  * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
0055  * a value from (to) these registers. The IMR register consists of four 16-bit
0056  * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
0057  * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
0058  * 32 overflow into the second register.
0059  *
0060  * Because the interrupt mask register (IMR) combines the function of IRQ type
0061  * selection and masking, two extra values are stored. @intr_mask is used to
0062  * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store
0063  * the selected interrupt types. The logical AND of these values is written to
0064  * IMR on changes.
0065  */
0066 struct realtek_gpio_ctrl {
0067     struct gpio_chip gc;
0068     void __iomem *base;
0069     void __iomem *cpumask_base;
0070     struct cpumask cpu_irq_maskable;
0071     raw_spinlock_t lock;
0072     u8 intr_mask[REALTEK_GPIO_MAX];
0073     u8 intr_type[REALTEK_GPIO_MAX];
0074     u32 (*bank_read)(void __iomem *reg);
0075     void (*bank_write)(void __iomem *reg, u32 value);
0076     unsigned int (*line_imr_pos)(unsigned int line);
0077 };
0078
0079 /* Expand with more flags as devices with other quirks are added */
0080 enum realtek_gpio_flags {
0081     /*
0082      * Allow disabling interrupts, for cases where the port order is
0083      * unknown. This may result in a port mismatch between ISR and IMR.
0084      * An interrupt would appear to come from a different line than the
0085      * line the IRQ handler was assigned to, causing uncaught interrupts.
0086      */
0087     GPIO_INTERRUPTS_DISABLED = BIT(0),
0088     /*
0089      * Port order is reversed, meaning DCBA register layout for 1-bit
0090      * fields, and [BA, DC] for 2-bit fields.
0091      */
0092     GPIO_PORTS_REVERSED = BIT(1),
0093     /*
0094      * Interrupts can be enabled per cpu. This requires a secondary IO
0095      * range, where the per-cpu enable masks are located.
0096      */
0097     GPIO_INTERRUPTS_PER_CPU = BIT(2),
0098 };
0099
0100 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
0101 {
0102     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0103
0104     return container_of(gc, struct realtek_gpio_ctrl, gc);
0105 }
0106
0107 /*
0108  * Normal port order register access
0109  *
0110  * Port information is stored with the first port at offset 0, followed by the
0111  * second, etc. Most registers store one bit per GPIO and use a u8 value per
0112  * port. The two interrupt mask registers store two bits per GPIO, so use u16
0113  * values.
0114  */
0115 static u32 realtek_gpio_bank_read_swapped(void __iomem *reg)
0116 {
0117     return ioread32be(reg);
0118 }
0119
0120 static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value)
0121 {
0122     iowrite32be(value, reg);
0123 }
0124
0125 static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line)
0126 {
0127     unsigned int port_pin = line % 8;
0128     unsigned int port = line / 8;
0129
0130     return 2 * (8 * (port ^ 1) + port_pin);
0131 }
0132
0133 /*
0134  * Reversed port order register access
0135  *
0136  * For registers with one bit per GPIO, all ports are stored as u8-s in one
0137  * register in reversed order. The two interrupt mask registers store two bits
0138  * per GPIO, so use u16 values. The first register contains ports 1 and 0, the
0139  * second ports 3 and 2.
0140  */
0141 static u32 realtek_gpio_bank_read(void __iomem *reg)
0142 {
0143     return ioread32(reg);
0144 }
0145
0146 static void realtek_gpio_bank_write(void __iomem *reg, u32 value)
0147 {
0148     iowrite32(value, reg);
0149 }
0150
0151 static unsigned int realtek_gpio_line_imr_pos(unsigned int line)
0152 {
0153     return 2 * line;
0154 }
0155
0156 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask)
0157 {
0158     ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask);
0159 }
0160
0161 static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl)
0162 {
0163     return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR);
0164 }
0165
0166 /* Set the rising and falling edge mask bits for a GPIO pin */
0167 static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line)
0168 {
0169     void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR;
0170     unsigned int line_shift = ctrl->line_imr_pos(line);
0171     unsigned int shift = line_shift % 32;
0172     u32 irq_type = ctrl->intr_type[line];
0173     u32 irq_mask = ctrl->intr_mask[line];
0174     u32 reg_val;
0175
0176     reg += 4 * (line_shift / 32);
0177     reg_val = ioread32(reg);
0178     reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift);
0179     reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift;
0180     iowrite32(reg_val, reg);
0181 }
0182
0183 static void realtek_gpio_irq_ack(struct irq_data *data)
0184 {
0185     struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
0186     irq_hw_number_t line = irqd_to_hwirq(data);
0187
0188     realtek_gpio_clear_isr(ctrl, BIT(line));
0189 }
0190
0191 static void realtek_gpio_irq_unmask(struct irq_data *data)
0192 {
0193     struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
0194     unsigned int line = irqd_to_hwirq(data);
0195     unsigned long flags;
0196
0197     gpiochip_enable_irq(&ctrl->gc, line);
0198
0199     raw_spin_lock_irqsave(&ctrl->lock, flags);
0200     ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK;
0201     realtek_gpio_update_line_imr(ctrl, line);
0202     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0203 }
0204
0205 static void realtek_gpio_irq_mask(struct irq_data *data)
0206 {
0207     struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
0208     unsigned int line = irqd_to_hwirq(data);
0209     unsigned long flags;
0210
0211     raw_spin_lock_irqsave(&ctrl->lock, flags);
0212     ctrl->intr_mask[line] = 0;
0213     realtek_gpio_update_line_imr(ctrl, line);
0214     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0215
0216     gpiochip_disable_irq(&ctrl->gc, line);
0217 }
0218
0219 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
0220 {
0221     struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
0222     unsigned int line = irqd_to_hwirq(data);
0223     unsigned long flags;
0224     u8 type;
0225
0226     switch (flow_type & IRQ_TYPE_SENSE_MASK) {
0227     case IRQ_TYPE_EDGE_FALLING:
0228         type = REALTEK_GPIO_IRQ_EDGE_FALLING;
0229         break;
0230     case IRQ_TYPE_EDGE_RISING:
0231         type = REALTEK_GPIO_IRQ_EDGE_RISING;
0232         break;
0233     case IRQ_TYPE_EDGE_BOTH:
0234         type = REALTEK_GPIO_IRQ_EDGE_BOTH;
0235         break;
0236     default:
0237         return -EINVAL;
0238     }
0239
0240     irq_set_handler_locked(data, handle_edge_irq);
0241
0242     raw_spin_lock_irqsave(&ctrl->lock, flags);
0243     ctrl->intr_type[line] = type;
0244     realtek_gpio_update_line_imr(ctrl, line);
0245     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0246
0247     return 0;
0248 }
0249
0250 static void realtek_gpio_irq_handler(struct irq_desc *desc)
0251 {
0252     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0253     struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
0254     struct irq_chip *irq_chip = irq_desc_get_chip(desc);
0255     unsigned long status;
0256     int offset;
0257
0258     chained_irq_enter(irq_chip, desc);
0259
0260     status = realtek_gpio_read_isr(ctrl);
0261     for_each_set_bit(offset, &status, gc->ngpio)
0262         generic_handle_domain_irq(gc->irq.domain, offset);
0263
0264     chained_irq_exit(irq_chip, desc);
0265 }
0266
0267 static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu)
0268 {
0269     return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu;
0270 }
0271
0272 static int realtek_gpio_irq_set_affinity(struct irq_data *data,
0273     const struct cpumask *dest, bool force)
0274 {
0275     struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
0276     unsigned int line = irqd_to_hwirq(data);
0277     void __iomem *irq_cpu_mask;
0278     unsigned long flags;
0279     int cpu;
0280     u32 v;
0281
0282     if (!ctrl->cpumask_base)
0283         return -ENXIO;
0284
0285     raw_spin_lock_irqsave(&ctrl->lock, flags);
0286
0287     for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {
0288         irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu);
0289         v = ctrl->bank_read(irq_cpu_mask);
0290
0291         if (cpumask_test_cpu(cpu, dest))
0292             v |= BIT(line);
0293         else
0294             v &= ~BIT(line);
0295
0296         ctrl->bank_write(irq_cpu_mask, v);
0297     }
0298
0299     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0300
0301     irq_data_update_effective_affinity(data, dest);
0302
0303     return 0;
0304 }
0305
0306 static int realtek_gpio_irq_init(struct gpio_chip *gc)
0307 {
0308     struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
0309     u32 mask_all = GENMASK(gc->ngpio - 1, 0);
0310     unsigned int line;
0311     int cpu;
0312
0313     for (line = 0; line < gc->ngpio; line++)
0314         realtek_gpio_update_line_imr(ctrl, line);
0315
0316     realtek_gpio_clear_isr(ctrl, mask_all);
0317
0318     for_each_cpu(cpu, &ctrl->cpu_irq_maskable)
0319         ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all);
0320
0321     return 0;
0322 }
0323
0324 static const struct irq_chip realtek_gpio_irq_chip = {
0325     .name = "realtek-otto-gpio",
0326     .irq_ack = realtek_gpio_irq_ack,
0327     .irq_mask = realtek_gpio_irq_mask,
0328     .irq_unmask = realtek_gpio_irq_unmask,
0329     .irq_set_type = realtek_gpio_irq_set_type,
0330     .irq_set_affinity = realtek_gpio_irq_set_affinity,
0331     .flags = IRQCHIP_IMMUTABLE,
0332     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0333 };
0334
0335 static const struct of_device_id realtek_gpio_of_match[] = {
0336     {
0337         .compatible = "realtek,otto-gpio",
0338         .data = (void *)GPIO_INTERRUPTS_DISABLED,
0339     },
0340     {
0341         .compatible = "realtek,rtl8380-gpio",
0342     },
0343     {
0344         .compatible = "realtek,rtl8390-gpio",
0345     },
0346     {
0347         .compatible = "realtek,rtl9300-gpio",
0348         .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
0349     },
0350     {
0351         .compatible = "realtek,rtl9310-gpio",
0352     },
0353     {}
0354 };
0355 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
0356
0357 static int realtek_gpio_probe(struct platform_device *pdev)
0358 {
0359     struct device *dev = &pdev->dev;
0360     unsigned long bgpio_flags;
0361     unsigned int dev_flags;
0362     struct gpio_irq_chip *girq;
0363     struct realtek_gpio_ctrl *ctrl;
0364     struct resource *res;
0365     u32 ngpios;
0366     unsigned int nr_cpus;
0367     int cpu, err, irq;
0368
0369     ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
0370     if (!ctrl)
0371         return -ENOMEM;
0372
0373     dev_flags = (unsigned int) device_get_match_data(dev);
0374
0375     ngpios = REALTEK_GPIO_MAX;
0376     device_property_read_u32(dev, "ngpios", &ngpios);
0377
0378     if (ngpios > REALTEK_GPIO_MAX) {
0379         dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",
0380             REALTEK_GPIO_MAX);
0381         return -EINVAL;
0382     }
0383
0384     ctrl->base = devm_platform_ioremap_resource(pdev, 0);
0385     if (IS_ERR(ctrl->base))
0386         return PTR_ERR(ctrl->base);
0387
0388     raw_spin_lock_init(&ctrl->lock);
0389
0390     if (dev_flags & GPIO_PORTS_REVERSED) {
0391         bgpio_flags = 0;
0392         ctrl->bank_read = realtek_gpio_bank_read;
0393         ctrl->bank_write = realtek_gpio_bank_write;
0394         ctrl->line_imr_pos = realtek_gpio_line_imr_pos;
0395     } else {
0396         bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
0397         ctrl->bank_read = realtek_gpio_bank_read_swapped;
0398         ctrl->bank_write = realtek_gpio_bank_write_swapped;
0399         ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped;
0400     }
0401
0402     err = bgpio_init(&ctrl->gc, dev, 4,
0403         ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,
0404         ctrl->base + REALTEK_GPIO_REG_DIR, NULL,
0405         bgpio_flags);
0406     if (err) {
0407         dev_err(dev, "unable to init generic GPIO");
0408         return err;
0409     }
0410
0411     ctrl->gc.ngpio = ngpios;
0412     ctrl->gc.owner = THIS_MODULE;
0413
0414     irq = platform_get_irq_optional(pdev, 0);
0415     if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
0416         girq = &ctrl->gc.irq;
0417         gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip);
0418         girq->default_type = IRQ_TYPE_NONE;
0419         girq->handler = handle_bad_irq;
0420         girq->parent_handler = realtek_gpio_irq_handler;
0421         girq->num_parents = 1;
0422         girq->parents = devm_kcalloc(dev, girq->num_parents,
0423                     sizeof(*girq->parents), GFP_KERNEL);
0424         if (!girq->parents)
0425             return -ENOMEM;
0426         girq->parents[0] = irq;
0427         girq->init_hw = realtek_gpio_irq_init;
0428     }
0429
0430     cpumask_clear(&ctrl->cpu_irq_maskable);
0431
0432     if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) {
0433         ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
0434         if (IS_ERR(ctrl->cpumask_base))
0435             return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),
0436                 "missing CPU IRQ mask registers");
0437
0438         nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK;
0439         nr_cpus = min(nr_cpus, num_present_cpus());
0440
0441         for (cpu = 0; cpu < nr_cpus; cpu++)
0442             cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);
0443     }
0444
0445     return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
0446 }
0447
0448 static struct platform_driver realtek_gpio_driver = {
0449     .driver = {
0450         .name = "realtek-otto-gpio",
0451         .of_match_table = realtek_gpio_of_match,
0452     },
0453     .probe = realtek_gpio_probe,
0454 };
0455 module_platform_driver(realtek_gpio_driver);
0456
0457 MODULE_DESCRIPTION("Realtek Otto GPIO support");
0458 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
0459 MODULE_LICENSE("GPL v2");