drivers/gpio/gpio-rda.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * RDA Micro GPIO driver
0004  *
0005  * Copyright (C) 2012 RDA Micro Inc.
0006  * Copyright (C) 2019 Manivannan Sadhasivam
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spinlock.h>
0015
0016 #define RDA_GPIO_OEN_VAL        0x00
0017 #define RDA_GPIO_OEN_SET_OUT        0x04
0018 #define RDA_GPIO_OEN_SET_IN     0x08
0019 #define RDA_GPIO_VAL            0x0c
0020 #define RDA_GPIO_SET            0x10
0021 #define RDA_GPIO_CLR            0x14
0022 #define RDA_GPIO_INT_CTRL_SET       0x18
0023 #define RDA_GPIO_INT_CTRL_CLR       0x1c
0024 #define RDA_GPIO_INT_CLR        0x20
0025 #define RDA_GPIO_INT_STATUS     0x24
0026
0027 #define RDA_GPIO_IRQ_RISE_SHIFT     0
0028 #define RDA_GPIO_IRQ_FALL_SHIFT     8
0029 #define RDA_GPIO_DEBOUCE_SHIFT      16
0030 #define RDA_GPIO_LEVEL_SHIFT        24
0031
0032 #define RDA_GPIO_IRQ_MASK       0xff
0033
0034 /* Each bank consists of 32 GPIOs */
0035 #define RDA_GPIO_BANK_NR    32
0036
0037 struct rda_gpio {
0038     struct gpio_chip chip;
0039     void __iomem *base;
0040     spinlock_t lock;
0041     struct irq_chip irq_chip;
0042     int irq;
0043 };
0044
0045 static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset,
0046                    u16 reg, int val)
0047 {
0048     struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
0049     void __iomem *base = rda_gpio->base;
0050     unsigned long flags;
0051     u32 tmp;
0052
0053     spin_lock_irqsave(&rda_gpio->lock, flags);
0054     tmp = readl_relaxed(base + reg);
0055
0056     if (val)
0057         tmp |= BIT(offset);
0058     else
0059         tmp &= ~BIT(offset);
0060
0061     writel_relaxed(tmp, base + reg);
0062     spin_unlock_irqrestore(&rda_gpio->lock, flags);
0063 }
0064
0065 static void rda_gpio_irq_mask(struct irq_data *data)
0066 {
0067     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0068     struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
0069     void __iomem *base = rda_gpio->base;
0070     u32 offset = irqd_to_hwirq(data);
0071     u32 value;
0072
0073     value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
0074     value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
0075
0076     writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
0077 }
0078
0079 static void rda_gpio_irq_ack(struct irq_data *data)
0080 {
0081     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0082     u32 offset = irqd_to_hwirq(data);
0083
0084     rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1);
0085 }
0086
0087 static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset,
0088                 unsigned int flow_type)
0089 {
0090     struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
0091     void __iomem *base = rda_gpio->base;
0092     u32 value;
0093
0094     switch (flow_type) {
0095     case IRQ_TYPE_EDGE_RISING:
0096         /* Set rising edge trigger */
0097         value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
0098         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
0099
0100         /* Switch to edge trigger interrupt */
0101         value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
0102         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
0103         break;
0104
0105     case IRQ_TYPE_EDGE_FALLING:
0106         /* Set falling edge trigger */
0107         value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
0108         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
0109
0110         /* Switch to edge trigger interrupt */
0111         value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
0112         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
0113         break;
0114
0115     case IRQ_TYPE_EDGE_BOTH:
0116         /* Set both edge trigger */
0117         value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
0118         value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
0119         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
0120
0121         /* Switch to edge trigger interrupt */
0122         value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
0123         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
0124         break;
0125
0126     case IRQ_TYPE_LEVEL_HIGH:
0127         /* Set high level trigger */
0128         value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
0129
0130         /* Switch to level trigger interrupt */
0131         value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
0132         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
0133         break;
0134
0135     case IRQ_TYPE_LEVEL_LOW:
0136         /* Set low level trigger */
0137         value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
0138
0139         /* Switch to level trigger interrupt */
0140         value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
0141         writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
0142         break;
0143
0144     default:
0145         return -EINVAL;
0146     }
0147
0148     return 0;
0149 }
0150
0151 static void rda_gpio_irq_unmask(struct irq_data *data)
0152 {
0153     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0154     u32 offset = irqd_to_hwirq(data);
0155     u32 trigger = irqd_get_trigger_type(data);
0156
0157     rda_gpio_set_irq(chip, offset, trigger);
0158 }
0159
0160 static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
0161 {
0162     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0163     u32 offset = irqd_to_hwirq(data);
0164     int ret;
0165
0166     ret = rda_gpio_set_irq(chip, offset, flow_type);
0167     if (ret)
0168         return ret;
0169
0170     if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
0171         irq_set_handler_locked(data, handle_level_irq);
0172     else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0173         irq_set_handler_locked(data, handle_edge_irq);
0174
0175     return 0;
0176 }
0177
0178 static void rda_gpio_irq_handler(struct irq_desc *desc)
0179 {
0180     struct gpio_chip *chip = irq_desc_get_handler_data(desc);
0181     struct irq_chip *ic = irq_desc_get_chip(desc);
0182     struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
0183     unsigned long status;
0184     u32 n;
0185
0186     chained_irq_enter(ic, desc);
0187
0188     status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS);
0189     /* Only lower 8 bits are capable of generating interrupts */
0190     status &= RDA_GPIO_IRQ_MASK;
0191
0192     for_each_set_bit(n, &status, RDA_GPIO_BANK_NR)
0193         generic_handle_domain_irq(chip->irq.domain, n);
0194
0195     chained_irq_exit(ic, desc);
0196 }
0197
0198 static int rda_gpio_probe(struct platform_device *pdev)
0199 {
0200     struct device *dev = &pdev->dev;
0201     struct gpio_irq_chip *girq;
0202     struct rda_gpio *rda_gpio;
0203     u32 ngpios;
0204     int ret;
0205
0206     rda_gpio = devm_kzalloc(dev, sizeof(*rda_gpio), GFP_KERNEL);
0207     if (!rda_gpio)
0208         return -ENOMEM;
0209
0210     ret = device_property_read_u32(dev, "ngpios", &ngpios);
0211     if (ret < 0)
0212         return ret;
0213
0214     /*
0215      * Not all ports have interrupt capability. For instance, on
0216      * RDA8810PL, GPIOC doesn't support interrupt. So we must handle
0217      * those also.
0218      */
0219     rda_gpio->irq = platform_get_irq(pdev, 0);
0220
0221     rda_gpio->base = devm_platform_ioremap_resource(pdev, 0);
0222     if (IS_ERR(rda_gpio->base))
0223         return PTR_ERR(rda_gpio->base);
0224
0225     spin_lock_init(&rda_gpio->lock);
0226
0227     ret = bgpio_init(&rda_gpio->chip, dev, 4,
0228              rda_gpio->base + RDA_GPIO_VAL,
0229              rda_gpio->base + RDA_GPIO_SET,
0230              rda_gpio->base + RDA_GPIO_CLR,
0231              rda_gpio->base + RDA_GPIO_OEN_SET_OUT,
0232              rda_gpio->base + RDA_GPIO_OEN_SET_IN,
0233              BGPIOF_READ_OUTPUT_REG_SET);
0234     if (ret) {
0235         dev_err(dev, "bgpio_init failed\n");
0236         return ret;
0237     }
0238
0239     rda_gpio->chip.label = dev_name(dev);
0240     rda_gpio->chip.ngpio = ngpios;
0241     rda_gpio->chip.base = -1;
0242
0243     if (rda_gpio->irq >= 0) {
0244         rda_gpio->irq_chip.name = "rda-gpio",
0245         rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack,
0246         rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask,
0247         rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask,
0248         rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type,
0249         rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE,
0250
0251         girq = &rda_gpio->chip.irq;
0252         girq->chip = &rda_gpio->irq_chip;
0253         girq->handler = handle_bad_irq;
0254         girq->default_type = IRQ_TYPE_NONE;
0255         girq->parent_handler = rda_gpio_irq_handler;
0256         girq->parent_handler_data = rda_gpio;
0257         girq->num_parents = 1;
0258         girq->parents = devm_kcalloc(dev, 1,
0259                          sizeof(*girq->parents),
0260                          GFP_KERNEL);
0261         if (!girq->parents)
0262             return -ENOMEM;
0263         girq->parents[0] = rda_gpio->irq;
0264     }
0265
0266     platform_set_drvdata(pdev, rda_gpio);
0267
0268     return devm_gpiochip_add_data(dev, &rda_gpio->chip, rda_gpio);
0269 }
0270
0271 static const struct of_device_id rda_gpio_of_match[] = {
0272     { .compatible = "rda,8810pl-gpio", },
0273     { /* sentinel */ }
0274 };
0275 MODULE_DEVICE_TABLE(of, rda_gpio_of_match);
0276
0277 static struct platform_driver rda_gpio_driver = {
0278     .probe = rda_gpio_probe,
0279     .driver = {
0280         .name = "rda-gpio",
0281         .of_match_table = rda_gpio_of_match,
0282     },
0283 };
0284
0285 module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe);
0286
0287 MODULE_DESCRIPTION("RDA Micro GPIO driver");
0288 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
0289 MODULE_LICENSE("GPL v2");