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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas R-Car GPIO Support
0004  *
0005  *  Copyright (C) 2014 Renesas Electronics Corporation
0006  *  Copyright (C) 2013 Magnus Damm
0007  */
0008 
0009 #include <linux/err.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/ioport.h>
0015 #include <linux/irq.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/pinctrl/consumer.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/slab.h>
0024 
0025 struct gpio_rcar_bank_info {
0026     u32 iointsel;
0027     u32 inoutsel;
0028     u32 outdt;
0029     u32 posneg;
0030     u32 edglevel;
0031     u32 bothedge;
0032     u32 intmsk;
0033 };
0034 
0035 struct gpio_rcar_info {
0036     bool has_outdtsel;
0037     bool has_both_edge_trigger;
0038     bool has_always_in;
0039     bool has_inen;
0040 };
0041 
0042 struct gpio_rcar_priv {
0043     void __iomem *base;
0044     spinlock_t lock;
0045     struct device *dev;
0046     struct gpio_chip gpio_chip;
0047     unsigned int irq_parent;
0048     atomic_t wakeup_path;
0049     struct gpio_rcar_info info;
0050     struct gpio_rcar_bank_info bank_info;
0051 };
0052 
0053 #define IOINTSEL    0x00    /* General IO/Interrupt Switching Register */
0054 #define INOUTSEL    0x04    /* General Input/Output Switching Register */
0055 #define OUTDT       0x08    /* General Output Register */
0056 #define INDT        0x0c    /* General Input Register */
0057 #define INTDT       0x10    /* Interrupt Display Register */
0058 #define INTCLR      0x14    /* Interrupt Clear Register */
0059 #define INTMSK      0x18    /* Interrupt Mask Register */
0060 #define MSKCLR      0x1c    /* Interrupt Mask Clear Register */
0061 #define POSNEG      0x20    /* Positive/Negative Logic Select Register */
0062 #define EDGLEVEL    0x24    /* Edge/level Select Register */
0063 #define FILONOFF    0x28    /* Chattering Prevention On/Off Register */
0064 #define OUTDTSEL    0x40    /* Output Data Select Register */
0065 #define BOTHEDGE    0x4c    /* One Edge/Both Edge Select Register */
0066 #define INEN        0x50    /* General Input Enable Register */
0067 
0068 #define RCAR_MAX_GPIO_PER_BANK      32
0069 
0070 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
0071 {
0072     return ioread32(p->base + offs);
0073 }
0074 
0075 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
0076                    u32 value)
0077 {
0078     iowrite32(value, p->base + offs);
0079 }
0080 
0081 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
0082                  int bit, bool value)
0083 {
0084     u32 tmp = gpio_rcar_read(p, offs);
0085 
0086     if (value)
0087         tmp |= BIT(bit);
0088     else
0089         tmp &= ~BIT(bit);
0090 
0091     gpio_rcar_write(p, offs, tmp);
0092 }
0093 
0094 static void gpio_rcar_irq_disable(struct irq_data *d)
0095 {
0096     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0097     struct gpio_rcar_priv *p = gpiochip_get_data(gc);
0098     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0099 
0100     gpio_rcar_write(p, INTMSK, ~BIT(hwirq));
0101     gpiochip_disable_irq(gc, hwirq);
0102 }
0103 
0104 static void gpio_rcar_irq_enable(struct irq_data *d)
0105 {
0106     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0107     struct gpio_rcar_priv *p = gpiochip_get_data(gc);
0108     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0109 
0110     gpiochip_enable_irq(gc, hwirq);
0111     gpio_rcar_write(p, MSKCLR, BIT(hwirq));
0112 }
0113 
0114 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
0115                           unsigned int hwirq,
0116                           bool active_high_rising_edge,
0117                           bool level_trigger,
0118                           bool both)
0119 {
0120     unsigned long flags;
0121 
0122     /* follow steps in the GPIO documentation for
0123      * "Setting Edge-Sensitive Interrupt Input Mode" and
0124      * "Setting Level-Sensitive Interrupt Input Mode"
0125      */
0126 
0127     spin_lock_irqsave(&p->lock, flags);
0128 
0129     /* Configure positive or negative logic in POSNEG */
0130     gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
0131 
0132     /* Configure edge or level trigger in EDGLEVEL */
0133     gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
0134 
0135     /* Select one edge or both edges in BOTHEDGE */
0136     if (p->info.has_both_edge_trigger)
0137         gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
0138 
0139     /* Select "Interrupt Input Mode" in IOINTSEL */
0140     gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
0141 
0142     /* Write INTCLR in case of edge trigger */
0143     if (!level_trigger)
0144         gpio_rcar_write(p, INTCLR, BIT(hwirq));
0145 
0146     spin_unlock_irqrestore(&p->lock, flags);
0147 }
0148 
0149 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
0150 {
0151     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0152     struct gpio_rcar_priv *p = gpiochip_get_data(gc);
0153     unsigned int hwirq = irqd_to_hwirq(d);
0154 
0155     dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
0156 
0157     switch (type & IRQ_TYPE_SENSE_MASK) {
0158     case IRQ_TYPE_LEVEL_HIGH:
0159         gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
0160                               false);
0161         break;
0162     case IRQ_TYPE_LEVEL_LOW:
0163         gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
0164                               false);
0165         break;
0166     case IRQ_TYPE_EDGE_RISING:
0167         gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
0168                               false);
0169         break;
0170     case IRQ_TYPE_EDGE_FALLING:
0171         gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
0172                               false);
0173         break;
0174     case IRQ_TYPE_EDGE_BOTH:
0175         if (!p->info.has_both_edge_trigger)
0176             return -EINVAL;
0177         gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
0178                               true);
0179         break;
0180     default:
0181         return -EINVAL;
0182     }
0183     return 0;
0184 }
0185 
0186 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
0187 {
0188     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0189     struct gpio_rcar_priv *p = gpiochip_get_data(gc);
0190     int error;
0191 
0192     if (p->irq_parent) {
0193         error = irq_set_irq_wake(p->irq_parent, on);
0194         if (error) {
0195             dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
0196                 p->irq_parent);
0197             p->irq_parent = 0;
0198         }
0199     }
0200 
0201     if (on)
0202         atomic_inc(&p->wakeup_path);
0203     else
0204         atomic_dec(&p->wakeup_path);
0205 
0206     return 0;
0207 }
0208 
0209 static const struct irq_chip gpio_rcar_irq_chip = {
0210     .name       = "gpio-rcar",
0211     .irq_mask   = gpio_rcar_irq_disable,
0212     .irq_unmask = gpio_rcar_irq_enable,
0213     .irq_set_type   = gpio_rcar_irq_set_type,
0214     .irq_set_wake   = gpio_rcar_irq_set_wake,
0215     .flags      = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED |
0216               IRQCHIP_MASK_ON_SUSPEND,
0217     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0218 };
0219 
0220 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
0221 {
0222     struct gpio_rcar_priv *p = dev_id;
0223     u32 pending;
0224     unsigned int offset, irqs_handled = 0;
0225 
0226     while ((pending = gpio_rcar_read(p, INTDT) &
0227               gpio_rcar_read(p, INTMSK))) {
0228         offset = __ffs(pending);
0229         gpio_rcar_write(p, INTCLR, BIT(offset));
0230         generic_handle_domain_irq(p->gpio_chip.irq.domain,
0231                       offset);
0232         irqs_handled++;
0233     }
0234 
0235     return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
0236 }
0237 
0238 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
0239                                unsigned int gpio,
0240                                bool output)
0241 {
0242     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0243     unsigned long flags;
0244 
0245     /* follow steps in the GPIO documentation for
0246      * "Setting General Output Mode" and
0247      * "Setting General Input Mode"
0248      */
0249 
0250     spin_lock_irqsave(&p->lock, flags);
0251 
0252     /* Configure positive logic in POSNEG */
0253     gpio_rcar_modify_bit(p, POSNEG, gpio, false);
0254 
0255     /* Select "General Input/Output Mode" in IOINTSEL */
0256     gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
0257 
0258     /* Select Input Mode or Output Mode in INOUTSEL */
0259     gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
0260 
0261     /* Select General Output Register to output data in OUTDTSEL */
0262     if (p->info.has_outdtsel && output)
0263         gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
0264 
0265     spin_unlock_irqrestore(&p->lock, flags);
0266 }
0267 
0268 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
0269 {
0270     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0271     int error;
0272 
0273     error = pm_runtime_get_sync(p->dev);
0274     if (error < 0) {
0275         pm_runtime_put(p->dev);
0276         return error;
0277     }
0278 
0279     error = pinctrl_gpio_request(chip->base + offset);
0280     if (error)
0281         pm_runtime_put(p->dev);
0282 
0283     return error;
0284 }
0285 
0286 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
0287 {
0288     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0289 
0290     pinctrl_gpio_free(chip->base + offset);
0291 
0292     /*
0293      * Set the GPIO as an input to ensure that the next GPIO request won't
0294      * drive the GPIO pin as an output.
0295      */
0296     gpio_rcar_config_general_input_output_mode(chip, offset, false);
0297 
0298     pm_runtime_put(p->dev);
0299 }
0300 
0301 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
0302 {
0303     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0304 
0305     if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
0306         return GPIO_LINE_DIRECTION_OUT;
0307 
0308     return GPIO_LINE_DIRECTION_IN;
0309 }
0310 
0311 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
0312 {
0313     gpio_rcar_config_general_input_output_mode(chip, offset, false);
0314     return 0;
0315 }
0316 
0317 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
0318 {
0319     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0320     u32 bit = BIT(offset);
0321 
0322     /*
0323      * Before R-Car Gen3, INDT does not show correct pin state when
0324      * configured as output, so use OUTDT in case of output pins
0325      */
0326     if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))
0327         return !!(gpio_rcar_read(p, OUTDT) & bit);
0328     else
0329         return !!(gpio_rcar_read(p, INDT) & bit);
0330 }
0331 
0332 static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
0333                   unsigned long *bits)
0334 {
0335     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0336     u32 bankmask, outputs, m, val = 0;
0337     unsigned long flags;
0338 
0339     bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
0340     if (chip->valid_mask)
0341         bankmask &= chip->valid_mask[0];
0342 
0343     if (!bankmask)
0344         return 0;
0345 
0346     if (p->info.has_always_in) {
0347         bits[0] = gpio_rcar_read(p, INDT) & bankmask;
0348         return 0;
0349     }
0350 
0351     spin_lock_irqsave(&p->lock, flags);
0352     outputs = gpio_rcar_read(p, INOUTSEL);
0353     m = outputs & bankmask;
0354     if (m)
0355         val |= gpio_rcar_read(p, OUTDT) & m;
0356 
0357     m = ~outputs & bankmask;
0358     if (m)
0359         val |= gpio_rcar_read(p, INDT) & m;
0360     spin_unlock_irqrestore(&p->lock, flags);
0361 
0362     bits[0] = val;
0363     return 0;
0364 }
0365 
0366 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
0367 {
0368     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0369     unsigned long flags;
0370 
0371     spin_lock_irqsave(&p->lock, flags);
0372     gpio_rcar_modify_bit(p, OUTDT, offset, value);
0373     spin_unlock_irqrestore(&p->lock, flags);
0374 }
0375 
0376 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
0377                    unsigned long *bits)
0378 {
0379     struct gpio_rcar_priv *p = gpiochip_get_data(chip);
0380     unsigned long flags;
0381     u32 val, bankmask;
0382 
0383     bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
0384     if (chip->valid_mask)
0385         bankmask &= chip->valid_mask[0];
0386 
0387     if (!bankmask)
0388         return;
0389 
0390     spin_lock_irqsave(&p->lock, flags);
0391     val = gpio_rcar_read(p, OUTDT);
0392     val &= ~bankmask;
0393     val |= (bankmask & bits[0]);
0394     gpio_rcar_write(p, OUTDT, val);
0395     spin_unlock_irqrestore(&p->lock, flags);
0396 }
0397 
0398 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
0399                       int value)
0400 {
0401     /* write GPIO value to output before selecting output mode of pin */
0402     gpio_rcar_set(chip, offset, value);
0403     gpio_rcar_config_general_input_output_mode(chip, offset, true);
0404     return 0;
0405 }
0406 
0407 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
0408     .has_outdtsel = false,
0409     .has_both_edge_trigger = false,
0410     .has_always_in = false,
0411     .has_inen = false,
0412 };
0413 
0414 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
0415     .has_outdtsel = true,
0416     .has_both_edge_trigger = true,
0417     .has_always_in = false,
0418     .has_inen = false,
0419 };
0420 
0421 static const struct gpio_rcar_info gpio_rcar_info_gen3 = {
0422     .has_outdtsel = true,
0423     .has_both_edge_trigger = true,
0424     .has_always_in = true,
0425     .has_inen = false,
0426 };
0427 
0428 static const struct gpio_rcar_info gpio_rcar_info_gen4 = {
0429     .has_outdtsel = true,
0430     .has_both_edge_trigger = true,
0431     .has_always_in = true,
0432     .has_inen = true,
0433 };
0434 
0435 static const struct of_device_id gpio_rcar_of_table[] = {
0436     {
0437         .compatible = "renesas,gpio-r8a779a0",
0438         .data = &gpio_rcar_info_gen4,
0439     }, {
0440         .compatible = "renesas,rcar-gen1-gpio",
0441         .data = &gpio_rcar_info_gen1,
0442     }, {
0443         .compatible = "renesas,rcar-gen2-gpio",
0444         .data = &gpio_rcar_info_gen2,
0445     }, {
0446         .compatible = "renesas,rcar-gen3-gpio",
0447         .data = &gpio_rcar_info_gen3,
0448     }, {
0449         .compatible = "renesas,rcar-gen4-gpio",
0450         .data = &gpio_rcar_info_gen4,
0451     }, {
0452         .compatible = "renesas,gpio-rcar",
0453         .data = &gpio_rcar_info_gen1,
0454     }, {
0455         /* Terminator */
0456     },
0457 };
0458 
0459 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
0460 
0461 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
0462 {
0463     struct device_node *np = p->dev->of_node;
0464     const struct gpio_rcar_info *info;
0465     struct of_phandle_args args;
0466     int ret;
0467 
0468     info = of_device_get_match_data(p->dev);
0469     p->info = *info;
0470 
0471     ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
0472     *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
0473 
0474     if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
0475         dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
0476              *npins, RCAR_MAX_GPIO_PER_BANK);
0477         *npins = RCAR_MAX_GPIO_PER_BANK;
0478     }
0479 
0480     return 0;
0481 }
0482 
0483 static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)
0484 {
0485     u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);
0486 
0487     /* Select "Input Enable" in INEN */
0488     if (p->gpio_chip.valid_mask)
0489         mask &= p->gpio_chip.valid_mask[0];
0490     if (mask)
0491         gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);
0492 }
0493 
0494 static int gpio_rcar_probe(struct platform_device *pdev)
0495 {
0496     struct gpio_rcar_priv *p;
0497     struct gpio_chip *gpio_chip;
0498     struct gpio_irq_chip *girq;
0499     struct device *dev = &pdev->dev;
0500     const char *name = dev_name(dev);
0501     unsigned int npins;
0502     int ret;
0503 
0504     p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
0505     if (!p)
0506         return -ENOMEM;
0507 
0508     p->dev = dev;
0509     spin_lock_init(&p->lock);
0510 
0511     /* Get device configuration from DT node */
0512     ret = gpio_rcar_parse_dt(p, &npins);
0513     if (ret < 0)
0514         return ret;
0515 
0516     platform_set_drvdata(pdev, p);
0517 
0518     pm_runtime_enable(dev);
0519 
0520     ret = platform_get_irq(pdev, 0);
0521     if (ret < 0)
0522         goto err0;
0523     p->irq_parent = ret;
0524 
0525     p->base = devm_platform_ioremap_resource(pdev, 0);
0526     if (IS_ERR(p->base)) {
0527         ret = PTR_ERR(p->base);
0528         goto err0;
0529     }
0530 
0531     gpio_chip = &p->gpio_chip;
0532     gpio_chip->request = gpio_rcar_request;
0533     gpio_chip->free = gpio_rcar_free;
0534     gpio_chip->get_direction = gpio_rcar_get_direction;
0535     gpio_chip->direction_input = gpio_rcar_direction_input;
0536     gpio_chip->get = gpio_rcar_get;
0537     gpio_chip->get_multiple = gpio_rcar_get_multiple;
0538     gpio_chip->direction_output = gpio_rcar_direction_output;
0539     gpio_chip->set = gpio_rcar_set;
0540     gpio_chip->set_multiple = gpio_rcar_set_multiple;
0541     gpio_chip->label = name;
0542     gpio_chip->parent = dev;
0543     gpio_chip->owner = THIS_MODULE;
0544     gpio_chip->base = -1;
0545     gpio_chip->ngpio = npins;
0546 
0547     girq = &gpio_chip->irq;
0548     gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip);
0549     /* This will let us handle the parent IRQ in the driver */
0550     girq->parent_handler = NULL;
0551     girq->num_parents = 0;
0552     girq->parents = NULL;
0553     girq->default_type = IRQ_TYPE_NONE;
0554     girq->handler = handle_level_irq;
0555 
0556     ret = gpiochip_add_data(gpio_chip, p);
0557     if (ret) {
0558         dev_err(dev, "failed to add GPIO controller\n");
0559         goto err0;
0560     }
0561 
0562     irq_domain_set_pm_device(gpio_chip->irq.domain, dev);
0563     ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,
0564                    IRQF_SHARED, name, p);
0565     if (ret) {
0566         dev_err(dev, "failed to request IRQ\n");
0567         goto err1;
0568     }
0569 
0570     if (p->info.has_inen) {
0571         pm_runtime_get_sync(dev);
0572         gpio_rcar_enable_inputs(p);
0573         pm_runtime_put(dev);
0574     }
0575 
0576     dev_info(dev, "driving %d GPIOs\n", npins);
0577 
0578     return 0;
0579 
0580 err1:
0581     gpiochip_remove(gpio_chip);
0582 err0:
0583     pm_runtime_disable(dev);
0584     return ret;
0585 }
0586 
0587 static int gpio_rcar_remove(struct platform_device *pdev)
0588 {
0589     struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
0590 
0591     gpiochip_remove(&p->gpio_chip);
0592 
0593     pm_runtime_disable(&pdev->dev);
0594     return 0;
0595 }
0596 
0597 #ifdef CONFIG_PM_SLEEP
0598 static int gpio_rcar_suspend(struct device *dev)
0599 {
0600     struct gpio_rcar_priv *p = dev_get_drvdata(dev);
0601 
0602     p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
0603     p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
0604     p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
0605     p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
0606     p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
0607     p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
0608     if (p->info.has_both_edge_trigger)
0609         p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
0610 
0611     if (atomic_read(&p->wakeup_path))
0612         device_set_wakeup_path(dev);
0613 
0614     return 0;
0615 }
0616 
0617 static int gpio_rcar_resume(struct device *dev)
0618 {
0619     struct gpio_rcar_priv *p = dev_get_drvdata(dev);
0620     unsigned int offset;
0621     u32 mask;
0622 
0623     for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
0624         if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
0625             continue;
0626 
0627         mask = BIT(offset);
0628         /* I/O pin */
0629         if (!(p->bank_info.iointsel & mask)) {
0630             if (p->bank_info.inoutsel & mask)
0631                 gpio_rcar_direction_output(
0632                     &p->gpio_chip, offset,
0633                     !!(p->bank_info.outdt & mask));
0634             else
0635                 gpio_rcar_direction_input(&p->gpio_chip,
0636                               offset);
0637         } else {
0638             /* Interrupt pin */
0639             gpio_rcar_config_interrupt_input_mode(
0640                 p,
0641                 offset,
0642                 !(p->bank_info.posneg & mask),
0643                 !(p->bank_info.edglevel & mask),
0644                 !!(p->bank_info.bothedge & mask));
0645 
0646             if (p->bank_info.intmsk & mask)
0647                 gpio_rcar_write(p, MSKCLR, mask);
0648         }
0649     }
0650 
0651     if (p->info.has_inen)
0652         gpio_rcar_enable_inputs(p);
0653 
0654     return 0;
0655 }
0656 #endif /* CONFIG_PM_SLEEP*/
0657 
0658 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
0659 
0660 static struct platform_driver gpio_rcar_device_driver = {
0661     .probe      = gpio_rcar_probe,
0662     .remove     = gpio_rcar_remove,
0663     .driver     = {
0664         .name   = "gpio_rcar",
0665         .pm     = &gpio_rcar_pm_ops,
0666         .of_match_table = of_match_ptr(gpio_rcar_of_table),
0667     }
0668 };
0669 
0670 module_platform_driver(gpio_rcar_device_driver);
0671 
0672 MODULE_AUTHOR("Magnus Damm");
0673 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
0674 MODULE_LICENSE("GPL v2");
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