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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/plat-pxa/gpio.c
0004  *
0005  *  Generic PXA GPIO handling
0006  *
0007  *  Author: Nicolas Pitre
0008  *  Created:    Jun 15, 2001
0009  *  Copyright:  MontaVista Software Inc.
0010  */
0011 #include <linux/module.h>
0012 #include <linux/clk.h>
0013 #include <linux/err.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/gpio-pxa.h>
0016 #include <linux/init.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/irq.h>
0019 #include <linux/irqdomain.h>
0020 #include <linux/irqchip/chained_irq.h>
0021 #include <linux/io.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 #include <linux/pinctrl/consumer.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/syscore_ops.h>
0027 #include <linux/slab.h>
0028 
0029 /*
0030  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
0031  * one set of registers. The register offsets are organized below:
0032  *
0033  *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
0034  * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
0035  * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
0036  * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
0037  *
0038  * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
0039  * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
0040  * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
0041  *
0042  * BANK 6 - 0x0200  0x020C  0x0218  0x0224  0x0230  0x023C  0x0248
0043  *
0044  * NOTE:
0045  *   BANK 3 is only available on PXA27x and later processors.
0046  *   BANK 4 and 5 are only available on PXA935, PXA1928
0047  *   BANK 6 is only available on PXA1928
0048  */
0049 
0050 #define GPLR_OFFSET 0x00
0051 #define GPDR_OFFSET 0x0C
0052 #define GPSR_OFFSET 0x18
0053 #define GPCR_OFFSET 0x24
0054 #define GRER_OFFSET 0x30
0055 #define GFER_OFFSET 0x3C
0056 #define GEDR_OFFSET 0x48
0057 #define GAFR_OFFSET 0x54
0058 #define ED_MASK_OFFSET  0x9C    /* GPIO edge detection for AP side */
0059 
0060 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
0061 
0062 int pxa_last_gpio;
0063 static int irq_base;
0064 
0065 struct pxa_gpio_bank {
0066     void __iomem    *regbase;
0067     unsigned long   irq_mask;
0068     unsigned long   irq_edge_rise;
0069     unsigned long   irq_edge_fall;
0070 
0071 #ifdef CONFIG_PM
0072     unsigned long   saved_gplr;
0073     unsigned long   saved_gpdr;
0074     unsigned long   saved_grer;
0075     unsigned long   saved_gfer;
0076 #endif
0077 };
0078 
0079 struct pxa_gpio_chip {
0080     struct device *dev;
0081     struct gpio_chip chip;
0082     struct pxa_gpio_bank *banks;
0083     struct irq_domain *irqdomain;
0084 
0085     int irq0;
0086     int irq1;
0087     int (*set_wake)(unsigned int gpio, unsigned int on);
0088 };
0089 
0090 enum pxa_gpio_type {
0091     PXA25X_GPIO = 0,
0092     PXA26X_GPIO,
0093     PXA27X_GPIO,
0094     PXA3XX_GPIO,
0095     PXA93X_GPIO,
0096     MMP_GPIO = 0x10,
0097     MMP2_GPIO,
0098     PXA1928_GPIO,
0099 };
0100 
0101 struct pxa_gpio_id {
0102     enum pxa_gpio_type  type;
0103     int         gpio_nums;
0104 };
0105 
0106 static DEFINE_SPINLOCK(gpio_lock);
0107 static struct pxa_gpio_chip *pxa_gpio_chip;
0108 static enum pxa_gpio_type gpio_type;
0109 
0110 static struct pxa_gpio_id pxa25x_id = {
0111     .type       = PXA25X_GPIO,
0112     .gpio_nums  = 85,
0113 };
0114 
0115 static struct pxa_gpio_id pxa26x_id = {
0116     .type       = PXA26X_GPIO,
0117     .gpio_nums  = 90,
0118 };
0119 
0120 static struct pxa_gpio_id pxa27x_id = {
0121     .type       = PXA27X_GPIO,
0122     .gpio_nums  = 121,
0123 };
0124 
0125 static struct pxa_gpio_id pxa3xx_id = {
0126     .type       = PXA3XX_GPIO,
0127     .gpio_nums  = 128,
0128 };
0129 
0130 static struct pxa_gpio_id pxa93x_id = {
0131     .type       = PXA93X_GPIO,
0132     .gpio_nums  = 192,
0133 };
0134 
0135 static struct pxa_gpio_id mmp_id = {
0136     .type       = MMP_GPIO,
0137     .gpio_nums  = 128,
0138 };
0139 
0140 static struct pxa_gpio_id mmp2_id = {
0141     .type       = MMP2_GPIO,
0142     .gpio_nums  = 192,
0143 };
0144 
0145 static struct pxa_gpio_id pxa1928_id = {
0146     .type       = PXA1928_GPIO,
0147     .gpio_nums  = 224,
0148 };
0149 
0150 #define for_each_gpio_bank(i, b, pc)                    \
0151     for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
0152 
0153 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
0154 {
0155     struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
0156 
0157     return pxa_chip;
0158 }
0159 
0160 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
0161 {
0162     struct pxa_gpio_chip *p = gpiochip_get_data(c);
0163     struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
0164 
0165     return bank->regbase;
0166 }
0167 
0168 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
0169                             unsigned gpio)
0170 {
0171     return chip_to_pxachip(c)->banks + gpio / 32;
0172 }
0173 
0174 static inline int gpio_is_pxa_type(int type)
0175 {
0176     return (type & MMP_GPIO) == 0;
0177 }
0178 
0179 static inline int gpio_is_mmp_type(int type)
0180 {
0181     return (type & MMP_GPIO) != 0;
0182 }
0183 
0184 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
0185  * as well as their Alternate Function value being '1' for GPIO in GAFRx.
0186  */
0187 static inline int __gpio_is_inverted(int gpio)
0188 {
0189     if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
0190         return 1;
0191     return 0;
0192 }
0193 
0194 /*
0195  * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
0196  * function of a GPIO, and GPDRx cannot be altered once configured. It
0197  * is attributed as "occupied" here (I know this terminology isn't
0198  * accurate, you are welcome to propose a better one :-)
0199  */
0200 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
0201 {
0202     void __iomem *base;
0203     unsigned long gafr = 0, gpdr = 0;
0204     int ret, af = 0, dir = 0;
0205 
0206     base = gpio_bank_base(&pchip->chip, gpio);
0207     gpdr = readl_relaxed(base + GPDR_OFFSET);
0208 
0209     switch (gpio_type) {
0210     case PXA25X_GPIO:
0211     case PXA26X_GPIO:
0212     case PXA27X_GPIO:
0213         gafr = readl_relaxed(base + GAFR_OFFSET);
0214         af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
0215         dir = gpdr & GPIO_bit(gpio);
0216 
0217         if (__gpio_is_inverted(gpio))
0218             ret = (af != 1) || (dir == 0);
0219         else
0220             ret = (af != 0) || (dir != 0);
0221         break;
0222     default:
0223         ret = gpdr & GPIO_bit(gpio);
0224         break;
0225     }
0226     return ret;
0227 }
0228 
0229 int pxa_irq_to_gpio(int irq)
0230 {
0231     struct pxa_gpio_chip *pchip = pxa_gpio_chip;
0232     int irq_gpio0;
0233 
0234     irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
0235     if (irq_gpio0 > 0)
0236         return irq - irq_gpio0;
0237 
0238     return irq_gpio0;
0239 }
0240 
0241 static bool pxa_gpio_has_pinctrl(void)
0242 {
0243     switch (gpio_type) {
0244     case PXA3XX_GPIO:
0245     case MMP2_GPIO:
0246         return false;
0247 
0248     default:
0249         return true;
0250     }
0251 }
0252 
0253 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
0254 {
0255     struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
0256 
0257     return irq_find_mapping(pchip->irqdomain, offset);
0258 }
0259 
0260 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0261 {
0262     void __iomem *base = gpio_bank_base(chip, offset);
0263     uint32_t value, mask = GPIO_bit(offset);
0264     unsigned long flags;
0265     int ret;
0266 
0267     if (pxa_gpio_has_pinctrl()) {
0268         ret = pinctrl_gpio_direction_input(chip->base + offset);
0269         if (ret)
0270             return ret;
0271     }
0272 
0273     spin_lock_irqsave(&gpio_lock, flags);
0274 
0275     value = readl_relaxed(base + GPDR_OFFSET);
0276     if (__gpio_is_inverted(chip->base + offset))
0277         value |= mask;
0278     else
0279         value &= ~mask;
0280     writel_relaxed(value, base + GPDR_OFFSET);
0281 
0282     spin_unlock_irqrestore(&gpio_lock, flags);
0283     return 0;
0284 }
0285 
0286 static int pxa_gpio_direction_output(struct gpio_chip *chip,
0287                      unsigned offset, int value)
0288 {
0289     void __iomem *base = gpio_bank_base(chip, offset);
0290     uint32_t tmp, mask = GPIO_bit(offset);
0291     unsigned long flags;
0292     int ret;
0293 
0294     writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0295 
0296     if (pxa_gpio_has_pinctrl()) {
0297         ret = pinctrl_gpio_direction_output(chip->base + offset);
0298         if (ret)
0299             return ret;
0300     }
0301 
0302     spin_lock_irqsave(&gpio_lock, flags);
0303 
0304     tmp = readl_relaxed(base + GPDR_OFFSET);
0305     if (__gpio_is_inverted(chip->base + offset))
0306         tmp &= ~mask;
0307     else
0308         tmp |= mask;
0309     writel_relaxed(tmp, base + GPDR_OFFSET);
0310 
0311     spin_unlock_irqrestore(&gpio_lock, flags);
0312     return 0;
0313 }
0314 
0315 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
0316 {
0317     void __iomem *base = gpio_bank_base(chip, offset);
0318     u32 gplr = readl_relaxed(base + GPLR_OFFSET);
0319 
0320     return !!(gplr & GPIO_bit(offset));
0321 }
0322 
0323 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0324 {
0325     void __iomem *base = gpio_bank_base(chip, offset);
0326 
0327     writel_relaxed(GPIO_bit(offset),
0328                base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0329 }
0330 
0331 #ifdef CONFIG_OF_GPIO
0332 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
0333                  const struct of_phandle_args *gpiospec,
0334                  u32 *flags)
0335 {
0336     if (gpiospec->args[0] > pxa_last_gpio)
0337         return -EINVAL;
0338 
0339     if (flags)
0340         *flags = gpiospec->args[1];
0341 
0342     return gpiospec->args[0];
0343 }
0344 #endif
0345 
0346 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase)
0347 {
0348     int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
0349     struct pxa_gpio_bank *bank;
0350 
0351     pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
0352                     GFP_KERNEL);
0353     if (!pchip->banks)
0354         return -ENOMEM;
0355 
0356     pchip->chip.parent = pchip->dev;
0357     pchip->chip.label = "gpio-pxa";
0358     pchip->chip.direction_input  = pxa_gpio_direction_input;
0359     pchip->chip.direction_output = pxa_gpio_direction_output;
0360     pchip->chip.get = pxa_gpio_get;
0361     pchip->chip.set = pxa_gpio_set;
0362     pchip->chip.to_irq = pxa_gpio_to_irq;
0363     pchip->chip.ngpio = ngpio;
0364     pchip->chip.request = gpiochip_generic_request;
0365     pchip->chip.free = gpiochip_generic_free;
0366 
0367 #ifdef CONFIG_OF_GPIO
0368     pchip->chip.of_xlate = pxa_gpio_of_xlate;
0369     pchip->chip.of_gpio_n_cells = 2;
0370 #endif
0371 
0372     for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
0373         bank = pchip->banks + i;
0374         bank->regbase = regbase + BANK_OFF(i);
0375     }
0376 
0377     return gpiochip_add_data(&pchip->chip, pchip);
0378 }
0379 
0380 /* Update only those GRERx and GFERx edge detection register bits if those
0381  * bits are set in c->irq_mask
0382  */
0383 static inline void update_edge_detect(struct pxa_gpio_bank *c)
0384 {
0385     uint32_t grer, gfer;
0386 
0387     grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
0388     gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
0389     grer |= c->irq_edge_rise & c->irq_mask;
0390     gfer |= c->irq_edge_fall & c->irq_mask;
0391     writel_relaxed(grer, c->regbase + GRER_OFFSET);
0392     writel_relaxed(gfer, c->regbase + GFER_OFFSET);
0393 }
0394 
0395 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
0396 {
0397     struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
0398     unsigned int gpio = irqd_to_hwirq(d);
0399     struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
0400     unsigned long gpdr, mask = GPIO_bit(gpio);
0401 
0402     if (type == IRQ_TYPE_PROBE) {
0403         /* Don't mess with enabled GPIOs using preconfigured edges or
0404          * GPIOs set to alternate function or to output during probe
0405          */
0406         if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
0407             return 0;
0408 
0409         if (__gpio_is_occupied(pchip, gpio))
0410             return 0;
0411 
0412         type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
0413     }
0414 
0415     gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0416 
0417     if (__gpio_is_inverted(gpio))
0418         writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
0419     else
0420         writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
0421 
0422     if (type & IRQ_TYPE_EDGE_RISING)
0423         c->irq_edge_rise |= mask;
0424     else
0425         c->irq_edge_rise &= ~mask;
0426 
0427     if (type & IRQ_TYPE_EDGE_FALLING)
0428         c->irq_edge_fall |= mask;
0429     else
0430         c->irq_edge_fall &= ~mask;
0431 
0432     update_edge_detect(c);
0433 
0434     pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
0435         ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
0436         ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
0437     return 0;
0438 }
0439 
0440 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
0441 {
0442     int loop, gpio, n, handled = 0;
0443     unsigned long gedr;
0444     struct pxa_gpio_chip *pchip = d;
0445     struct pxa_gpio_bank *c;
0446 
0447     do {
0448         loop = 0;
0449         for_each_gpio_bank(gpio, c, pchip) {
0450             gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
0451             gedr = gedr & c->irq_mask;
0452             writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
0453 
0454             for_each_set_bit(n, &gedr, BITS_PER_LONG) {
0455                 loop = 1;
0456 
0457                 generic_handle_domain_irq(pchip->irqdomain,
0458                               gpio + n);
0459             }
0460         }
0461         handled += loop;
0462     } while (loop);
0463 
0464     return handled ? IRQ_HANDLED : IRQ_NONE;
0465 }
0466 
0467 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
0468 {
0469     struct pxa_gpio_chip *pchip = d;
0470 
0471     if (in_irq == pchip->irq0) {
0472         generic_handle_domain_irq(pchip->irqdomain, 0);
0473     } else if (in_irq == pchip->irq1) {
0474         generic_handle_domain_irq(pchip->irqdomain, 1);
0475     } else {
0476         pr_err("%s() unknown irq %d\n", __func__, in_irq);
0477         return IRQ_NONE;
0478     }
0479     return IRQ_HANDLED;
0480 }
0481 
0482 static void pxa_ack_muxed_gpio(struct irq_data *d)
0483 {
0484     struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
0485     unsigned int gpio = irqd_to_hwirq(d);
0486     void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
0487 
0488     writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
0489 }
0490 
0491 static void pxa_mask_muxed_gpio(struct irq_data *d)
0492 {
0493     struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
0494     unsigned int gpio = irqd_to_hwirq(d);
0495     struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
0496     void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
0497     uint32_t grer, gfer;
0498 
0499     b->irq_mask &= ~GPIO_bit(gpio);
0500 
0501     grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
0502     gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
0503     writel_relaxed(grer, base + GRER_OFFSET);
0504     writel_relaxed(gfer, base + GFER_OFFSET);
0505 }
0506 
0507 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
0508 {
0509     struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
0510     unsigned int gpio = irqd_to_hwirq(d);
0511 
0512     if (pchip->set_wake)
0513         return pchip->set_wake(gpio, on);
0514     else
0515         return 0;
0516 }
0517 
0518 static void pxa_unmask_muxed_gpio(struct irq_data *d)
0519 {
0520     struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
0521     unsigned int gpio = irqd_to_hwirq(d);
0522     struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
0523 
0524     c->irq_mask |= GPIO_bit(gpio);
0525     update_edge_detect(c);
0526 }
0527 
0528 static struct irq_chip pxa_muxed_gpio_chip = {
0529     .name       = "GPIO",
0530     .irq_ack    = pxa_ack_muxed_gpio,
0531     .irq_mask   = pxa_mask_muxed_gpio,
0532     .irq_unmask = pxa_unmask_muxed_gpio,
0533     .irq_set_type   = pxa_gpio_irq_type,
0534     .irq_set_wake   = pxa_gpio_set_wake,
0535 };
0536 
0537 static int pxa_gpio_nums(struct platform_device *pdev)
0538 {
0539     const struct platform_device_id *id = platform_get_device_id(pdev);
0540     struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
0541     int count = 0;
0542 
0543     switch (pxa_id->type) {
0544     case PXA25X_GPIO:
0545     case PXA26X_GPIO:
0546     case PXA27X_GPIO:
0547     case PXA3XX_GPIO:
0548     case PXA93X_GPIO:
0549     case MMP_GPIO:
0550     case MMP2_GPIO:
0551     case PXA1928_GPIO:
0552         gpio_type = pxa_id->type;
0553         count = pxa_id->gpio_nums - 1;
0554         break;
0555     default:
0556         count = -EINVAL;
0557         break;
0558     }
0559     return count;
0560 }
0561 
0562 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
0563                   irq_hw_number_t hw)
0564 {
0565     irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
0566                  handle_edge_irq);
0567     irq_set_chip_data(irq, d->host_data);
0568     irq_set_noprobe(irq);
0569     return 0;
0570 }
0571 
0572 static const struct irq_domain_ops pxa_irq_domain_ops = {
0573     .map    = pxa_irq_domain_map,
0574     .xlate  = irq_domain_xlate_twocell,
0575 };
0576 
0577 #ifdef CONFIG_OF
0578 static const struct of_device_id pxa_gpio_dt_ids[] = {
0579     { .compatible = "intel,pxa25x-gpio",    .data = &pxa25x_id, },
0580     { .compatible = "intel,pxa26x-gpio",    .data = &pxa26x_id, },
0581     { .compatible = "intel,pxa27x-gpio",    .data = &pxa27x_id, },
0582     { .compatible = "intel,pxa3xx-gpio",    .data = &pxa3xx_id, },
0583     { .compatible = "marvell,pxa93x-gpio",  .data = &pxa93x_id, },
0584     { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
0585     { .compatible = "marvell,mmp2-gpio",    .data = &mmp2_id, },
0586     { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
0587     {}
0588 };
0589 
0590 static int pxa_gpio_probe_dt(struct platform_device *pdev,
0591                  struct pxa_gpio_chip *pchip)
0592 {
0593     int nr_gpios;
0594     const struct pxa_gpio_id *gpio_id;
0595 
0596     gpio_id = of_device_get_match_data(&pdev->dev);
0597     gpio_type = gpio_id->type;
0598 
0599     nr_gpios = gpio_id->gpio_nums;
0600     pxa_last_gpio = nr_gpios - 1;
0601 
0602     irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
0603     if (irq_base < 0) {
0604         dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
0605         return irq_base;
0606     }
0607     return irq_base;
0608 }
0609 #else
0610 #define pxa_gpio_probe_dt(pdev, pchip)      (-1)
0611 #endif
0612 
0613 static int pxa_gpio_probe(struct platform_device *pdev)
0614 {
0615     struct pxa_gpio_chip *pchip;
0616     struct pxa_gpio_bank *c;
0617     struct clk *clk;
0618     struct pxa_gpio_platform_data *info;
0619     void __iomem *gpio_reg_base;
0620     int gpio, ret;
0621     int irq0 = 0, irq1 = 0, irq_mux;
0622 
0623     pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
0624     if (!pchip)
0625         return -ENOMEM;
0626     pchip->dev = &pdev->dev;
0627 
0628     info = dev_get_platdata(&pdev->dev);
0629     if (info) {
0630         irq_base = info->irq_base;
0631         if (irq_base <= 0)
0632             return -EINVAL;
0633         pxa_last_gpio = pxa_gpio_nums(pdev);
0634         pchip->set_wake = info->gpio_set_wake;
0635     } else {
0636         irq_base = pxa_gpio_probe_dt(pdev, pchip);
0637         if (irq_base < 0)
0638             return -EINVAL;
0639     }
0640 
0641     if (!pxa_last_gpio)
0642         return -EINVAL;
0643 
0644     pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
0645                          pxa_last_gpio + 1, irq_base,
0646                          0, &pxa_irq_domain_ops, pchip);
0647     if (!pchip->irqdomain)
0648         return -ENOMEM;
0649 
0650     irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
0651     irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
0652     irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
0653     if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
0654         || (irq_mux <= 0))
0655         return -EINVAL;
0656 
0657     pchip->irq0 = irq0;
0658     pchip->irq1 = irq1;
0659 
0660     gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
0661     if (IS_ERR(gpio_reg_base))
0662         return PTR_ERR(gpio_reg_base);
0663 
0664     clk = devm_clk_get_enabled(&pdev->dev, NULL);
0665     if (IS_ERR(clk)) {
0666         dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
0667             PTR_ERR(clk));
0668         return PTR_ERR(clk);
0669     }
0670 
0671     /* Initialize GPIO chips */
0672     ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
0673     if (ret)
0674         return ret;
0675 
0676     /* clear all GPIO edge detects */
0677     for_each_gpio_bank(gpio, c, pchip) {
0678         writel_relaxed(0, c->regbase + GFER_OFFSET);
0679         writel_relaxed(0, c->regbase + GRER_OFFSET);
0680         writel_relaxed(~0, c->regbase + GEDR_OFFSET);
0681         /* unmask GPIO edge detect for AP side */
0682         if (gpio_is_mmp_type(gpio_type))
0683             writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
0684     }
0685 
0686     if (irq0 > 0) {
0687         ret = devm_request_irq(&pdev->dev,
0688                        irq0, pxa_gpio_direct_handler, 0,
0689                        "gpio-0", pchip);
0690         if (ret)
0691             dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
0692                 ret);
0693     }
0694     if (irq1 > 0) {
0695         ret = devm_request_irq(&pdev->dev,
0696                        irq1, pxa_gpio_direct_handler, 0,
0697                        "gpio-1", pchip);
0698         if (ret)
0699             dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
0700                 ret);
0701     }
0702     ret = devm_request_irq(&pdev->dev,
0703                    irq_mux, pxa_gpio_demux_handler, 0,
0704                        "gpio-mux", pchip);
0705     if (ret)
0706         dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
0707                 ret);
0708 
0709     pxa_gpio_chip = pchip;
0710 
0711     return 0;
0712 }
0713 
0714 static const struct platform_device_id gpio_id_table[] = {
0715     { "pxa25x-gpio",    (unsigned long)&pxa25x_id },
0716     { "pxa26x-gpio",    (unsigned long)&pxa26x_id },
0717     { "pxa27x-gpio",    (unsigned long)&pxa27x_id },
0718     { "pxa3xx-gpio",    (unsigned long)&pxa3xx_id },
0719     { "pxa93x-gpio",    (unsigned long)&pxa93x_id },
0720     { "mmp-gpio",       (unsigned long)&mmp_id },
0721     { "mmp2-gpio",      (unsigned long)&mmp2_id },
0722     { "pxa1928-gpio",   (unsigned long)&pxa1928_id },
0723     { },
0724 };
0725 
0726 static struct platform_driver pxa_gpio_driver = {
0727     .probe      = pxa_gpio_probe,
0728     .driver     = {
0729         .name   = "pxa-gpio",
0730         .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
0731     },
0732     .id_table   = gpio_id_table,
0733 };
0734 
0735 static int __init pxa_gpio_legacy_init(void)
0736 {
0737     if (of_have_populated_dt())
0738         return 0;
0739 
0740     return platform_driver_register(&pxa_gpio_driver);
0741 }
0742 postcore_initcall(pxa_gpio_legacy_init);
0743 
0744 static int __init pxa_gpio_dt_init(void)
0745 {
0746     if (of_have_populated_dt())
0747         return platform_driver_register(&pxa_gpio_driver);
0748 
0749     return 0;
0750 }
0751 device_initcall(pxa_gpio_dt_init);
0752 
0753 #ifdef CONFIG_PM
0754 static int pxa_gpio_suspend(void)
0755 {
0756     struct pxa_gpio_chip *pchip = pxa_gpio_chip;
0757     struct pxa_gpio_bank *c;
0758     int gpio;
0759 
0760     if (!pchip)
0761         return 0;
0762 
0763     for_each_gpio_bank(gpio, c, pchip) {
0764         c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
0765         c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0766         c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
0767         c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
0768 
0769         /* Clear GPIO transition detect bits */
0770         writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
0771     }
0772     return 0;
0773 }
0774 
0775 static void pxa_gpio_resume(void)
0776 {
0777     struct pxa_gpio_chip *pchip = pxa_gpio_chip;
0778     struct pxa_gpio_bank *c;
0779     int gpio;
0780 
0781     if (!pchip)
0782         return;
0783 
0784     for_each_gpio_bank(gpio, c, pchip) {
0785         /* restore level with set/clear */
0786         writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
0787         writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
0788 
0789         writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
0790         writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
0791         writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
0792     }
0793 }
0794 #else
0795 #define pxa_gpio_suspend    NULL
0796 #define pxa_gpio_resume     NULL
0797 #endif
0798 
0799 static struct syscore_ops pxa_gpio_syscore_ops = {
0800     .suspend    = pxa_gpio_suspend,
0801     .resume     = pxa_gpio_resume,
0802 };
0803 
0804 static int __init pxa_gpio_sysinit(void)
0805 {
0806     register_syscore_ops(&pxa_gpio_syscore_ops);
0807     return 0;
0808 }
0809 postcore_initcall(pxa_gpio_sysinit);
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